Tunnel FET Based Non-Volatile Memory Boosted By Vertical Band-to-Band Tunneling
A tunnel field effect transistor (TFET), including a source region, a gate region, a channel region, and a drain region, the gate region including a gate stack, wherein an area of the source region that is facing the channel region is overlapped by the gate stack.
The present invention claims priority to the U.S. provisional patent application with the Ser. No. 62/358,202 that was filed on Jul. 5, 2016, the entire contents thereof being herewith incorporated by reference.
FIELD OF THE INVENTIONThe present invention relates to the field of Tunnel Field Effect Transistors (TFET), low voltage operation transistors, nanoscale transistors, and application of the same as non-volatile memory devices.
BACKGROUNDDue to their mode of operation Tunnel Field Effect Transistors (TFETs) have been proposed in reference [2] as steep slope switches able to reduce the voltage operation of logic circuits below 0.2V with reduced leakage current and improved switching energy efficiency. While high-performance TFETs exploit InAs-Si hetero-structures on nanowires, as shown in reference [3], the all-Si homo-junction TFET family appears primarily to have a very high ION/IOFF and the lowest IOFF as shown in reference [4] yet fail to achieve the requirements of ION. Due to its excellent reliability, charge-trapping silicon oxide-nitride-oxide-silicon (SONOS) NVM is a promising alternative to conventional floating-gate flash devices at the next 16-nm technology node, as shown in reference [5].
While reference [6] proposed a non-volatile memory with a TFET, they have used a conventional lateral tunneling nano-wire with limited performance of the TFET device and an oxide-nitride-oxide (ONO) stack. In a Tunnel FET the gate modulation of tunneling barrier is of great significance. In a conventional lateral TFET, the carriers tunneling from source to the channel are not aligned to the gate electric field which id vertical. Accordingly, only a part of the gate field is utilized in band to band tunneling of carriers. Thus it becomes evident that in order to have a better gate modulation in a TFET, the tunneling direction should be aligned to the gate electric field. Such TFETs, called “Line Tunneling” have their source region significantly overlapped by the gate as shown in reference [1]. It leads to optimal control of the carrier injection mechanism and results in the best modulation on the drain current levels. In such device architectures, the band-to-band (BTB) tunneling takes place from an inversion layer induced in the source by the gate field [1]. Such devices show much better sub threshold slope than lateral devices over a large gate voltage range.
An ideal optimized Tunnel FET structure is simulated with ONO stack to simulate its memory operation and compared with MOSFET based nonvolatile memory, as shown in reference [7]. We then demonstrate the nonvolatile memory operation on a simplified Tunnel FET architecture by fabricating it with a high-k Al2O3/HfO2/Al2O3 gate stack and experimentally show how vertical tunneling boosts the memory operation in NVM cells, as shown in reference [8].
However, despite all these advancements and improvements in the field of Tunnel FET, advanced devices are desired, specifically to improve upon the characteristics for non-volatile memory operation, for example to increase trapped charges for memory operation, and to better control the carrier injection. Therefore, novel Tunnel FET devices with substantially improved characteristics are desired.
SUMMARYAccording to one aspect of the present invention, a tunnel field effect transistor (TFET) is provided, including a source region, a gate region, a channel region, and a drain region, the gate region including a gate stack. Moreover, an area of the source region that is facing the channel region is overlapped by the gate stack.
According to another aspect of the present invention, a method for operating a tunnel field effect transistor in a non-volatile memory device is provided. Preferably, the tunnel field effect transistor includes a source region, a gate region, a channel region, and a drain region, the gate region including a gate stack, wherein an area of the source region that is facing the channel region is overlapped by the gate stack. In addition, preferably the method includes the steps of performing a write operation, performing a read operation, and performing an erase operation.
According to yet another aspect of the present invention, a method for operating a tunnel field effect transistor in a non-volatile memory device is provided. Preferably, the tunnel field effect transistor includes a source region, a gate region, a channel region, a drain region, and a substrate, the gate region including a gate stack, wherein an area of the source region that is facing the channel region is overlapped by the gate stack. Moreover, the method preferably includes the step of operating the tunnel field effect transistor using vertical band-to-band tunneling to augment charge trapping in the gate stack.
According to still another aspect of the present invention, a vertical band-to-band tunneling operation is used due to the specific architecture of the Tunnel FET that allows to boost the charge storage in gate stack, as compared to the background art non-volatile MOSFET memories and background art lateral Tunnel FET memories, and offers stability at elevated temperatures.
The above and other objects, features and advantages of the present invention and the manner of realizing them will become more apparent, and the invention itself will best be understood from a study of the following description with reference to the attached drawings showing some preferred embodiments of the invention.
The accompanying drawings, which are incorporated herein and constitute part of this specification, illustrate the presently preferred embodiments of the invention, and together with the general description and the tables given above and the detailed description given below, serve to explain features of the invention.
Table I shows a summary of relevant patents and publications of non-volatile memory devices;
Table II shows non-volatile memory (NVM) parameter comparison of recent devices;
Table III lists the parameters of the device that has been simulated; and
Table IV shows the programming scheme for a p-type device.
Herein, identical reference numerals are used, where possible, to designate identical elements that are common to the figures. Also, the images are simplified for illustration purposes and may not be depicted to scale.
BRIEF DESCRIPTION OF THE SEVERAL EMBODIMENTSA nonvolatile memory device using Tunnel Field Effect Transistor (TFET) rather than conventional Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is provided. The nonvolatile memory device is realized using a unique architecture, with source of the device underlapping the gate of the Tunnel FET resulting in the alignment of the gate electric field to both the Fowler-Nordheim (FN) tunneling field and the Band-to-Band (BTB) tunneling direction. This field alignment results in the generation of BTB carriers just under the gate oxide in addition to the inversion carriers and thus provides enhanced charge injection into the used high-K oxides charge trapping gate stack.
As shown in
Next, the principle of the Tunnel FET memory operation is explained. The memory operation is based on the generation of band-to-band carriers just under the gate oxide stack. These carriers are available for tunneling right under the gate stack. When a suitable program/erase voltage is applied on the gate these carriers either tunnel into or out of the charge trap layer through tunneling oxide. Because the tunneling direction is now aligned to the component of the electric field modulated by the gate, this device offers good control of the carrier injection mechanism and a strong modulation on the drain current levels, as shown in reference
Choice of suitable oxide stack is critical for non volatile memory operation. The tunneling oxide should be thin enough to allow Fowler-Nordheim (FN) tunneling of BTB carriers into the gate stack on application of suitable program/erase voltage at gate stack. Similarly, the blocking oxide should be thick enough to prevent carrier injection from the gate into the gate stack throughout the program/erase voltage range. The charge trap layer should have appropriate conduction and valence band offset with respect to the tunneling oxide and blocking oxide so that it facilitates charge storage in the charge trap layer.
According to one aspect, the Tunnel FET device is a p-type device due to its doping scheme and hence the programming scheme of the memory is such that the programming voltage is Vp=−9V and the erase voltage is VE=8V, as shown in Table IV. During the programming phase, electrons are trapped inside the nitride layer instead of holes and the programmed ID-Vg (Drain current vs gate voltage) curve is shifted towards low negative gate voltages.
Next, the TCAD simulation of the memory operation of the proposed Tunnel FET is explained, according to an aspect of the present invention. The proposed memory operation is simulated with Sentaurus™ TCAD on a gated p+/i/n+ (highly doped p-type/insulator/highly doped n-type) structure, as exemplarily illustrated in
The SONOS structure and the TFET-based non-volatile memory have been created using Sentaurus™ Structure Editor. In both cases the gate stack consists of a 1.8 nm SiO2 layer, an 8.0 nm Si3N4 layer, and a 4.0 nm SiO2 layer between the channel area and the poly-silicon gate. In the case of the TFET-based structure the silicon substrate has been substituted with a thick buried oxide layer and a 20 nm thick silicon epitaxial layer (SOI TFET) in order to avoid perturbations to the TFET current levels because of the substrate contact. Source and drain in the MOS based structure are doped with a Gaussian profile of Arsenic (1020 cm−3), while the substrate is doped uniformly with boron (1016 cm−3). In case of the TFET, the source doping was kept at 1020 cm−3, the channel area and the SiGe (Silicon-Germanium with 30% Germanium) part as kept undoped (1015 cm−3,) and the drain was lowly doped at 1019 cm−3. The choice of a lower drain doping is needed to reduce the unwanted ambipolar behavior of TFET.
Sentaurus Device is also used to simulate the program and erase cycle of both the devices and to simulate the ID-VG curves during the read cycle. The single programming cycle is composed of a write phase, a hold phase of 2.5 msec, an erase phase and an hold phase of 5 msec. In the write phase for a p-type device a voltage of 9 V is applied to the gate contact for 0.5 msec, in the erase phase a voltage of −8 V is applied for 7.5 msec and in the hold phases no voltage is applied. The programming voltages of a n-type device will be of opposite polarity. The programming scheme for a p-type device is also shown in Table IV.
The program and erase operations were conducted within a single transient simulation by varying the gate voltage, then the final program and erase states are saved at the end of a series of programming cycles to obtain the steady-state solution. In order to facilitate the convergence of the simulation, especially in case of the TFET-based memory, the meshing strategy in the gate stack has been designed to result in a high-quality mesh without excessive node counts. The rest of the meshing strategy has been defined using regular refinement boxes, which specify the allowed minimum and maximum mesh spacing within a specified area. For more details on the simulation models used refer to the example project in Sentaurus Workbench SONOS Memory by Synopsys™, TCAD user guide Ver: I 2014.09.
The simulation of two programming cycles for a p-type TFET as shown in
It is interesting to notice, as shown in
This increased trapped charges ultimately translates into a bigger memory window, when the memory cell is read after a write or erase operation. When the gate voltage is swept from 0 V to +8(−9) V, the two curves present a spike which is due the opening of a wide B2B tunneling window at the source/channel interface. The large number of electrons (holes), generated in the SiGe via band-to-band tunneling, is available to tunnel through the bottom oxide into the nitride layer. As soon as the concentration of trapped electrons (holes) increases, the negative (positive) charges inside the nitride layer has the effect of screening the positive (negative) voltage applied to the gate contact and consequently reduces the tunneling window both at the source/channel interface and at the channel/bottom oxide interface. This explains the decreasing trend for both the barrier tunneling curves even if the gate voltage is fixed at +9(−8) V.
During the reading phase, the gate bias is swept from zero 0 V to +(−) 6 V for n(p)-type, the source is grounded and the drain is fixed at +(−)1.0 V. The ID-VG curves of program and erase states are plotted in
The most significant result is that the modified programming scheme and the bigger number of trapped holes due to the band-to-band-tunneling generation (boosting effect) cause a threshold voltage shift of 2.6V, which is higher of the corresponding value (2V) for the traditional MOSFET based SONOS flash memory.
Next, experimental results of non-volatile memory device are discussed. A device was fabricated without the epitaxial SiGe layer, as shown in the simulated design of
Such vertical devices without epitaxial layer have been demonstrated and predicted to have good characteristics, for example as discussed in reference [10]. In the fabricated device, with architectures as shown in
As shown in
The absence of a low band gap epitaxial layer above the source does affects the device working in certain way. Devices with low bandgap SiGe epitaxial layer are advantageous over the devices with just source-gate overlap, see
In accordance with another aspect of the present invention, with respect to the programming scheme or method, the following sequence can be used. (i) WRITE—The writing operations on the fabricated device was carried out by applying a pulse of −15V the at the gate for 10 μs, with drain, source and substrate all grounded. (ii) READ—The read operation was carried out at gate bias of −2V and drain voltage at −2V with source and substrate grounded. (iii) ERASE—The erase operation was carried out by applying a pulse of +15V at the gate for 10 μs, with drain, source and substrate all grounded. The WRITE cycle includes essentially the application of very high inverting voltage at the gate electrode, that leads to charge inversion in the channel, negative in case of p-type TFET, leading to tunneling of carriers into the charge trapping layer (HfO2) through the tunneling oxide (thinner Al2O3) from the underlapping highly doped source region or from the intrinsic Silicon-Germanium channel in case of device with SiGe epitaxy. In READ cycle we apply sufficient inverting voltage at the gate so that the device turns on but there is no carrier tunneling into the gate stack, thus the effect of WRITE/ERASE operations can be investigated by measuring this drain current. The ERASE cycle includes an application of high non inverting voltage such that it leads to tunneling of carriers into the charge trap layer just like in WRITE cycle but the carriers are of opposite polarity, thus they neutralize the previous stored charge during WRITE cycle.
Next, a NVM memory characterization is provided. Extensive DC and transient characterizations were performed on the fabricated NVM TFETs, showing well behaved TFETs with low Ioff current (<1 pA/μm).
As shown in
Regarding the retention characteristics,
In sum, the main advantages of proposed Tunnel FET based non-volatile memory include the following features: (1) Being a Tunnel FET based memory, the transfer characteristics of the memory transistor does not directly depend on temperature and less sensitive over wide range of temperatures as compared to the MOSFET based nonvolatile memories. (2) The gate-source overlap architecture of the device offers superior carrier generation and charge injection into the gate stack at a given voltage as compared to MOSFETs, thus enabling efficient memory operation. (3) The high-K gate stack offer better charge trapping and retention than silicon nitride below 4 nm of thickness. Thus high-K gate stack allows for more aggressive scaling for state of the art technology nodes. (4) High hysteresis, low voltage operation and temperature insensitivity allows for the proposed memory device to find application is demanding operating environment. A brief overview of different parameters is given by Table II, to compare with the devices of reference [6], [8], and [12]. Moreover, Table I provides for a brief overview a summary of relevant patents and publications of non-volatile memory devices.
A nonvolatile memory device based on Tunnel FET that can operate at comparatively lower voltages and has stable memory operation up to 125° C. and program/erase cycles greater than 106 has been shown. The device and its method of operation can help promote a more durable, efficient and robust nonvolatile memory function as a replacement for current Flash based solutions for military grade specifications.
While the invention has been disclosed with reference to certain preferred embodiments, numerous modifications, alterations, and changes to the described embodiments, and equivalents thereof, are possible without departing from the sphere and scope of the invention. Accordingly, it is intended that the invention not be limited to the described embodiments, and be given the broadest reasonable interpretation in accordance with the language of the appended claims.
REFERENCES
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Claims
1. A tunnel field effect transistor, comprising:
- a source region, a gate region, a channel region, and a drain region, the gate region including a gate stack,
- wherein an area of the source region that is facing the channel region is overlapped by the gate stack.
2. The tunnel field effect transistor according to claim 1, wherein the gate stack includes a first SiO2 layer, a Si3N4 layer, and a second SiO2 layer.
3. The tunnel field effect transistor according to claim 1, wherein the gate stack includes a first Al2O3 layer, a HfO2 layer, and a second Al2O3 layer.
4. The tunnel field effect transistor according to claim 1, further comprising:
- a low bandgap SiGe epitaxial layer arranged between the source region and the gate stack, in the overlapped area and in an intrinsic silicon area.
5. The tunnel field effect transistor according to claim 1, wherein an upper surface of the channel region is at least partially covered by the gate stack.
6. The tunnel field effect transistor according to claim 1, operated as a non-volatile memory device.
7. A method for operating a tunnel field effect transistor in a non-volatile memory device, the tunnel field effect transistor including a source region, a gate region, a channel region, a drain region, and a substrate, the gate region including a gate stack, wherein an area of the source region that is facing the channel region is overlapped by the gate stack, the method comprising the steps of:
- performing a write operation;
- performing a read operation; and
- performing an erase operation
8. The method according to claim 7, wherein the write operation includes a step of applying a negative voltage pulse to the gate region while the drain region, the source region, and the substrate are grounded.
9. The method according to claim 7, wherein the read operation includes a step of applying a negative bias to the gate region and a negative voltage to the drain region, while the source region and the substrate are grounded.
10. The method according to claim 7, wherein the erase operation includes a step of applying a positive voltage pulse to the gate region while the drain region, the source region, and the substrate are grounded.
11. A method for operating a tunnel field effect transistor in a non-volatile memory device, the tunnel field effect transistor including a source region, a gate region, a channel region, a drain region, and a substrate, the gate region including a gate stack, wherein an area of the source region that is facing the channel region is overlapped by the gate stack, the method comprising the step of:
- operating the tunnel field effect transistor using vertical band-to-band tunneling to augment charge trapping in the gate stack.
Type: Application
Filed: Jul 5, 2017
Publication Date: Jan 11, 2018
Inventors: Arnab Biswas (Munchen), Saurabh Tomar (Echandens), Adrian Mihai Ionescu (Ecublens)
Application Number: 15/641,472