METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE
A method of manufacturing a semiconductor package includes forming a preliminary package, on a supporting substrate, which includes a connection substrate, a semiconductor chip and a molding pattern on the connection substrate and the semiconductor chip, forming a buffer pattern on the molding pattern, and forming a carrier substrate, on the buffer pattern, which includes a first portion contacting the buffer pattern and a second portion contacting the molding pattern.
This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2016-0117915, filed on Sep. 13, 2016 in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety.
TECHNICAL FIELDExample embodiments of the present disclosure relate to methods of manufacturing the semiconductor package, more specifically, to methods of forming and removing a carrier substrate.
DISCUSSION OF THE RELATED ARTA semiconductor package can be manufactured by mounting a semiconductor chip on a printed circuit board substrate and electrically connecting the semiconductor chip to the printed circuit board substrate by, for example, a bonding wire or a bump. As demand for highly functional, higher speed, smaller electronic components increases with developments of the electronics industry, mounting methods in which multiple semiconductor chips are stacked on a single package substrate, or methods of stacking packages on one another, have emerged.
SUMMARYAccording to example embodiments of the inventive concepts, a method of manufacturing a semiconductor package may include forming a preliminary package on a supporting substrate, which includes a connection substrate, a semiconductor chip and a molding pattern on the connection substrate and the semiconductor chip, forming a buffer pattern on the molding pattern, and forming a carrier substrate on the buffer pattern and the molding pattern, which includes a first portion contacting the buffer pattern and a second portion contacting the molding pattern.
According to example embodiments of the inventive concepts, a method of manufacturing a semiconductor package may include providing a preliminary package which includes a connection substrate, a semiconductor chip and a molding pattern, providing a buffer pattern on a first portion of the molding pattern, which exposes an upper surface of a second portion of the molding pattern, providing a carrier substrate on the buffer pattern and the molding pattern, which contacts the upper surface of the second portion of the molding pattern, and removing the second portion of the molding pattern to detach the carrier substrate from the molding pattern.
According to example embodiments of the inventive concepts, a method of manufacturing a semiconductor package may include forming a package on a supporting substrate, which includes a connection substrate including openings exposing the supporting substrate, semiconductor chips in respective ones of the openings and a molding pattern covering the supporting substrate and the semiconductor chips, forming a buffer pattern on the package, which exposes the molding pattern, and forming a carrier substrate on the buffer pattern and the molding pattern, which contacts an upper surface of the buffer pattern and an upper surface of the exposed molding pattern.
According to example embodiments of the inventive concepts, a method of manufacturing a semiconductor package may include providing connection substrate on a supporting substrate, wherein the connection substrate has a plurality of openings. A semiconductor chip may be arranged on the supporting substrate and in each of the plurality of openings of the connection substrate. A molding pattern may be formed to cover an upper surface of each semiconductor chip and an upper surface of the connection substrate. A carrier substrate may be arranged on the molding pattern such that the carrier substrate extends over the upper surface of each semiconductor chip and the upper surface of the connection substrate. The carrier substrate may be spaced apart from the molding pattern at a region over the upper surface of each semiconductor chip, and may be adhered to the molding pattern at a region over the upper surface of connection substrate. After the carrier substrate is arranged as discussed above, the supporting substrate may be removed.
Various example embodiments will now be described more fully with reference to the accompanying drawings in which some example embodiments are shown. However, the concepts described herein may be embodied in many alternate forms and should not be construed as limited to only example embodiments set forth herein.
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The connection substrate 200 may be disposed on the supporting substrate 100. The connection substrate 200 may be attached on the supporting substrate 100 by an adhesion layer 110. As an example, the connection substrate 200 may include a printed circuit board (PCB) substrate. The connection substrate 200 may include base layers 210 and a conductive member 220. The base layers 210 may include a non-conductive material. In an embodiment, the base layers 210 may include a silicone-based material, a polymer, or the like or any combination thereof. The conductive member 220 may be disposed in the base layers 210. The conductive member 220 may include a first pad 221, a wiring pattern 222, vias 223 and a second pad 224. The first pad 221 may be disposed on a lower surface 200b of the connection substrate 200. The vias 223 may penetrate the base layers 210. The wiring pattern 222 may be disposed between the base layers 210 and may be directly connected to the vias 223. The second pad 224 may be disposed on an upper surface 200a of the connection substrate 200 may be connected to at least one of the vias 223. The second pad 224 may not be aligned with the first pad 221 in a third direction D3. The third direction D3 may be a direction vertical to the lower surface 200b of the connection substrate 200. A first direction D1 and a second direction D2 may be parallel to the lower surface 200b of the connection substrate 200. The first direction D1 may cross the second direction D2.
The conductive member 220 may include a metal such as copper, aluminum, nickel, etc., or an alloy thereof. Openings 250 may be formed in the connection substrate 200. The openings 250 may expose the supporting substrate 100.
The first semiconductor chips 300 may be provided on the supporting substrate 100. The first semiconductor chips 300 may be provided in the first regions R1, respectively, of the preliminary package P. The first semiconductor chips 300 may be disposed in the openings 250, respectively, of the connection substrate 200. The connection substrate 200 may surround the respective first semiconductor chips 300. Chip pads 350 may be disposed on a lower surface 300b of each of the semiconductor chips 300.
The molding pattern 400 may be formed on the upper surface 200a of the connection substrate 200 and upper surfaces 300a of the first semiconductor chips 300. The molding pattern 400 may extend in or fill gaps between the connection substrate 200 and the first semiconductor chips 300. The molding pattern 400 may include a soft material, for example, an insulating polymer. The molding pattern 400 may be formed using, for example, a polymer sheet. In some embodiments, the molding pattern 400 may include a build-up film or laminated multiple layers.
The molding pattern 400 may include a first portion 410 and a second portion 420. When viewed in plan view, the first portion 410 of the molding pattern 400 may be disposed on the central region of the preliminary package P and may overlap the plurality of first regions R1. When viewed in plan view, the second portion 420 of the molding pattern 400 may overlap the second region R2. The second portion 420 of the molding pattern 400 may be connected to the first portion 410 of the molding pattern 400.
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The supporting substrate 100 and the adhesion layer 110 may be removed (e.g., as indicated by the dashed lines) to expose a lower surface of the preliminary package P, for example, the lower surfaces 300b of the first semiconductor chips 300 and the lower surface 200b of the connection substrate 200.
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An external terminal 730 may be formed on a lower surface of the first substrate 700. The external terminal 730 may be connected to the redistribution pattern 720. The external terminal 730 may include a metal. The external terminal 730 may include a solder ball. The external terminal 730 may be electrically connected to the second pad 224 by the redistribution pattern 720 and the conductive member 220. The external terminal 730 may not be aligned with the second pad 224 in the third direction D3. The number of external terminals 730 may be different from the number of the second pad 224. An arrangement freedom degree of the second pad 224 may be increased by the conductive member 220 and the redistribution pattern 720.
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A connection terminal 900 (e.g., a solder bump) may be formed between the first package P1 and the second package P2. The connection terminal 900 may be connected to the second substrate 800 and the second pad 224. The second package P2 may be electrically connected to the first package P1 by the connection terminal 900.
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Thereafter, a first removing process of the carrier substrate 600 may be performed. For example, the first removing process of the carrier substrate 600 may be performed by treating chemicals on sidewalls of the molding pattern 400. The chemicals may react with the molding pattern 400, and thus a second portion 420 of the molding pattern 400 may be removed (as indicated by the region enclosed by the dashed lines). Thereafter, the carrier substrate 600 may be separated from the molding pattern 400 and may be detached from the preliminary package P.
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A buffer pattern 500 and a carrier substrate 600 may be disposed on the preliminary package P. A first substrate 700 may be formed on lower surfaces 300b of first semiconductor chips 300 and a lower surface 200b of a connection substrate 200.
A test pad 740 may be formed on a lower surface of the first substrate 700 in the dummy region DR. The test pad 740 may be electrically connected to a redistribution pattern 720. A test circuit may be disposed in the connection substrate 200 in the dummy region DR. The test circuit may be electrically connected to the test pad 740.
An electrical connection of the first substrate 700 may be tested. For example, a probe may be in contact with the test pad 740 to test an electrical connection of the redistribution pattern 720. The test of the electrical connection of the redistribution pattern 720 may include a test of an electrical short circuit or disconnection.
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After the formation of the first substrate 700, a carrier substrate 600 and a buffer pattern 500 may be removed. A preliminary package P and the carrier substrate 600 may be sawed to separate a second region R2 of the preliminary package P and the carrier substrate 600 from first regions R1 of the preliminary package P, thereby removing the second region R2 of the preliminary package P and the carrier substrate 600 from the preliminary packager P.
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While the present inventive concepts have been particularly shown and described with reference to example embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the following claims.
Claims
1. A method of manufacturing a semiconductor package, the method comprising:
- forming a preliminary package on a supporting substrate, the preliminary package including a connection substrate, a semiconductor chip and a molding pattern on the connection substrate and the semiconductor chip;
- forming a buffer pattern on the molding pattern; and
- forming a carrier substrate on the buffer pattern and the molding pattern, the carrier substrate including a first portion contacting the buffer pattern and a second portion contacting the molding pattern.
2. The method according to claim 1, wherein the buffer pattern includes a non-adhesive material.
3. The method according to claim 1, further comprising removing the carrier substrate,
- wherein removing the carrier substrate includes:
- a first removing process of removing the second portion of the carrier substrate by performing a sawing process on the carrier substrate: and
- a second removing process of separating the carrier substrate from the buffer pattern.
4. The method according to claim 3, further comprising:
- removing the supporting substrate to expose a lower surface of the preliminary package; and
- forming a redistribution substrate on the lower surface of the preliminary package,
- wherein removing the carrier substrate is performed after forming the redistribution substrate.
5. The method according to claim 4, wherein the redistribution substrate includes insulating patterns and a redistribution pattern.
6. The method according to claim 5, wherein the redistribution pattern is electrically connected to the semiconductor chip and the connection substrate.
7. The method according to claim 1, wherein the second portion of the carrier substrate is overlapped with an edge region of the preliminary package in plan view.
8. A method of manufacturing a semiconductor package, the method comprising:
- providing a preliminary package, the preliminary package including a connection substrate, a semiconductor chip and a molding pattern;
- providing a buffer pattern on a first portion of the molding pattern, the buffer pattern exposing an upper surface of a second portion of the molding pattern;
- providing a carrier substrate on the buffer pattern and the molding pattern, the carrier substrate contacting the upper surface of the second portion of the molding pattern; and
- removing the second portion of the molding pattern to detach the carrier substrate from the molding pattern.
9. The method according to claim 8, wherein the carrier substrate is attached to the preliminary package by the second portion of the molding pattern.
10. The method according to claim 8, further comprising, after detaching the carrier substrate, removing the carrier substrate from the preliminary package.
11. The method according to claim 10, further comprising, after removing the carrier substrate, disposing an upper package on the molding pattern,
- wherein the connection substrate includes a base layer and a conductive member in the base layer, and
- wherein the upper package is electrically connected to the conductive member.
12. The method according to claim 8, wherein the second portion of the molding pattern is provided in an edge region of the preliminary package.
13. The method according to claim 8, wherein removing the second portion of the molding pattern includes sawing the carrier substrate and the preliminary package to separate the second portion of the molding pattern from the first portion of the molding pattern.
14. The method according to claim 8, wherein removing the second portion of the molding pattern includes chemically etching a sidewall of the preliminary package.
15. The method according to claim 8, wherein after providing the carrier substrate, the upper surface of the second portion of the molding pattern is substantially coplanar with an upper surface of the buffer pattern.
16. A method of manufacturing a semiconductor package, the method comprising:
- forming a package on a supporting substrate, the package including a connection substrate including openings exposing the supporting substrate, semiconductor chips in respective ones of the openings and a molding pattern covering the supporting substrate and the semiconductor chips;
- forming a buffer pattern on the package, the buffer pattern exposing the molding pattern; and
- forming a carrier substrate on the buffer pattern and the molding pattern, the carrier substrate contacting an upper surface of the buffer pattern and an upper surface of the exposed molding pattern.
17. The method according to claim 16, wherein the buffer pattern includes a non-adhesive material.
18. The method according to claim 16, wherein the buffer pattern includes a plurality of buffer patterns spaced apart from each other, and
- wherein the molding pattern is present in a gap between the buffer patterns.
19. The method according to claim 16, further comprising forming a substrate on a lower surface of the package,
- wherein the substrate includes first regions overlapped with the semiconductor chips, respectively, when viewed in plan view, and a dummy region between the first regions, and
- wherein a test pad and/or an alignment key is formed in the dummy region of the substrate.
20. The method according to claim 16, wherein the carrier substrate contacts the molding pattern in an edge region of the package.
21-28. (canceled)
Type: Application
Filed: Apr 6, 2017
Publication Date: Mar 15, 2018
Inventors: Kyoung Hwan KIM (Yongin-si), Taewoo KANG (Suwon-si), Byung Lyul PARK (Seoul), Hyungjun JEON (Seoul)
Application Number: 15/481,446