SEMICONDUCTOR DEVICES, MEMORY DIES AND RELATED METHODS
A semiconductor substrate is provided. Active areas and trench isolation regions are formed. The active areas extend along a first direction. Buried word lines extending along a second direction are formed in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. Buried digit lines extending along a third direction are formed above the buried word lines. An upper portion of the trench isolation region is removed to form an L-shaped recessed area around each of the cell contact areas. The L-shaped recessed area exposes sidewalls of the cell contact areas. An epitaxial silicon growth process is then performed to grow an epitaxial silicon layer from the exposed sidewalls and a top surface of each of the cell contact areas, thereby forming enlarged cell contact areas.
This is a continuation of U.S. patent application Ser. No. 15/253,894, filed Sep. 1, 2016, pending, which is a divisional of U.S. patent application Ser. No. 15/002,401, filed Jan. 21, 2016, pending, the disclosure of each of which is hereby incorporated herein in its entirety by this reference.
TECHNICAL FIELDThis disclosure relates generally to semiconductor memory devices and a method of fabricating the same. More particularly, the present disclosure relates to a memory device including buried (or damascened) digit lines (BDLs)/buried word lines (BWLs), as well as enlarged cell contact areas, in the cell array, and a method of fabricating the same.
BACKGROUNDAs known in the art, a dynamic random access memory (DRAM) device is made up of memory cells. Each cell of a DRAM device comprises a transistor and a capacitor electrically coupled to a terminal such as the drain (or source) of the transistor. A digit line is electrically coupled to another terminal such as the source (or drain) of the transistor. The memory cells are addressed via a word line and the digit line, one of which addresses a “column” of memory cells while the other addresses a “row” of the memory cells.
One type of the typical DRAM device utilizes buried word line (BWL) architecture comprising parallel word lines embedded in a cell array. The buried word lines are fabricated in word line trenches that intersect with the active areas (AAs). The capacitor is stacked on a major surface of the silicon substrate and the digit line is constructed over the major surface of the silicon substrate and over the capacitor.
As the size of DRAM cell shrinks, the surface area of the AA becomes smaller and smaller. The decreasing surface area of the AAs results in insufficient cell contact area (or landing area) for the capacitors and decreased process window when forming a cell contact layer (or landing pad). Additionally, there is a continuing goal to further decrease the cell area. Therefore, it has become a major issue in this technical field to cope with the insufficient cell contact area and narrow process window.
BRIEF SUMMARYIt is one object of the disclosure to provide an improved DRAM device comprised of a plurality of memory cells having an effective cell size of 6F2 and an enlarged cell contact area.
It is another object of the disclosure to provide an improved DRAM device having buried digit lines/word lines and a capacitor-over-digit line structure.
It is another object of the disclosure to provide a method for fabricating a DRAM device without the need of forming a cell contact layer or a landing pad.
According to one embodiment of the disclosure, a method for fabricating a memory array is disclosed. A semiconductor substrate is provided. A plurality of active areas and a trench isolation region isolating the plurality of active areas from one another are formed. The active areas extend along a first direction. Buried word lines extending along a second direction are formed in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into three portions including a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. Buried digit lines extending along a third direction in the semiconductor substrate are formed above the buried word lines. The third direction is substantially perpendicular to the second direction. An upper portion of the trench isolation region is selectively removed to form an L-shaped recessed area around each of the two cell contact areas. The L-shaped recessed area exposes sidewalls of each of the two cell contact areas. An epitaxial silicon growth process is then performed to grow an epitaxial silicon layer from the exposed sidewalls and a top surface of each of the cell contact areas, thereby forming enlarged cell contact areas.
According to one aspect of the disclosure, a memory array is disclosed. The memory array includes a semiconductor substrate having thereon a plurality of active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active area into three portions including a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. Buried digit lines extend along a third direction in the semiconductor substrate above the buried word lines. The third direction is substantially perpendicular to the second direction. An epitaxial silicon layer extends from exposed sidewalls and a top surface of each of the cell contact areas.
These and other objectives of the present disclosure will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various drawings.
The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute a part of this specification. The drawings illustrate some of the embodiments and, together with the description, serve to explain their principles. In the drawings:
It should be noted that all the figures are diagrammatic. Relative dimensions and proportions of parts of the drawings have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same reference numerals are generally used to refer to corresponding or similar features in modified and different embodiments.
DETAILED DESCRIPTIONIn the following detailed description of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the disclosure. Other embodiments may be utilized and structural changes may be made without departing from the scope of the present disclosure.
The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present disclosure is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled. One or more implementations of the present disclosure will now be described with reference to the attached drawings, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures are not necessarily drawn to scale.
The terms “wafer” and “substrate” used herein include any structure having an exposed surface onto which a layer is deposited according to the present disclosure, for example, to form the integrated circuit (IC) structure. The term “substrate” is understood to include semiconductor wafers. The term “substrate” is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art.
The term “horizontal” as used herein is defined as a plane parallel to the conventional major plane or surface of the semiconductor substrate, regardless of its orientation. The term “vertical” refers to a direction perpendicular to the term horizontal as just defined. Terms, such as “on,” “above,” “below,” “bottom,” “top,” “side” (as in “sidewall”), “higher,” “lower,” “over,” and “under,” are defined with respect to the horizontal plane.
The present disclosure pertains to an improved DRAM device that is comprised of a plurality of memory cells having an effective cell size of 6F2 (e.g., 3F×2F) and an enlarged cell contact area. The enlarged cell contact area involves the use of inventive self-constrained epitaxial growth technology, which effectively avoids shorting between neighboring cells.
The width of the feature is also referred to as the CD or minimum feature size (“F”) of the line. The CD is typically the smallest geometrical feature, such as the width of an interconnect line, contact, or trench, that is formed during IC manufacturing using a given technology, such as photolithography.
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According to the embodiment, the L-shaped recessed area 420 is not filled up with the epitaxial silicon layer 52, leaving a gap between the epitaxial silicon layer 52 and the adjacent BDL trenches 22 and the BWL trenches 160 (
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Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the disclosure. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims
1. A semiconductor device, comprising:
- a semiconductor substrate including active areas;
- an isolation region;
- buried word lines extending along the semiconductor substrate, at least one of the buried word lines and the isolation region intersecting with at least one of the active areas, the at least one of the buried word lines and the isolation region separating the at least one of the active areas into at least two portions including at least one cell contact area and a digit line contact area;
- buried digit lines extending along the semiconductor substrate, at least one of the buried digit lines positioned adjacent to the digit line contact area; and
- an epitaxial silicon material adjacent to the at least one cell contact area, wherein the epitaxial silicon material has a top surface higher than a top surface of the buried digit lines.
2. The semiconductor device of claim 1, wherein the isolation region comprises isolation regions positioned between each of the active areas.
3. The semiconductor device of claim 1, wherein the at least one of the buried word lines and the isolation region separates the at least one of the active areas into three portions.
4. The semiconductor device of claim 3, wherein the three portions of the at least one of the active areas comprises two cell contact areas and the digit line contact area.
5. The semiconductor device of claim 1, wherein each of the buried word lines intersects with at least one of the active areas.
6. The semiconductor device of claim 1, wherein the active areas extend along a first direction and the buried word lines extend along a second direction transverse to the first direction.
7. The semiconductor device of claim 6, wherein the buried digit lines extend along a third direction transverse to the second direction.
8. The semiconductor device of claim 1, wherein the top surface of the buried digit lines is flush with a top surface of the at least one cell contact area.
9. The semiconductor device of claim 1, wherein the epitaxial silicon material extends from at least one exposed sidewall and a top surface of the at least one cell contact area.
10. A memory die, comprising:
- a semiconductor substrate including active areas;
- word lines extending along the semiconductor substrate, the word lines intersecting with at least one of the active areas, at least one of the word lines separating the at least one of the active areas into at least two portions including at least one cell contact area and a digit line contact area;
- digit lines extending along the semiconductor substrate, at least one of the digit lines positioned adjacent to the digit line contact area; and
- a silicon material adjacent to the at least one cell contact area, wherein the silicon material has a top surface higher than a top surface of the digit lines.
11. The memory die of claim 10, wherein the digit lines intersect with the active areas at an acute angle.
12. The memory die of claim 10, further comprising a capacitor directly on the silicon material.
13. The memory die of claim 10, further comprising an isolation region separating the active areas.
14. The memory die of claim 13, further comprising an open recessed volume between the digit line contact area and the silicon material.
15. The memory die of claim 14, wherein the open recessed volume is directly over the isolation region.
16. A method for fabricating a semiconductor device, comprising:
- intersecting active areas of a semiconductor substrate with word lines extending along the semiconductor substrate;
- separating the at least one of the active areas into at least two portions including at least one cell contact area and a digit line contact area with the at least one of the word lines;
- extending digit lines along the semiconductor substrate;
- connecting at least one of the digit lines with the digit line contact area;
- positioning a silicon material adjacent to the at least one cell contact area; and
- defining the silicon material to exhibit a top surface higher than a top surface of the digit lines.
17. The method of claim 16, further comprising orienting the active areas along a first direction and the word lines along a second direction transverse to the first direction.
18. The method of claim 16, wherein separating the at least one of the active areas into the at least two portions comprises defining three portions including two cell contact areas and the digit line contact area.
19. The method of claim 16, further comprising positioning the top surface of the digit lines substantially flush with a top surface of the at least one cell contact area.
20. The method of claim 16, further comprising extending the silicon material from at least one exposed sidewall and a top surface of the at least one cell contact area.
Type: Application
Filed: Dec 1, 2017
Publication Date: Mar 22, 2018
Patent Grant number: 10847518
Inventor: Kuo-Chen Wang (New Taipei City)
Application Number: 15/829,420