TERMINATION FOR SINGLE-ENDED RECEIVER

Abstract

Described herein is a termination circuit for a receiver receiving a single-ended signal. The termination circuit includes the first stage having a low-pass transfer function having a first pole/zero pair, and a second stage coupled to the first stage, where the second stage has a high-pass transfer function having a second pole/zero pair that cancels out the first pole/zero pair.

Description

FIELD

The present disclosure relates to a low power transceiver device. In particular, examples described herein relate to a single-ended transceiver device for achieving high bandwidth and/or high density at low power. Examples described herein may be useful for ultra-short reach (USR) applications, and may also apply to ultra-short serializer/deserializers.

BACKGROUND

In terminating an output of electronic circuits, there are a few common approaches. Examples approaches are demonstrated in FIGS. 1A and 1B where the circuit is DC terminated by either pulling the output to ground, as shown in FIG. 1A, or pulling the output to a supply voltage V_DD, as shown in FIG. 1B. In these examples, the pull-up or pull-down resistor is labeled as R_RX. The DC termination typically provides good performance and return loss across all frequencies. Nevertheless, DC termination is generally avoided in circuits requiring low power due to the higher power consumption at the transmitting (TX) driver. DC termination also typically requires a reference voltage V_ref for defining the receiver (RX) slicing point (not shown) which also may change with swing of the output. This problem may be resolved with a simple resistor-capacitor (RC) circuit. However, at low data rates, such solution may exhibit problems with consecutive identical digits (CIDs). DC termination also typically exhibits an asymmetry in the eye (e.g. rise and fall times are different), which may cause the transmitter to also exhibit asymmetric properties.

Another approach to terminating the output of electronic circuits is AC coupled termination as demonstrated in FIGS. 1C and 1D. The approach presented in FIG. 1C provides AC termination that resolves some of the power consumption problems of DC termination by requiring only half the power. AC termination also requires no generation of a reference voltage. However, AC termination typically suffers from DC wander. As well, tracking CIDs, particularly at low data rates, typically requires a large capacitor (which may be too large for practical implementation). Further, AC termination may have poor low frequency termination.

The DC wander exhibited by FIG. 1C may be corrected by adding a voltage regulator 102, as shown in FIG. 1D. However, this is at the cost of higher power consumption for both the TX driver and RX regulator for singled-ended receiving. The voltage regulator 102 also requires area on the semiconductor device. The voltage regulator 102 may also become unstable in certain instances.

SUMMARY

The present disclosure describes circuits that may be useful for single-ended transceivers, including ultra-short reach (USR) transceivers (TXRX) where the goal is to achieve high bandwidth and high density at low power consumption. For example, a low power usage target may be less than about 2 pJ/bit, for example about 1.5 pJ/bit.

In some first examples, the present disclosure describes a termination circuit for a receiver receiving a single-ended signal, the termination circuit comprising:

• • a first stage for receiving input from an input port of the receiver, the first stage having a low-pass transfer function having a first pole/zero pair; and
  • a second stage for outputting to one or more further stages of the receiver, the second stage being coupled to the first stage, the second stage having a high-pass transfer function, the high-pass transfer function having a second pole/zero pair that cancels out the first pole/zero pair.

In one aspect of those examples, the first stage comprises a first resistor in series with a first capacitor, the first resistor and the first capacitor being coupled between the input port and ground.

In one aspect of those examples, the first resistor has a resistance of approximately 50 Ω+/−20%.

In one aspect of those examples, the first capacitor has a capacitance in the range of approximately 50 pF to approximately 500 pF.

In one aspect of those examples, the capacitance of the first capacitor is approximately 100 pF.

In one aspect of those examples, the second stage comprises a second capacitor coupled to the input port and an output of the termination circuit, and a second resistor in series with a third capacitor, the second resistor and the third capacitor being coupled between the output of the termination circuit and ground.

In one aspect of those examples, the second capacitor and the third capacitor have approximately equal capacitance.

In one aspect of those examples, wherein the first resistance, second resistance, first capacitance, and second capacitance are selected to satisfy the condition 2R₁C₁=R₂C₂, where R₁ is resistance of the first resistor, C₁ is capacitance of the first capacitor, R₂ is resistance of the second resistor, C₂ is capacitance of the second capacitor, and the third capacitor has capacitance approximately equal to capacitance of the second capacitor.

In one aspect of those examples, wherein R₁=50Ω, C₁=100 pF, C₂=1 pF, and R₂=10 kΩ.

In one aspect of those examples, wherein the termination circuit consumes power less than approximately 2 pJ/bit.

In some second examples, the present disclosure describes a receiver for receiving a single-ended signal, the receiver comprising:

• • an input port for receiving the single-ended signal;
  • a termination circuit comprising:
  • a first stage coupled to the input port of the receiver, the first stage having a low-pass transfer function having a first pole/zero pair; and
  • a second stage coupled to the first stage, the second stage having a high-pass transfer function, the high-pass transfer function having a second pole/zero pair that cancels out the first pole/zero pair; and
  • one or more further stages coupled to output of the termination circuit, for processing the single-ended signal.

In one aspect of those examples, the first stage of the termination circuit comprises a first resistor in series with a first capacitor, the first resistor and the first capacitor being coupled between the input port and ground.

In one aspect of those examples, wherein the second stage of the termination circuit comprises a second capacitor coupled between the input port and one of the one or more further stages, and a second resistor in series with a third capacitor, the second resistor and the third capacitor being coupled between the one of the one or more further stages and ground.

In one aspect of those examples, wherein the first resistance, second resistance, first capacitance, and second capacitance are selected to satisfy the condition 2R₁C₁=R₂C₂, where R₁ is resistance of the first resistor, C₁ is capacitance of the first capacitor, R₂ is resistance of the second resistor, C₂ is capacitance of the second capacitor, and the third capacitor has capacitance approximately equal to capacitance of the second capacitor.

In one aspect of those examples, the termination circuit consumes power less than approximately 2 pJ/bit.

In some third examples, the present disclosure describes a low-power communication device comprising a receiver, wherein the receiver comprises:

• • an input port of the receiver for receiving a single-ended signal;

a termination circuit comprising:

• • a first stage coupled to the input port of the receiver, the first stage having a low-pass transfer function having a first pole/zero pair; and
  • a second stage coupled to the first stage, the second stage having a high-pass transfer function, the high-pass transfer function having a second pole/zero pair that cancels out the first pole/zero pair; and
  • one or more further stages of the receiver coupled to output of the termination circuit, for processing the single-ended signal.

In one aspect of those examples, the first stage of the termination circuit comprises a first resistor in series with a first capacitor, the first resistor and the first capacitor being coupled between the input port and ground.

In one aspect of those examples, the second stage of the termination circuit comprises a second capacitor coupled between the input port and one of the one or more further stages, and a second resistor in series with a third capacitor, the second resistor and the third capacitor being coupled between the one of the one or more further stages and ground.

In one aspect of those examples, the first resistance, second resistance, first capacitance, and second capacitance are selected to satisfy the condition 2R₁C₁=R₂C₂, where R₁ is resistance of the first resistor, C₁ is capacitance of the first capacitor, R₂ is resistance of the second resistor, C₂ is capacitance of the second capacitor, and the third capacitor has capacitance approximately equal to capacitance of the second capacitor.

In one aspect of those examples, the termination circuit consumes power less than approximately 2 pJ/bit.

Additional aspects may become apparent to one of skill in the art and the common general knowledge in light of the disclosure presented herein.

BRIEF DESCRIPTION OF THE DRAWINGS

Reference will now be made, by way of example, to the accompanying drawings which show example embodiments of the present application, and in which:

FIG. 1A is a schematic diagram demonstrating a prior art DC termination with a pull-down resistor R_RX;

FIG. 1B is a schematic diagram demonstrating a prior art DC termination with a pull-up resistor R_RX;

FIG. 1C is a schematic diagram demonstrating a prior art low-pass filter termination;

FIG. 1D is a schematic diagram demonstrating a prior art low-pass filter termination with voltage regulation;

FIG. 2 is a schematic diagram of an example termination circuit with AC coupling termination;

FIG. 3 is a schematic diagram of example system including the termination circuit of FIG. 2; and

FIG. 4 is a simulated Bode diagram of the example system of FIG. 3.

Similar reference numerals may have been used in different figures to denote similar components.

DESCRIPTION OF EXAMPLE EMBODIMENTS

Examples described herein may be applicable to a single-ended USR TXRX that may enable high bandwidth at a low power. Examples described herein may also enable high density implementation on a chip. In some examples, a very low power usage may be achieved, which may be less than 2 pJ/bit, for example approximately 1.5 pJ/bit.

In order to achieve low power consumption, a transmitter may be designed to transmit signals as a single-ended mode signal rather than using differential signaling. Further, AC coupled RX termination may be preferable for low power consumption. Conventional AC coupled termination may be suitable for differential signals, because the common-mode of the differential signal is constant, however such approaches may not be suitable for single-ended signaling. In contrast to differential signaling, the RX termination common-mode in single-ended signaling is data-dependent, which may lead to DC wander and eye closure.

FIG. 2 is a schematic diagram of an example AC coupled RX termination circuit 200 that may address one or more of the challenges discussed above. The example termination circuit 200 may be implemented at a RX (which may be part of a TXRX), for example. The example circuit 200 provides a two-stage RX termination circuit that may have an all-pass (or near all-pass) transfer function. An input signal is received at an input port 204 of the RX, at a first stage 202 of the termination circuit 200. The first stage 202 may include a first resistor R₁ (which may be referred to as the RX termination resistor) in series with a first capacitor C₁, connecting the input port 204 to ground. The first resistor R₁ may have a resistance value that is selected to avoid or reduce far-end mismatch, for example having a resistance of 40-60Ω, or about 50Ω. The capacitance of the first capacitor may be selected to provide good return loss, and may be relatively large. The capacitance of the first capacitor may be selected dependent on the value of the first resistor R₁, and may be in the range of about 50 pF to about 500 pF, for example about 100 pF. This first stage 202 may have a low-pass transfer function which may result in inter-symbol interference (e.g., causing eye closure) and/or additive noise for single-ended input data.

The second stage 206 may include a second capacitor C₂ coupled to the input port 204 and an output port 208 of the termination circuit 200. The capacitance of the second capacitor may be selected dependent on the value of the resistance and capacitance values of the first stage 204, and may be in the range of about 500 fF to about 2 pF, for example about 1 pF. The output port 208 of the termination circuit 200 may be coupled to other stages of a RX for signal processing, for example a continuous time linear equalizer (CTLE), a gain stage, a boost stage, or a comparator. Within the termination circuit 200, the output port 208 is further coupled to a second resistor R₂ in series with a third capacitor C₃ connected to ground. The third capacitor C₃ may have the same capacitance value as second capacitor C₂. The second stage 206 may provide a high-pass transfer function having a pole/zero pair that cancels out the pole/zero pair of the first stage 204, resulting in a generally flat transfer function overall for the circuit 200, which reduces or eliminates DC wander for input data with long CIDs.

In general, the termination circuit 200 may be designed as two stages in which the pole/zero pair of the second stage 206 cancels out the pole/zero pair of the first stage 204, to result in a generally flat transfer function for the termination circuit 200.

In particular, the following conditions have been found to enable the termination circuit 200 to maintain a flat response:

C₂=C₃; and

2R₁C₁=R₂C₂

In order to meet these conditions, the ratio of the first and second resistors R₁ and R₂ may be matched with the ratio of the first and second capacitors C₁ and C₂ ratios. Although these meeting these conditions may ensure a flat response, a completely flat response may not be practical or necessary in practice. For example, the resistance and capacitance values of individual components may randomly vary (e.g., due to variations in manufacturing) by up to 20% from the nominal value. In the case where these ratios are not matched, the impact of such mismatch may be acceptable since simulations have shown that the impact of such mismatch typically occurs at lower frequencies. The size of the capacitors C₁, C₂, C₃ may be scaled to fit the desired low frequency return loss specification. The capacitance values of the capacitors C₁, C₂, C₃ may also be selected depending on the application and the area available. In an example implementation, suitable capacitance values may be C₁=100 pF and C₂=C₃=1 pF, and a variation of up to five times these capacitance values may be acceptable.

The example circuit 200 may occupy a relatively compact space when implemented on an integrated circuit, because there are relatively few components in the first and second stages 202, 206.

FIG. 3 is a schematic diagram of a transmitter and receiver system 200 including the example AC coupled termination circuit 200 of FIG. 2. The example system 300 includes a TX driver 302 coupled to the termination circuit 200 of a RX via a transmission channel 304. Output from the TX driver 302 may travel through a third resistor R₃, which may be a TX termination resistor, for example having a resistance of 40-60Ω or about 50Ω.

The transfer function for this example system 300 may be given by:

$\frac{V_{\mathrm{RX}}}{V_{\mathrm{TX}}}=\left(1+{\mathrm{sR}}_1C_1\right)\left(1+\frac{{\mathrm{sR}}_2C_2}{\left(1+{\mathrm{sR}}_2C_2\right)\left(2+{\mathrm{sR}}_2C_2\right)}\right)$

As in the example circuit 200, the following conditions have been found to enable the system 300 to maintain a flat response:

C₂=C₃; and

2R₁C₁=R₂C₂

To assist in understanding the present disclosure, simulation results are now discussed. It should be understood that these simulation results are for the purpose of illustration only, and are not intended to be limiting or promissory.

A simulation was performed for the example system 300, using the parameters: R₃=50Ω, R₁=50Ω, C₁=100 pF, C₃=C₂=1 pF, and R₂=10 kΩ. These parameter values may represent reasonable and practical resistance and capacitance values for implementation. Variations of these parameters may be suitable in practice (e.g., depending on application requirements), for example resistance values may vary by +/−20% and capacitance values may vary by up to 200%. FIG. 4 presents results of this simulation as a Bode diagram, with reference to voltages V_RX, V_MID and V_TX as indicated in FIG. 3. As may be observed in FIG. 4, the response of the first stage 202 (and including the transmission channel 304), given by V_MID/V_TX, demonstrates a low-pass response. The response of the second stage 206, given by V_RX/V_MID, demonstrates a high-pass response that cancels out the first stage 202. The overall transfer function of the system 300, given by V_RX/V_TX, thus provides a flat response at −6 dB.

Examples disclosed herein provide AC coupled RX termination for singled-ended signals. The disclosed examples may address disadvantages of prior art approaches, such as increased power consumption and/or DC wander for single-ended mode signals, particularly for input data with long CIDs. The example two-stage AC coupled termination described herein may address such disadvantages, over a range of data rates (e.g., 1 Gbps to 30 Gbps, or more), without requiring significantly higher power consumption or added complexity. Further, the size of the termination circuit may be scaled down, as desired, for example to meet the requirements of USR devices or other low-power receivers or transceivers.

The embodiments described herein may be applicable to a wide range of network systems, storage system, computing systems, and/or mobile systems. These techniques may also apply to any applications that may require high-speed and/or power-efficient interconnects.

The present disclosure may be embodied in other specific forms without departing from the subject matter of the claims. The described example embodiments are to be considered in all respects as being only illustrative and not restrictive. Selected features from one or more of the above-described embodiments may be combined to create alternative embodiments not explicitly described, features suitable for such combinations being understood within the scope of this disclosure.

All values and sub-ranges within disclosed ranges are also disclosed. Also, although the systems, devices and processes disclosed and shown herein may comprise a specific number of elements/components, the systems, devices and assemblies could be modified to include additional or fewer of such elements/components. For example, although any of the elements/components disclosed may be referenced as being singular, the embodiments disclosed herein could be modified to include a plurality of such elements/components. The subject matter described herein intends to cover and embrace all suitable changes in technology.

Claims

1. A termination circuit for a receiver receiving a single-ended signal, the termination circuit comprising:

a first stage for receiving input from an input port of the receiver, the first stage having a low-pass transfer function having a first pole/zero pair; and

a second stage for outputting to one or more further stages of the receiver, the second stage being coupled to the first stage, the second stage having a high-pass transfer function, the high-pass transfer function having a second pole/zero pair that cancels out the first pole/zero pair;

wherein the termination circuit provides AC-coupled termination for the single-ended signal.

2. The termination circuit according to claim 1, wherein the first stage comprises a first resistor in series with a first capacitor, the first resistor and the first capacitor being coupled at one end directly to the input port and at another end directly to ground.

3. The termination circuit according to claim 2, wherein the first resistor has a resistance of approximately 50Ω+/−20%.

4. The termination circuit according to claim 3, wherein the first capacitor has a capacitance in the range of approximately 50 pF to approximately 500 pF.

5. The termination circuit according to claim 4, wherein the capacitance of the first capacitor is approximately 100 pF.

6. The termination circuit according to claim 2, wherein the second stage comprises a second capacitor with one end directly coupled to the input port and another end directly coupled to an output of the termination circuit, and a second resistor in series with a third capacitor, the second resistor and the third capacitor being coupled at one end directly to the output of the termination circuit and at another end directly to ground.

7. The termination circuit according to claim 6, wherein the second capacitor and the third capacitor have approximately equal capacitance.

8. The termination circuit according to claim 7, wherein the first resistance, second resistance, first capacitance, and second capacitance are selected to satisfy the condition 2R1C1=R2C2, where R1 is resistance of the first resistor, C1 is capacitance of the first capacitor, R2 is resistance of the second resistor, C2 is capacitance of the second capacitor, and the third capacitor has capacitance approximately equal to capacitance of the second capacitor.

9. The termination circuit according to claim 8, wherein R1=50Ω, C1=100 pF, C2=1 pF, and R2=10 kΩ.

10. The termination circuit according to claim 1, wherein the termination circuit consumes power less than approximately 2 pJ/bit.

11. A receiver for receiving a single-ended signal, the receiver comprising:

an input port for receiving the single-ended signal;

a termination circuit comprising: a first stage coupled to the input port of the receiver, the first stage having a low-pass transfer function having a first pole/zero pair; and a second stage coupled to the first stage, the second stage having a high-pass transfer function, the high-pass transfer function having a second pole/zero pair that cancels out the first pole/zero pair;

wherein the termination circuit provides AC-coupled termination for the single-ended signal; and

one or more further stages coupled to output of the termination circuit, for processing the single-ended signal.

12. The receiver according to claim 11, wherein the first stage of the termination circuit comprises a first resistor in series with a first capacitor, the first resistor and the first capacitor being coupled at one end directly to the input port and at another end directly to ground.

13. The receiver according to claim 12, wherein the second stage of the termination circuit comprises a second capacitor coupled between the input port and one of the one or more further stages, and a second resistor in series with a third capacitor, the second resistor and the third capacitor being coupled at one end directly to the one of the one or more further stages and at another end directly to ground.

14. The receiver according to claim 13, wherein the first resistance, second resistance, first capacitance, and second capacitance are selected to satisfy the condition 2R1C1=R2C2, where R1 is resistance of the first resistor, C1 is capacitance of the first capacitor, R2 is resistance of the second resistor, C2 is capacitance of the second capacitor, and the third capacitor has capacitance approximately equal to capacitance of the second capacitor.

15. The receiver according to claim 11, wherein the termination circuit consumes power less than approximately 2 pJ/bit.

16. A low-power communication device comprising a receiver, wherein the receiver comprises:

an input port of the receiver for receiving a single-ended signal;

a termination circuit comprising: a first stage coupled to the input port of the receiver, the first stage having a low-pass transfer function having a first pole/zero pair; and a second stage coupled to the first stage, the second stage having a high-pass transfer function, the high-pass transfer function having a second pole/zero pair that cancels out the first pole/zero pair; wherein the termination circuit provides AC-coupled termination for the single-ended signal; and

one or more further stages of the receiver coupled to output of the termination circuit, for processing the single-ended signal.

17. The device according to claim 16, wherein the first stage of the termination circuit comprises a first resistor in series with a first capacitor, the first resistor and the first capacitor being coupled at one end directly to the input port and at another end directly to ground.

18. The device according to claim 17, wherein the second stage of the termination circuit comprises a second capacitor coupled between the input port and one of the one or more further stages, and a second resistor in series with a third capacitor, the second resistor and the third capacitor being coupled at one end directly to the one of the one or more further stages and at another end directly to ground.

19. The device according to claim 18, wherein the first resistance, second resistance, first capacitance, and second capacitance are selected to satisfy the condition 2R1C1=R2C2, where R1 is resistance of the first resistor, C1 is capacitance of the first capacitor, R2 is resistance of the second resistor, C2 is capacitance of the second capacitor, and the third capacitor has capacitance approximately equal to capacitance of the second capacitor.

20. The device according to claim 16, wherein the termination circuit consumes power less than approximately 2 pJ/bit.