TECHNOLOGIES FOR PROVIDING EFFICIENT MEMORY ACCESS ON AN ACCELERATOR SLED
Technologies for providing efficient access to the memory of an accelerator device include an accelerator sled. The accelerator sled includes an accelerator device including a memory. The accelerator sled also includes a network interface controller that includes a memory access logic unit. The memory access logic unit is to determine a memory address region usable by a remote compute device to access the memory of the accelerator device, receive, from the remote compute device, a memory access request to remotely access the memory of the accelerator device associated with the memory address region, and perform, in response to the memory access request, a direct memory access operation on the memory. Other embodiments are also described and claimed.
The present application claims the benefit of Indian Provisional Patent Application No. 201741030632, filed Aug. 30, 2017 and U.S. Provisional Patent Application No. 62/584,401, filed Nov. 10, 2017.
BACKGROUNDIn some data centers, a compute device may by physically separated from (e.g., connected through a network to) an accelerator device which may be physically located on a board with one or more other accelerator devices. In such systems, a general purpose processor is coupled between a network interface controller that provides connectivity to the network and the set of accelerator devices. The compute device may issue requests for operations to be performed by one of the accelerator devices, such as to read or write from a memory of the accelerator device (e.g., to provide a data set on which to perform a function or to read output data resulting from the execution of the function) to increase the speed of execution of a workload (e.g., an application). In such operations, the request and any accompanying data, is received by the network interface controller, passed to the general purpose processor, which acts as an intermediary, and then is passed to the corresponding accelerator device. This series of transactions that occur to access the memory of the accelerator device can incur latency that may diminish the speed improvement provided by offloading the function from the compute device to the accelerator device.
The concepts described herein are illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. Where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.
While the concepts of the present disclosure are susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will be described herein in detail. It should be understood, however, that there is no intent to limit the concepts of the present disclosure to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives consistent with the present disclosure and the appended claims.
References in the specification to “one embodiment,” “an embodiment,” “an illustrative embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may or may not necessarily include that particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. Additionally, it should be appreciated that items included in a list in the form of “at least one A, B, and C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C). Similarly, items listed in the form of “at least one of A, B, or C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C).
The disclosed embodiments may be implemented, in some cases, in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried by or stored on a transitory or non-transitory machine-readable (e.g., computer-readable) storage medium, which may be read and executed by one or more processors. A machine-readable storage medium may be embodied as any storage device, mechanism, or other physical structure for storing or transmitting information in a form readable by a machine (e.g., a volatile or non-volatile memory, a media disc, or other media device).
In the drawings, some structural or method features may be shown in specific arrangements and/or orderings. However, it should be appreciated that such specific arrangements and/or orderings may not be required. Rather, in some embodiments, such features may be arranged in a different manner and/or order than shown in the illustrative figures. Additionally, the inclusion of a structural or method feature in a particular figure is not meant to imply that such feature is required in all embodiments and, in some embodiments, may not be included or may be combined with other features.
Referring now to
Referring now to
It should be appreciated that each of the other pods 120, 130, 140 (as well as any additional pods of the data center 100) may be similarly structured as, and have components similar to, the pod 110 shown in and described in regard to
Referring now to
In the illustrative embodiments, each sled of the data center 100 is embodied as a chassis-less sled. That is, each sled has a chassis-less circuit board substrate on which physical resources (e.g., processors, memory, accelerators, storage, etc.) are mounted as discussed in more detail below. As such, the rack 240 is configured to receive the chassis-less sleds. For example, each pair 310 of elongated support arms 312 defines a sled slot 320 of the rack 240, which is configured to receive a corresponding chassis-less sled. To do so, each illustrative elongated support arm 312 includes a circuit board guide 330 configured to receive the chassis-less circuit board substrate of the sled. Each circuit board guide 330 is secured to, or otherwise mounted to, a top side 332 of the corresponding elongated support arm 312. For example, in the illustrative embodiment, each circuit board guide 330 is mounted at a distal end of the corresponding elongated support arm 312 relative to the corresponding elongated support post 302, 304. For clarity of the Figures, not every circuit board guide 330 may be referenced in each Figure.
Each circuit board guide 330 includes an inner wall that defines a circuit board slot 380 configured to receive the chassis-less circuit board substrate of a sled 400 when the sled 400 is received in the corresponding sled slot 320 of the rack 240. To do so, as shown in
It should be appreciated that each circuit board guide 330 is dual sided. That is, each circuit board guide 330 includes an inner wall that defines a circuit board slot 380 on each side of the circuit board guide 330. In this way, each circuit board guide 330 can support a chassis-less circuit board substrate on either side. As such, a single additional elongated support post may be added to the rack 240 to turn the rack 240 into a two-rack solution that can hold twice as many sled slots 320 as shown in
In some embodiments, various interconnects may be routed upwardly or downwardly through the elongated support posts 302, 304. To facilitate such routing, each elongated support post 302, 304 includes an inner wall that defines an inner chamber in which the interconnect may be located. The interconnects routed through the elongated support posts 302, 304 may be embodied as any type of interconnects including, but not limited to, data or communication interconnects to provide communication connections to each sled slot 320, power interconnects to provide power to each sled slot 320, and/or other types of interconnects.
The rack 240, in the illustrative embodiment, includes a support platform on which a corresponding optical data connector (not shown) is mounted. Each optical data connector is associated with a corresponding sled slot 320 and is configured to mate with an optical data connector of a corresponding sled 400 when the sled 400 is received in the corresponding sled slot 320. In some embodiments, optical connections between components (e.g., sleds, racks, and switches) in the data center 100 are made with a blind mate optical connection. For example, a door on each cable may prevent dust from contaminating the fiber inside the cable. In the process of connecting to a blind mate optical connector mechanism, the door is pushed open when the end of the cable enters the connector mechanism. Subsequently, the optical fiber inside the cable enters a gel within the connector mechanism and the optical fiber of one cable comes into contact with the optical fiber of another cable within the gel inside the connector mechanism.
The illustrative rack 240 also includes a fan array 370 coupled to the cross-support arms of the rack 240. The fan array 370 includes one or more rows of cooling fans 372, which are aligned in a horizontal line between the elongated support posts 302, 304. In the illustrative embodiment, the fan array 370 includes a row of cooling fans 372 for each sled slot 320 of the rack 240. As discussed above, each sled 400 does not include any on-board cooling system in the illustrative embodiment and, as such, the fan array 370 provides cooling for each sled 400 received in the rack 240. Each rack 240, in the illustrative embodiment, also includes a power supply associated with each sled slot 320. Each power supply is secured to one of the elongated support arms 312 of the pair 310 of elongated support arms 312 that define the corresponding sled slot 320. For example, the rack 240 may include a power supply coupled or secured to each elongated support arm 312 extending from the elongated support post 302. Each power supply includes a power connector configured to mate with a power connector of the sled 400 when the sled 400 is received in the corresponding sled slot 320. In the illustrative embodiment, the sled 400 does not include any on-board power supply and, as such, the power supplies provided in the rack 240 supply power to corresponding sleds 400 when mounted to the rack 240.
Referring now to
As discussed above, the illustrative sled 400 includes a chassis-less circuit board substrate 602, which supports various physical resources (e.g., electrical components) mounted thereon. It should be appreciated that the circuit board substrate 602 is “chassis-less” in that the sled 400 does not include a housing or enclosure. Rather, the chassis-less circuit board substrate 602 is open to the local environment. The chassis-less circuit board substrate 602 may be formed from any material capable of supporting the various electrical components mounted thereon. For example, in an illustrative embodiment, the chassis-less circuit board substrate 602 is formed from an FR-4 glass-reinforced epoxy laminate material. Of course, other materials may be used to form the chassis-less circuit board substrate 602 in other embodiments.
As discussed in more detail below, the chassis-less circuit board substrate 602 includes multiple features that improve the thermal cooling characteristics of the various electrical components mounted on the chassis-less circuit board substrate 602. As discussed, the chassis-less circuit board substrate 602 does not include a housing or enclosure, which may improve the airflow over the electrical components of the sled 400 by reducing those structures that may inhibit air flow. For example, because the chassis-less circuit board substrate 602 is not positioned in an individual housing or enclosure, there is no backplane (e.g., a backplate of the chassis) to the chassis-less circuit board substrate 602, which could inhibit air flow across the electrical components. Additionally, the chassis-less circuit board substrate 602 has a geometric shape configured to reduce the length of the airflow path across the electrical components mounted to the chassis-less circuit board substrate 602. For example, the illustrative chassis-less circuit board substrate 602 has a width 604 that is greater than a depth 606 of the chassis-less circuit board substrate 602. In one particular embodiment, for example, the chassis-less circuit board substrate 602 has a width of about 21 inches and a depth of about 9 inches, compared to a typical server that has a width of about 17 inches and a depth of about 39 inches. As such, an airflow path 608 that extends from a front edge 610 of the chassis-less circuit board substrate 602 toward a rear edge 612 has a shorter distance relative to typical servers, which may improve the thermal cooling characteristics of the sled 400. Furthermore, although not illustrated in
As discussed above, the illustrative sled 400 includes one or more physical resources 620 mounted to a top side 650 of the chassis-less circuit board substrate 602. Although two physical resources 620 are shown in
The sled 400 also includes one or more additional physical resources 630 mounted to the top side 650 of the chassis-less circuit board substrate 602. In the illustrative embodiment, the additional physical resources include a network interface controller (NIC) as discussed in more detail below. Of course, depending on the type and functionality of the sled 400, the physical resources 630 may include additional or other electrical components, circuits, and/or devices in other embodiments.
The physical resources 620 are communicatively coupled to the physical resources 630 via an input/output (I/O) subsystem 622. The I/O subsystem 622 may be embodied as circuitry and/or components to facilitate input/output operations with the physical resources 620, the physical resources 630, and/or other components of the sled 400. For example, the I/O subsystem 622 may be embodied as, or otherwise include, memory controller hubs, input/output control hubs, integrated sensor hubs, firmware devices, communication links (e.g., point-to-point links, bus links, wires, cables, light guides, printed circuit board traces, etc.), and/or other components and subsystems to facilitate the input/output operations. In the illustrative embodiment, the I/O subsystem 622 is embodied as, or otherwise includes, a double data rate 4 (DDR4) data bus or a DDR5 data bus.
In some embodiments, the sled 400 may also include a resource-to-resource interconnect 624. The resource-to-resource interconnect 624 may be embodied as any type of communication interconnect capable of facilitating resource-to-resource communications. In the illustrative embodiment, the resource-to-resource interconnect 624 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the resource-to-resource interconnect 624 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to resource-to-resource communications.
The sled 400 also includes a power connector 640 configured to mate with a corresponding power connector of the rack 240 when the sled 400 is mounted in the corresponding rack 240. The sled 400 receives power from a power supply of the rack 240 via the power connector 640 to supply power to the various electrical components of the sled 400. That is, the sled 400 does not include any local power supply (i.e., an on-board power supply) to provide power to the electrical components of the sled 400. The exclusion of a local or on-board power supply facilitates the reduction in the overall footprint of the chassis-less circuit board substrate 602, which may increase the thermal cooling characteristics of the various electrical components mounted on the chassis-less circuit board substrate 602 as discussed above. In some embodiments, power is provided to the processors 820 through vias directly under the processors 820 (e.g., through the bottom side 750 of the chassis-less circuit board substrate 602), providing an increased thermal budget, additional current and/or voltage, and better voltage control over typical boards.
In some embodiments, the sled 400 may also include mounting features 642 configured to mate with a mounting arm, or other structure, of a robot to facilitate the placement of the sled 600 in a rack 240 by the robot. The mounting features 642 may be embodied as any type of physical structures that allow the robot to grasp the sled 400 without damaging the chassis-less circuit board substrate 602 or the electrical components mounted thereto. For example, in some embodiments, the mounting features 642 may be embodied as non-conductive pads attached to the chassis-less circuit board substrate 602. In other embodiments, the mounting features may be embodied as brackets, braces, or other similar structures attached to the chassis-less circuit board substrate 602. The particular number, shape, size, and/or make-up of the mounting feature 642 may depend on the design of the robot configured to manage the sled 400.
Referring now to
The memory devices 720 may be embodied as any type of memory device capable of storing data for the physical resources 620 during operation of the sled 400, such as any type of volatile (e.g., dynamic random access memory (DRAM), etc.) or non-volatile memory. Volatile memory may be a storage medium that requires power to maintain the state of data stored by the medium. Non-limiting examples of volatile memory may include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM). One particular type of DRAM that may be used in a memory module is synchronous dynamic random access memory (SDRAM). In particular embodiments, DRAM of a memory component may comply with a standard promulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for Low Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4 (these standards are available at www.jedec.org). Such standards (and similar standards) may be referred to as DDR-based standards and communication interfaces of the storage devices that implement such standards may be referred to as DDR-based interfaces.
In one embodiment, the memory device is a block addressable memory device, such as those based on NAND or NOR technologies. A memory device may also include next-generation nonvolatile devices, such as Intel 3D XPoint™ memory or other byte addressable write-in-place nonvolatile memory devices. In one embodiment, the memory device may be or may include memory devices that use chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thyristor based memory device, or a combination of any of the above, or other memory. The memory device may refer to the die itself and/or to a packaged memory product. In some embodiments, the memory device may comprise a transistor-less stackable cross point architecture in which memory cells sit at the intersection of word lines and bit lines and are individually addressable and in which bit storage is based on a change in bulk resistance.
Referring now to
In the illustrative compute sled 800, the physical resources 620 are embodied as processors 820. Although only two processors 820 are shown in
In some embodiments, the compute sled 800 may also include a processor-to-processor interconnect 842. Similar to the resource-to-resource interconnect 624 of the sled 400 discussed above, the processor-to-processor interconnect 842 may be embodied as any type of communication interconnect capable of facilitating processor-to-processor interconnect 842 communications. In the illustrative embodiment, the processor-to-processor interconnect 842 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the processor-to-processor interconnect 842 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications.
The compute sled 800 also includes a communication circuit 830. The illustrative communication circuit 830 includes a network interface controller (NIC) 832, which may also be referred to as a host fabric interface (HFI). The NIC 832 may be embodied as, or otherwise include, any type of integrated circuit, discrete circuits, controller chips, chipsets, add-in-boards, daughtercards, network interface cards, other devices that may be used by the compute sled 800 to connect with another compute device (e.g., with other sleds 400). In some embodiments, the NIC 832 may be embodied as part of a system-on-a-chip (SoC) that includes one or more processors, or included on a multichip package that also contains one or more processors. In some embodiments, the NIC 832 may include a local processor (not shown) and/or a local memory (not shown) that are both local to the NIC 832. In such embodiments, the local processor of the NIC 832 may be capable of performing one or more of the functions of the processors 820. Additionally or alternatively, in such embodiments, the local memory of the NIC 832 may be integrated into one or more components of the compute sled at the board level, socket level, chip level, and/or other levels.
The communication circuit 830 is communicatively coupled to an optical data connector 834. The optical data connector 834 is configured to mate with a corresponding optical data connector of the rack 240 when the compute sled 800 is mounted in the rack 240. Illustratively, the optical data connector 834 includes a plurality of optical fibers which lead from a mating surface of the optical data connector 834 to an optical transceiver 836. The optical transceiver 836 is configured to convert incoming optical signals from the rack-side optical data connector to electrical signals and to convert electrical signals to outgoing optical signals to the rack-side optical data connector. Although shown as forming part of the optical data connector 834 in the illustrative embodiment, the optical transceiver 836 may form a portion of the communication circuit 830 in other embodiments.
In some embodiments, the compute sled 800 may also include an expansion connector 840. In such embodiments, the expansion connector 840 is configured to mate with a corresponding connector of an expansion chassis-less circuit board substrate to provide additional physical resources to the compute sled 800. The additional physical resources may be used, for example, by the processors 820 during operation of the compute sled 800. The expansion chassis-less circuit board substrate may be substantially similar to the chassis-less circuit board substrate 602 discussed above and may include various electrical components mounted thereto. The particular electrical components mounted to the expansion chassis-less circuit board substrate may depend on the intended functionality of the expansion chassis-less circuit board substrate. For example, the expansion chassis-less circuit board substrate may provide additional compute resources, memory resources, and/or storage resources. As such, the additional physical resources of the expansion chassis-less circuit board substrate may include, but is not limited to, processors, memory devices, storage devices, and/or accelerator circuits including, for example, field programmable gate arrays (FPGA), application-specific integrated circuits (ASICs), security co-processors, graphics processing units (GPUs), machine learning circuits, or other specialized processors, controllers, devices, and/or circuits.
Referring now to
As discussed above, the individual processors 820 and communication circuit 830 are mounted to the top side 650 of the chassis-less circuit board substrate 602 such that no two heat-producing, electrical components shadow each other. In the illustrative embodiment, the processors 820 and communication circuit 830 are mounted in corresponding locations on the top side 650 of the chassis-less circuit board substrate 602 such that no two of those physical resources are linearly in-line with others along the direction of the airflow path 608. It should be appreciated that, although the optical data connector 834 is in-line with the communication circuit 830, the optical data connector 834 produces no or nominal heat during operation.
The memory devices 720 of the compute sled 800 are mounted to the bottom side 750 of the of the chassis-less circuit board substrate 602 as discussed above in regard to the sled 400. Although mounted to the bottom side 750, the memory devices 720 are communicatively coupled to the processors 820 located on the top side 650 via the I/O subsystem 622. Because the chassis-less circuit board substrate 602 is embodied as a double-sided circuit board, the memory devices 720 and the processors 820 may be communicatively coupled by one or more vias, connectors, or other mechanisms extending through the chassis-less circuit board substrate 602. Of course, each processor 820 may be communicatively coupled to a different set of one or more memory devices 720 in some embodiments. Alternatively, in other embodiments, each processor 820 may be communicatively coupled to each memory device 720. In some embodiments, the memory devices 720 may be mounted to one or more memory mezzanines on the bottom side of the chassis-less circuit board substrate 602 and may interconnect with a corresponding processor 820 through a ball-grid array.
Each of the processors 820 includes a heatsink 850 secured thereto. Due to the mounting of the memory devices 720 to the bottom side 750 of the chassis-less circuit board substrate 602 (as well as the vertical spacing of the sleds 400 in the corresponding rack 240), the top side 650 of the chassis-less circuit board substrate 602 includes additional “free” area or space that facilitates the use of heatsinks 850 having a larger size relative to traditional heatsinks used in typical servers. Additionally, due to the improved thermal cooling characteristics of the chassis-less circuit board substrate 602, none of the processor heatsinks 850 include cooling fans attached thereto. That is, each of the heatsinks 850 is embodied as a fan-less heatsinks.
Referring now to
In the illustrative accelerator sled 1000, the physical resources 620 are embodied as accelerator circuits 1020. Although only two accelerator circuits 1020 are shown in
In some embodiments, the accelerator sled 1000 may also include an accelerator-to-accelerator interconnect 1042. Similar to the resource-to-resource interconnect 624 of the sled 600 discussed above, the accelerator-to-accelerator interconnect 1042 may be embodied as any type of communication interconnect capable of facilitating accelerator-to-accelerator communications. In the illustrative embodiment, the accelerator-to-accelerator interconnect 1042 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the accelerator-to-accelerator interconnect 1042 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications. In some embodiments, the accelerator circuits 1020 may be daisy-chained with a primary accelerator circuit 1020 connected to the NIC 832 and memory 720 through the I/O subsystem 622 and a secondary accelerator circuit 1020 connected to the NIC 832 and memory 720 through a primary accelerator circuit 1020.
Referring now to
Referring now to
In the illustrative storage sled 1200, the physical resources 620 are embodied as storage controllers 1220. Although only two storage controllers 1220 are shown in
In some embodiments, the storage sled 1200 may also include a controller-to-controller interconnect 1242. Similar to the resource-to-resource interconnect 624 of the sled 400 discussed above, the controller-to-controller interconnect 1242 may be embodied as any type of communication interconnect capable of facilitating controller-to-controller communications. In the illustrative embodiment, the controller-to-controller interconnect 1242 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the controller-to-controller interconnect 1242 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications.
Referring now to
The storage cage 1252 illustratively includes sixteen mounting slots 1256 and is capable of mounting and storing sixteen solid state drives 1254. Of course, the storage cage 1252 may be configured to store additional or fewer solid state drives 1254 in other embodiments. Additionally, in the illustrative embodiment, the solid state drivers are mounted vertically in the storage cage 1252, but may be mounted in the storage cage 1252 in a different orientation in other embodiments. Each solid state drive 1254 may be embodied as any type of data storage device capable of storing long term data. To do so, the solid state drives 1254 may include volatile and non-volatile memory devices discussed above.
As shown in
As discussed above, the individual storage controllers 1220 and the communication circuit 830 are mounted to the top side 650 of the chassis-less circuit board substrate 602 such that no two heat-producing, electrical components shadow each other. For example, the storage controllers 1220 and the communication circuit 830 are mounted in corresponding locations on the top side 650 of the chassis-less circuit board substrate 602 such that no two of those electrical components are linearly in-line with other along the direction of the airflow path 608.
The memory devices 720 of the storage sled 1200 are mounted to the bottom side 750 of the of the chassis-less circuit board substrate 602 as discussed above in regard to the sled 400. Although mounted to the bottom side 750, the memory devices 720 are communicatively coupled to the storage controllers 1220 located on the top side 650 via the I/O subsystem 622. Again, because the chassis-less circuit board substrate 602 is embodied as a double-sided circuit board, the memory devices 720 and the storage controllers 1220 may be communicatively coupled by one or more vias, connectors, or other mechanisms extending through the chassis-less circuit board substrate 602. Each of the storage controllers 1220 includes a heatsink 1270 secured thereto. As discussed above, due to the improved thermal cooling characteristics of the chassis-less circuit board substrate 602 of the storage sled 1200, none of the heatsinks 1270 include cooling fans attached thereto. That is, each of the heatsinks 1270 is embodied as a fan-less heatsink.
Referring now to
In the illustrative memory sled 1400, the physical resources 620 are embodied as memory controllers 1420. Although only two memory controllers 1420 are shown in
In some embodiments, the memory sled 1400 may also include a controller-to-controller interconnect 1442. Similar to the resource-to-resource interconnect 624 of the sled 400 discussed above, the controller-to-controller interconnect 1442 may be embodied as any type of communication interconnect capable of facilitating controller-to-controller communications. In the illustrative embodiment, the controller-to-controller interconnect 1442 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the controller-to-controller interconnect 1442 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications. As such, in some embodiments, a memory controller 1420 may access, through the controller-to-controller interconnect 1442, memory that is within the memory set 1432 associated with another memory controller 1420. In some embodiments, a scalable memory controller is made of multiple smaller memory controllers, referred to herein as “chiplets”, on a memory sled (e.g., the memory sled 1400). The chiplets may be interconnected (e.g., using EMIB (Embedded Multi-Die Interconnect Bridge)). The combined chiplet memory controller may scale up to a relatively large number of memory controllers and I/O ports, (e.g., up to 16 memory channels). In some embodiments, the memory controllers 1420 may implement a memory interleave (e.g., one memory address is mapped to the memory set 1430, the next memory address is mapped to the memory set 1432, and the third address is mapped to the memory set 1430, etc.). The interleaving may be managed within the memory controllers 1420, or from CPU sockets (e.g., of the compute sled 800) across network links to the memory sets 1430, 1432, and may improve the latency associated with performing memory access operations as compared to accessing contiguous memory addresses from the same memory device.
Further, in some embodiments, the memory sled 1400 may be connected to one or more other sleds 400 (e.g., in the same rack 240 or an adjacent rack 240) through a waveguide, using the waveguide connector 1480. In the illustrative embodiment, the waveguides are 64 millimeter waveguides that provide 16 Rx (i.e., receive) lanes and 16 Rt (i.e., transmit) lanes. Each lane, in the illustrative embodiment, is either 16 Ghz or 32 Ghz. In other embodiments, the frequencies may be different. Using a waveguide may provide high throughput access to the memory pool (e.g., the memory sets 1430, 1432) to another sled (e.g., a sled 400 in the same rack 240 or an adjacent rack 240 as the memory sled 1400) without adding to the load on the optical data connector 834.
Referring now to
Additionally, in some embodiments, the orchestrator server 1520 may identify trends in the resource utilization of the workload (e.g., the application 1532), such as by identifying phases of execution (e.g., time periods in which different operations, each having different resource utilizations characteristics, are performed) of the workload (e.g., the application 1532) and pre-emptively identifying available resources in the data center 100 and allocating them to the managed node 1570 (e.g., within a predefined time period of the associated phase beginning). In some embodiments, the orchestrator server 1520 may model performance based on various latencies and a distribution scheme to place workloads among compute sleds and other resources (e.g., accelerator sleds, memory sleds, storage sleds) in the data center 100. For example, the orchestrator server 1520 may utilize a model that accounts for the performance of resources on the sleds 400 (e.g., FPGA performance, memory access latency, etc.) and the performance (e.g., congestion, latency, bandwidth) of the path through the network to the resource (e.g., FPGA). As such, the orchestrator server 1520 may determine which resource(s) should be used with which workloads based on the total latency associated with each potential resource available in the data center 100 (e.g., the latency associated with the performance of the resource itself in addition to the latency associated with the path through the network between the compute sled executing the workload and the sled 400 on which the resource is located).
In some embodiments, the orchestrator server 1520 may generate a map of heat generation in the data center 100 using telemetry data (e.g., temperatures, fan speeds, etc.) reported from the sleds 400 and allocate resources to managed nodes as a function of the map of heat generation and predicted heat generation associated with different workloads, to maintain a target temperature and heat distribution in the data center 100. Additionally or alternatively, in some embodiments, the orchestrator server 1520 may organize received telemetry data into a hierarchical model that is indicative of a relationship between the managed nodes (e.g., a spatial relationship such as the physical locations of the resources of the managed nodes within the data center 100 and/or a functional relationship, such as groupings of the managed nodes by the customers the managed nodes provide services for, the types of functions typically performed by the managed nodes, managed nodes that typically share or exchange workloads among each other, etc.). Based on differences in the physical locations and resources in the managed nodes, a given workload may exhibit different resource utilizations (e.g., cause a different internal temperature, use a different percentage of processor or memory capacity) across the resources of different managed nodes. The orchestrator server 1520 may determine the differences based on the telemetry data stored in the hierarchical model and factor the differences into a prediction of future resource utilization of a workload if the workload is reassigned from one managed node to another managed node, to accurately balance resource utilization in the data center 100.
To reduce the computational load on the orchestrator server 1520 and the data transfer load on the network, in some embodiments, the orchestrator server 1520 may send self-test information to the sleds 400 to enable each sled 400 to locally (e.g., on the sled 400) determine whether telemetry data generated by the sled 400 satisfies one or more conditions (e.g., an available capacity that satisfies a predefined threshold, a temperature that satisfies a predefined threshold, etc.). Each sled 400 may then report back a simplified result (e.g., yes or no) to the orchestrator server 1520, which the orchestrator server 1520 may utilize in determining the allocation of resources to managed nodes.
Referring now to
In the illustrative embodiment, the compute sled 1630 is similar to the sled 800 of
Referring now to
The compute engine 1706, if included in the accelerator sled 1640, may be embodied as any type of device or collection of devices capable of performing various compute functions described below. In some embodiments, the compute engine 1706 may be embodied as a single device such as an integrated circuit, an embedded system, a field-programmable gate array (FPGA), a system-on-a-chip (SOC), or other integrated system or device. In the illustrative embodiment, the compute engine 1706 includes or is embodied as a processor 1708 and a memory 1710. The processor 1708 may be embodied as any type of device or circuitry capable of performing general computations and management of other components of the accelerator sled 1640. For example, the processor 1708 may be embodied as a microcontroller, a single or multi-core processor(s), or other processor or processing/controlling circuit. In some embodiments, the processor 1708 may be embodied as, include, or be coupled to an FPGA, an application specific integrated circuit (ASIC), reconfigurable hardware or hardware circuitry, or other specialized hardware to facilitate performance of the functions described herein.
The memory 1710 may be embodied as any type of volatile (e.g., dynamic random access memory (DRAM), etc.) or non-volatile memory or data storage capable of performing the functions described herein. Volatile memory may be a storage medium that requires power to maintain the state of data stored by the medium. Non-limiting examples of volatile memory may include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM). One particular type of DRAM that may be used in a memory module is synchronous dynamic random access memory (SDRAM). In particular embodiments, DRAM of a memory component may comply with a standard promulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for Low Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4 (these standards are available at www.jedec.org). Such standards (and similar standards) may be referred to as DDR-based standards and communication interfaces of the storage devices that implement such standards may be referred to as DDR-based interfaces.
In one embodiment, the memory device is a block addressable memory device, such as those based on NAND or NOR technologies. A memory device may also include future generation nonvolatile devices, such as a three dimensional crosspoint memory device (e.g., Intel 3D XPoint™ memory), or other byte addressable write-in-place nonvolatile memory devices. In one embodiment, the memory device may be or may include memory devices that use chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thyristor based memory device, or a combination of any of the above, or other memory. The memory device may refer to the die itself and/or to a packaged memory product.
In some embodiments, 3D crosspoint memory (e.g., Intel 3D XPoint™ memory) may comprise a transistor-less stackable cross point architecture in which memory cells sit at the intersection of word lines and bit lines and are individually addressable and in which bit storage is based on a change in bulk resistance. In some embodiments, all or a portion of the memory 1710 may be integrated into the processor 1708. In operation, the memory 1710 may store various software and data used during operation such as applications, programs, and libraries.
The components of the accelerator sled 1640 are connected together via the I/O subsystem 1704, which may be embodied as circuitry and/or devices to facilitate input/output operations with the communication circuitry 1702, the accelerator device(s) 1660, the compute engine 1706, and other components of the accelerator sled 1640. For example, the I/O subsystem 1704 may be embodied as, or otherwise include, memory controller hubs, input/output control hubs, integrated sensor hubs, firmware devices, communication links (e.g., point-to-point links, bus links, wires, cables, light guides, printed circuit board traces, etc.), and/or other components and subsystems to facilitate the input/output operations. In some embodiments, the I/O subsystem 1704 may form a portion of a system-on-a-chip (SoC) and be incorporated into one or more other components of the accelerator sled 1640.
The communication circuitry 1702 may be embodied as any communication circuit, device, or collection thereof, capable of enabling communications over the network 1612 between the accelerator sled 1640 and another compute device (e.g., the compute sled 1630 or the orchestrator server 1620). The communication circuitry 1702 may be configured to use any one or more communication technology (e.g., wired or wireless communications) and associated protocols (e.g., Ethernet, Bluetooth®, Wi-Fi®, WiMAX, etc.) to effect such communication.
The communication circuitry 1702, in the illustrative embodiment, includes a network interface controller (NIC) 1652, which may also be referred to as a host fabric interface (HFI). The NIC 1652 may be embodied as one or more add-in-boards, daughter cards, network interface cards, controller chips, chipsets, or other devices that may be used by the accelerator sled 1640 to connect with another compute device (e.g., the compute sled 1630, the orchestrator server 1620, etc.). In some embodiments, the NIC 1652 may be embodied as part of a system-on-a-chip (SoC) that includes one or more processors, or included on a multichip package that also contains one or more processors. In some embodiments, the NIC 1652 may include a local processor (not shown) and/or a local memory (not shown) that are both local to the NIC 1652. Additionally or alternatively, in such embodiments, the local memory of the NIC 1652 may be integrated into one or more components of the accelerator sled 1640 at the board level, socket level, chip level, and/or other levels. In the illustrative embodiment, the NIC 1652 additionally includes the memory access logic unit 1654, described above with reference to
The accelerator devices 1660, in the illustrative embodiment, include a set of primary FPGAs (e.g., FPGAs that are connected directly to the NIC 1652 through a local bus such as a peripheral component interconnect express (PCIe) bus), in which each primary FPGA 1720 operates as a PCIe root device (e.g., a PCIe root complex) and the NIC 1652 operates as a PCIe endpoint device. Additionally, the accelerator devices 1660 may include one or more secondary FPGAs 1730 that are daisy-chained (e.g., connected to another FPGA, such as a primary FPGA 1720) and, as such, are indirectly connected to the NIC 1652. Each FPGA 1720, 1730 is connected to a corresponding memory 1722, 1732, similar to the memory 1710. Each memory 1722, 1732 may include a register space, similar to the register spaces 1690, 1692, 1694, 1696 described with reference to
The accelerator sled 1640 may also include one or more data storage devices 1740, which may be embodied as any type of devices configured for short-term or long-term storage of data such as, for example, memory devices and circuits, memory cards, hard disk drives, solid-state drives, or other data storage devices. Each data storage device 1740 may include a system partition that stores data and firmware code for the data storage device 1740. Each data storage device 1740 may also include one or more operating system partitions that store data files and executables for operating systems.
The orchestrator server 1620, the compute sled 1630, and the client device 1614 may have components similar to those described in
As described above, the orchestrator server 1620, the sleds 1630, 1640, and the client device 1614 are illustratively in communication via the network 1612, which may be embodied as any type of wired or wireless communication network, including global networks (e.g., the Internet), local area networks (LANs) or wide area networks (WANs), cellular networks (e.g., Global System for Mobile Communications (GSM), 3G, Long Term Evolution (LTE), Worldwide Interoperability for Microwave Access (WiMAX), etc.), digital subscriber line (DSL) networks, cable networks (e.g., coaxial networks, fiber networks, etc.), or any combination thereof.
Referring now to
In the illustrative environment 1800, the network communicator 1820, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof as discussed above, is configured to facilitate inbound and outbound network communications (e.g., network traffic, network packets, network flows, etc.) to and from the accelerator sled 1640, respectively. To do so, the network communicator 1820 is configured to receive and process data packets from one system or computing device (e.g., the compute sled 1630, the orchestrator server 1620, etc.) and to prepare and send data packets to a computing device or system (e.g., the compute sled 1630, the orchestrator server 1620, etc.). Accordingly, in some embodiments, at least a portion of the functionality of the network communicator 1820 may be performed by the communication circuitry 1702, and, in the illustrative embodiment, by the NIC 1652.
The memory access manager 1830, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof, is configured to route memory access requests from a remote compute device (e.g., the compute sled 1630) to the corresponding accelerator devices 1660 as direct memory access operations (e.g., without relying on a general purpose processor as an intermediary) to reduce the latency that may otherwise be incurred in performing write or read operations on the memories of the accelerator devices 1660. To do so, in the illustrative embodiment, the memory access manager 1830 includes an address establisher 1832, a write manager 1834, and a read manager 1836.
The address establisher 1832, in the illustrative embodiment, is configured to establish (e.g., determine) the memory addresses to be mapped to regions of memory (e.g., random access memory (RAM), registers, etc.) that are to be remotely accessible by the compute sled 1630 or another remote compute device. In some embodiments, the address establisher may additionally establish queue pairs (e.g., a read queue and a write queue) for use in tracking the completion of remote direct memory access operations that have been requested (e.g., by the compute sled 1630) on the memory 1722, 1732 of a corresponding accelerator device 1660.
The write manager 1834, in the illustrative embodiment, is configured to manage the execution of write operations that have been requested by the compute sled 1630 or another remote compute device to corresponding memories 1722, 1732 (e.g., based on a memory address included in the request). Additionally, the read manager 1836 is configured to manage the execution of read operations that have been requested by the compute sled 1630 or another remote compute device to the corresponding memories 1722, 1732 (e.g., based on a memory address included in the request). As described above, the write operations and read operations, in the illustrative embodiment, are performed as direct memory access operations (e.g., data is copied from the NIC 1652 directly to a memory (e.g., the memory 1722) of an accelerator device (e.g., the FPGA 1720), without relying on an intermediate stage of copying the data to the memory associated with a general purpose processor (e.g., the memory 1710). It should be appreciated that each of the address establisher 1832, the write manager 1834, and the read manager 1836 may be separately embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof. For example, the address establisher 1832 may be embodied as a hardware component, while the write manger 1834 and the read manager 1836 are embodied as virtualized hardware components or as some other combination of hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof.
Referring now to
Additionally, in the illustrative embodiment, the accelerator sled 1640 assigns addresses for the register region(s), as indicated in block 1918. In doing so, the accelerator sled 1640 may assign an address space for administrative register(s) (e.g., registers usable to request the accelerator device 1660 to reset, power down, etc.), as indicated in block 1920. Further, and as indicated in block 1922, the accelerator sled 1640 assigns the address space to a predefined offset from the base address corresponding to each present accelerator device 1660. The accelerator sled 1640 may prevent the compute sled 1630 from accessing the address space associated with administrative operations (e.g., pursuant to a set of permissions associated with the workload 1632). Additionally, in the illustrative embodiment and as indicated in block 1924, the accelerator sled 1640 assigns an address space for user-level register(s) (e.g., register(s) usable to request the accelerator device 1660 to execute a function that was offloaded from the compute sled 1630, etc.). As indicated in block 1926, the accelerator sled 1640, in the illustrative embodiment, assigns an address space for user bit stream operations (e.g., register(s) usable to request the accelerator device 1660 to configure itself with a bit stream that is present in the RAM). Further, as indicated in block 1928, the accelerator sled 1640, in the illustrative embodiment, provides data indicative of the determined memory address regions to a remote compute device (e.g., the compute sled 1630). Subsequently, the method 1900 advances to block 1930 of
Referring now to
Subsequently, in block 1942, the accelerator sled 1640 may receive a request (e.g., from the compute sled 1630) to remotely access the memory of one of the accelerator devices 1660. The accelerator sled 1640, in the illustrative embodiment, receives the request at the NIC 1652, as indicated in block 1944. Further, as indicated in block 1946, the accelerator sled 1546 may receive a request that identifies a memory address to access. As indicated in block 1948, the accelerator sled 1640 may receive a request that includes the unique identifier associated with one of the queues (e.g., a read queue or a write queue) established in block 1930. As indicated in block 1950, the accelerator sled 1640 may receive a request to write data, or as indicated in block 1952, may receive a request to read data. Subsequently, the method 1900 advances to block 1954 of
Referring now to
Subsequently, in block 1966, the accelerator sled 1640 performs a direct memory access operation in response to the received request. In doing so, and as indicated in block 1968, the accelerator sled 1640, in the illustrative embodiment, provides the request from the NIC 1652 (e.g., from the memory access logic unit 1654) to the accelerator device 1660 mapped to an address (e.g., the base address) associated with the request. As indicated in block 1970, the accelerator sled 1640 may add the request to a corresponding queue (e.g., a read queue or a write queue). In situations in which the accelerator sled 1660 has determined that the memory access request is directed to an accelerator device 1660 that is indirectly connected to the NIC 1652 (e.g., as described in block 1962), the accelerator sled 1640 forwards the request from the corresponding accelerator device 1660 that is directly connected to the NIC 1652 to the accelerator device that is indirectly connected to the NIC 1652 (e.g., from a primary FPGA 1720 to a secondary FPGA 1730), as indicated in block 1972. In the illustrative embodiment, the NIC 1652 (e.g., the memory access logic unit 1654 of the NIC 1652) sends, as a PCIe endpoint device, the request to the accelerator device 1660, which is configured as a PCIe root device (e.g., a PCIe root complex), as indicated in block 1974. In performing the direct memory access operation, the accelerator sled 1640 may write to the memory, as indicated in block 1976, such as by writing to the RAM, as indicated in block 1978, or by writing to a register, as indicated in block 1980. Alternatively, the accelerator sled 1640 may read from the memory, as indicated in block 1982, such as by reading from the RAM, as indicated in block 1984, or by reading from a register, as indicated in block 1986. Subsequently, the method 1900 advances to block 1988 of
Illustrative examples of the technologies disclosed herein are provided below. An embodiment of the technologies may include any one or more, and any combination of, the examples described below.
Example 1 includes an accelerator sled comprising an accelerator device including a memory; a network interface controller including a memory access logic unit to (i) determine a memory address region usable by a remote compute device to access the memory of the accelerator device, (ii) receive, from the remote compute device, a memory access request to remotely access the memory of the accelerator device associated with the memory address region, and (iii) perform, in response to the memory access request, a direct memory access operation on the memory.
Example 2 includes the subject matter of Example 1, and wherein to perform the direct memory access operation comprises to perform the direct memory access operation using a peripheral component interconnect express protocol in which the network interface controller is an endpoint device and the accelerator device is a root device.
Example 3 includes the subject matter of any of Examples 1 and 2, and wherein the memory access logic unit is further to establish a write queue in the memory, wherein the write queue is usable to track one or more write operations to be performed on the memory; provide, to the remote compute device, a unique identifier that identifies the queue.
Example 4 includes the subject matter of any of Examples 1-3, and wherein the memory access logic unit is further to receive a request from the remote compute device to establish the write queue, wherein the request defines a length for the write queue and wherein to establish the write queue comprises to establish the write queue with the length defined in the request.
Example 5 includes the subject matter of any of Examples 1-4, and wherein the memory access logic unit is further to establish a read queue in the memory, wherein the read queue is usable to track one or more write operations to be performed on the memory; provide, to the remote compute device, a unique identifier that identifies the queue.
Example 6 includes the subject matter of any of Examples 1-5, and wherein the memory access logic unit is further to receive a request from the remote compute device to establish the read queue, wherein the request defines a length for the read queue and wherein to establish the read queue comprises to establish the read queue with the length defined in the request.
Example 7 includes the subject matter of any of Examples 1-6, and wherein the accelerator device is a first accelerator device, the memory is a first memory, accelerator sled further comprises a second accelerator device that includes a second memory, the memory access request includes a unique identifier associated with a read queue or a write queue, and the memory access logic unit is further to determine, from the unique identifier, whether the direct memory access operation is to be performed on the first memory or the second memory.
Example 8 includes the subject matter of any of Examples 1-7, and wherein the accelerator device is a first accelerator device connected to the network interface controller, the accelerator sled further comprising a second accelerator device that is indirectly connected to the network interface controller through the first accelerator device, and the memory access request includes a memory address on which the direct memory access operation is to be performed, and wherein the memory access logic unit is further to determine, as a function of the memory address, whether the memory access request corresponds to the first accelerator device or the second accelerator device.
Example 9 includes the subject matter of any of Examples 1-8, and wherein the accelerator device is a first accelerator device, the accelerator sled further comprising a second accelerator device that is connected to the network interface controller, the memory access request includes a memory address on which the direct memory access operation is to be performed, and the memory access logic unit is further to determine, as a function of the memory address, whether the memory access request corresponds to the first accelerator device or the second accelerator device.
Example 10 includes the subject matter of any of Examples 1-9, and wherein to perform the direct memory access operation comprises to perform the direct memory access operation on a register of the accelerator device.
Example 11 includes the subject matter of any of Examples 1-10, and wherein to perform the direct memory access operation comprises to perform the direct memory access operation on a random access memory of the accelerator device.
Example 12 includes the subject matter of any of Examples 1-11, and wherein to perform the direct memory access operation comprises to perform a read operation.
Example 13 includes the subject matter of any of Examples 1-12, and wherein to perform the direct memory access operation comprises to perform a write operation.
Example 14 includes the subject matter of any of Examples 1-13, and wherein to perform the direct memory access operation comprises to add data indicative of the memory access operation to a queue associated with direct memory access operations to be performed on the memory of the accelerator device.
Example 15 includes the subject matter of any of Examples 1-14, and wherein the accelerator sled does not include a general purpose processor.
Example 16 includes the subject matter of any of Examples 1-15, and wherein the accelerator device is a field-programmable gate array (FPGA).
Example 17 includes a method comprising determining, by a memory access logic unit of a network interface controller of an accelerator sled, a memory address region usable by a remote compute device to access the memory of an accelerator device of the accelerator sled; receiving, by the memory access logic unit and from the remote compute device, a memory access request to remotely access the memory of the accelerator device associated with the memory address region; and performing, by the memory access logic unit and in response to the memory access request, a direct memory access operation on the memory.
Example 18 includes the subject matter of Example 17, and wherein performing the direct memory access operation comprises performing the direct memory access operation using a peripheral component interconnect express protocol in which the network interface controller is an endpoint device and the accelerator device is a root device.
Example 19 includes the subject matter of any of Examples 17 and 18, and further including establishing, by the memory access logic unit, a write queue in the memory, wherein the write queue is usable to track one or more write operations to be performed on the memory; and providing, by the memory access logic unit and to the remote compute device, a unique identifier that identifies the queue.
Example 20 includes the subject matter of any of Examples 17-19, and further including receiving, by the memory access logic unit, a request from the remote compute device to establish the write queue, wherein the request defines a length for the write queue and wherein establishing the write queue comprises establishing the write queue with the length defined in the request.
Example 21 includes the subject matter of any of Examples 17-20, and further including establishing, by the memory access logic unit, a read queue in the memory, wherein the read queue is usable to track one or more write operations to be performed on the memory; providing, by the memory access logic unit and to the remote compute device, a unique identifier that identifies the queue.
Example 22 includes the subject matter of any of Examples 17-21, and further including receiving, by the memory access logic unit, a request from the remote compute device to establish the read queue, wherein the request defines a length for the read queue and wherein establishing the read queue comprises establishing the read queue with the length defined in the request.
Example 23 includes the subject matter of any of Examples 17-22, and wherein the accelerator device is a first accelerator device, the memory is a first memory, the accelerator sled additionally includes a second accelerator device that includes a second memory, and the memory access request includes a unique identifier associated with a read queue or a write queue, the method further comprising determining, by the memory access logic unit and from the unique identifier, whether the direct memory access operation is to be performed on the first memory or the second memory.
Example 24 includes the subject matter of any of Examples 17-23, and wherein the accelerator device is a first accelerator device connected to the network interface controller, the accelerator sled further includes a second accelerator device that is indirectly connected to the network interface controller through the first accelerator device, and the memory access request includes a memory address on which the direct memory access operation is to be performed, the method further comprising determining, by the memory access logic unit and as a function of the memory address, whether the memory access request corresponds to the first accelerator device or the second accelerator device.
Example 25 includes the subject matter of any of Examples 17-24, and wherein the accelerator device is a first accelerator device, the accelerator sled further comprising a second accelerator sled that is connected to the network interface, and the memory access request includes a memory address on which the direct memory access operation is to be performed, the method further comprising determining, by the memory access logic unit and as a function of the memory address, whether the memory access request corresponds to the first accelerator device or the second accelerator device.
Example 26 includes the subject matter of any of Examples 17-25, and wherein performing the direct memory access operation comprises performing the direct memory access operation on a register of the accelerator device.
Example 27 includes the subject matter of any of Examples 17-26, and wherein performing the direct memory access operation comprises performing the direct memory access operation on a random access memory of the accelerator device.
Example 28 includes the subject matter of any of Examples 17-27, and wherein performing the direct memory access operation comprises performing a read operation.
Example 29 includes the subject matter of any of Examples 17-28, and wherein performing the direct memory access operation comprises performing a write operation.
Example 30 includes the subject matter of any of Examples 17-29, and wherein performing the direct memory access operation comprises adding data indicative of the memory access operation to a queue associated with direct memory access operations to be performed on the memory of the accelerator device.
Example 31 includes an accelerator sled comprising means for performing the method of any of Examples 17-30.
Example 32 includes one or more machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause an accelerator sled to perform the method of any of Examples 17-30.
Example 33 includes an accelerator sled comprising a compute engine to perform the method of any of Examples 17-30.
Example 34 includes an accelerator sled comprising an accelerator device including a memory; a network interface controller including memory access manager circuitry to (i) determine a memory address region usable by a remote compute device to access the memory of the accelerator device, (ii) receive, from the remote compute device, a memory access request to remotely access the memory of the accelerator device associated with the memory address region, and (iii) perform, in response to the memory access request, a direct memory access operation on the memory.
Example 35 includes the subject matter of Example 34, and wherein to perform the direct memory access operation comprises to perform the direct memory access operation using a peripheral component interconnect express protocol in which the network interface controller is an endpoint device and the accelerator device is a root device.
Example 36 includes the subject matter of any of Examples 34 and 35, and wherein the memory access manager circuitry is further to establish a write queue in the memory, wherein the write queue is usable to track one or more write operations to be performed on the memory; provide, to the remote compute device, a unique identifier that identifies the queue.
Example 37 includes the subject matter of any of Examples 34-36, and wherein the memory access manager circuitry is further to receive a request from the remote compute device to establish the write queue, wherein the request defines a length for the write queue and wherein to establish the write queue comprises to establish the write queue with the length defined in the request.
Example 38 includes the subject matter of any of Examples 34-37, and wherein the memory access manager circuitry is further to establish a read queue in the memory, wherein the read queue is usable to track one or more write operations to be performed on the memory; provide, to the remote compute device, a unique identifier that identifies the queue.
Example 39 includes the subject matter of any of Examples 34-38, and wherein the memory access manager circuitry is further to receive a request from the remote compute device to establish the read queue, wherein the request defines a length for the read queue and wherein to establish the read queue comprises to establish the read queue with the length defined in the request.
Example 40 includes the subject matter of any of Examples 34-39, and wherein the accelerator device is a first accelerator device, the memory is a first memory, accelerator sled further comprises a second accelerator device that includes a second memory, the memory access request includes a unique identifier associated with a read queue or a write queue, and the memory access manager circuitry is further to determine, from the unique identifier, whether the direct memory access operation is to be performed on the first memory or the second memory.
Example 41 includes the subject matter of any of Examples 34-40, and wherein the accelerator device is a first accelerator device connected to the network interface controller, the accelerator sled further comprising a second accelerator device that is indirectly connected to the network interface controller through the first accelerator device, and the memory access request includes a memory address on which the direct memory access operation is to be performed, and wherein the memory access manager circuitry is further to determine, as a function of the memory address, whether the memory access request corresponds to the first accelerator device or the second accelerator device.
Example 42 includes the subject matter of any of Examples 34-41, and wherein the accelerator device is a first accelerator device, the accelerator sled further comprising a second accelerator device that is connected to the network interface controller, the memory access request includes a memory address on which the direct memory access operation is to be performed, and the memory access manager circuitry is further to determine, as a function of the memory address, whether the memory access request corresponds to the first accelerator device or the second accelerator device.
Example 43 includes the subject matter of any of Examples 34-42, and wherein to perform the direct memory access operation comprises to perform the direct memory access operation on a register of the accelerator device.
Example 44 includes the subject matter of any of Examples 34-43, and wherein to perform the direct memory access operation comprises to perform the direct memory access operation on a random access memory of the accelerator device.
Example 45 includes the subject matter of any of Examples 34-44, and wherein to perform the direct memory access operation comprises to perform a read operation.
Example 46 includes the subject matter of any of Examples 34-45, and wherein to perform the direct memory access operation comprises to perform a write operation.
Example 47 includes the subject matter of any of Examples 34-46, and wherein to perform the direct memory access operation comprises to add data indicative of the memory access operation to a queue associated with direct memory access operations to be performed on the memory of the accelerator device.
Example 48 includes the subject matter of any of Examples 34-47, and wherein the accelerator sled does not include a general purpose processor.
Example 49 includes the subject matter of any of Examples 34-48, and wherein the accelerator device is a field-programmable gate array (FPGA).
Example 50 includes an accelerator sled comprising means for determining, with a network interface controller of an accelerator sled, a memory address region usable by a remote compute device to access the memory of an accelerator device of the accelerator sled; circuitry for receiving, from the remote compute device, a memory access request to remotely access the memory of the accelerator device associated with the memory address region; and means for performing, in response to the memory access request, a direct memory access operation on the memory.
Example 51 includes the subject matter of Example 50, and wherein the means for performing the direct memory access operation comprises circuitry for performing the direct memory access operation using a peripheral component interconnect express protocol in which the network interface controller is an endpoint device and the accelerator device is a root device.
Example 52 includes the subject matter of any of Examples 50 and 51, and further including circuitry for establishing a write queue in the memory, wherein the write queue is usable to track one or more write operations to be performed on the memory; circuitry for providing, to the remote compute device, a unique identifier that identifies the queue.
Example 53 includes the subject matter of any of Examples 50-52, and further including circuity for receiving a request from the remote compute device to establish the write queue, wherein the request defines a length for the write queue and wherein the circuitry or establishing the write queue comprises circuitry for establishing the write queue with the length defined in the request.
Example 54 includes the subject matter of any of Examples 50-53, and further including circuitry for establishing a read queue in the memory, wherein the read queue is usable to track one or more write operations to be performed on the memory; circuitry for providing, to the remote compute device, a unique identifier that identifies the queue.
Example 55 includes the subject matter of any of Examples 50-54, and further including circuitry for receiving a request from the remote compute device to establish the read queue, wherein the request defines a length for the read queue and wherein the circuitry for establishing the read queue comprises circuitry for establishing the read queue with the length defined in the request.
Example 56 includes the subject matter of any of Examples 50-55, and wherein the accelerator device is a first accelerator device, the memory is a first memory, the accelerator sled additionally includes a second accelerator device that includes a second memory, and the memory access request includes a unique identifier associated with a read queue or a write queue, the accelerator sled further comprising circuitry for determining, from the unique identifier, whether the direct memory access operation is to be performed on the first memory or the second memory.
Example 57 includes the subject matter of any of Examples 50-56, and wherein the accelerator device is a first accelerator device connected to the network interface controller, the accelerator sled further includes a second accelerator device that is indirectly connected to the network interface controller through the first accelerator device, and the memory access request includes a memory address on which the direct memory access operation is to be performed, the accelerator sled further comprising circuitry for determining, as a function of the memory address, whether the memory access request corresponds to the first accelerator device or the second accelerator device.
Example 58 includes the subject matter of any of Examples 50-57, and wherein the accelerator device is a first accelerator device, the accelerator sled further comprising a second accelerator sled that is connected to the network interface controller, and the memory access request includes a memory address on which the direct memory access operation is to be performed, the accelerator sled further comprising circuitry for determining, as a function of the memory address, whether the memory access request corresponds to the first accelerator device or the second accelerator device.
Example 59 includes the subject matter of any of Examples 50-58, and wherein the means for performing the direct memory access operation comprises circuitry for performing the direct memory access operation on a register of the accelerator device.
Example 60 includes the subject matter of any of Examples 50-59, and wherein the means for performing the direct memory access operation comprises circuitry for performing the direct memory access operation on a random access memory of the accelerator device.
Example 61 includes the subject matter of any of Examples 50-60, and wherein the means for performing the direct memory access operation comprises circuitry for performing a read operation.
Example 62 includes the subject matter of any of Examples 50-61, and wherein the means for performing the direct memory access operation comprises circuitry for performing a write operation.
Example 63 includes the subject matter of any of Examples 50-62, and wherein the means for performing the direct memory access operation comprises circuitry for adding data indicative of the memory access operation to a queue associated with direct memory access operations to be performed on the memory of the accelerator device.
Claims
1. An accelerator sled comprising:
- an accelerator device including a memory;
- a network interface controller including a memory access logic unit to (i) determine a memory address region usable by a remote compute device to access the memory of the accelerator device, (ii) receive, from the remote compute device, a memory access request to remotely access the memory of the accelerator device associated with the memory address region, and (iii) perform, in response to the memory access request, a direct memory access operation on the memory.
2. The accelerator sled of claim 1, wherein to perform the direct memory access operation comprises to perform the direct memory access operation using a peripheral component interconnect express protocol in which the network interface controller is an endpoint device and the accelerator device is a root device.
3. The accelerator sled of claim 1, wherein the memory access logic unit is further to:
- establish a write queue in the memory, wherein the write queue is usable to track one or more write operations to be performed on the memory;
- provide, to the remote compute device, a unique identifier that identifies the queue.
4. The accelerator sled of claim 1, wherein the memory access logic unit is further to receive a request from the remote compute device to establish the write queue, wherein the request defines a length for the write queue and wherein to establish the write queue comprises to establish the write queue with the length defined in the request.
5. The accelerator sled of claim 1, wherein the memory access logic unit is further to:
- establish a read queue in the memory, wherein the read queue is usable to track one or more write operations to be performed on the memory;
- provide, to the remote compute device, a unique identifier that identifies the queue.
6. The accelerator sled of claim 1, wherein the memory access logic unit is further to receive a request from the remote compute device to establish the read queue, wherein the request defines a length for the read queue and wherein to establish the read queue comprises to establish the read queue with the length defined in the request.
7. The accelerator sled of claim 1, wherein the accelerator device is a first accelerator device, the memory is a first memory, accelerator sled further comprises a second accelerator device that includes a second memory, the memory access request includes a unique identifier associated with a read queue or a write queue, and the memory access logic unit is further to determine, from the unique identifier, whether the direct memory access operation is to be performed on the first memory or the second memory.
8. The accelerator sled of claim 1, wherein the accelerator device is a first accelerator device connected to the network interface controller, the accelerator sled further comprising a second accelerator device that is indirectly connected to the network interface controller through the first accelerator device, and the memory access request includes a memory address on which the direct memory access operation is to be performed, and wherein the memory access logic unit is further to determine, as a function of the memory address, whether the memory access request corresponds to the first accelerator device or the second accelerator device.
9. The accelerator sled of claim 1, wherein the accelerator device is a first accelerator device, the accelerator sled further comprising a second accelerator device that is connected to the network interface controller, the memory access request includes a memory address on which the direct memory access operation is to be performed, and the memory access logic unit is further to determine, as a function of the memory address, whether the memory access request corresponds to the first accelerator device or the second accelerator device.
10. The accelerator sled of claim 1, wherein to perform the direct memory access operation comprises to perform the direct memory access operation on a register of the accelerator device.
11. The accelerator sled of claim 1, wherein to perform the direct memory access operation comprises to perform the direct memory access operation on a random access memory of the accelerator device.
12. The accelerator sled of claim 1, wherein to perform the direct memory access operation comprises to perform a read operation.
13. One or more machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause an accelerator sled to:
- determine, with a memory access logic unit of a network interface controller of the accelerator sled, a memory address region usable by a remote compute device to access the memory of an accelerator device of the accelerator sled;
- receive, with the memory access logic unit and from the remote compute device, a memory access request to remotely access the memory of the accelerator device associated with the memory address region; and
- perform, with the memory access logic unit and in response to the memory access request, a direct memory access operation on the memory.
14. The one or more machine-readable storage media of claim 13, wherein to perform the direct memory access operation comprises to perform the direct memory access operation using a peripheral component interconnect express protocol in which the network interface controller is an endpoint device and the accelerator device is a root device.
15. The one or more machine-readable storage media of claim 13, wherein the plurality of instructions further cause the accelerator sled to:
- establish, with the memory access logic unit, a write queue in the memory, wherein the write queue is usable to track one or more write operations to be performed on the memory;
- provide, with the memory access logic unit and to the remote compute device, a unique identifier that identifies the queue.
16. The one or more machine-readable storage media of claim 13, wherein the plurality of instructions further cause the accelerator sled to receive, with the memory access logic unit, a request from the remote compute device to establish the write queue, wherein the request defines a length for the write queue and wherein to establish the write queue comprises to establish the write queue with the length defined in the request.
17. The one or more machine-readable storage media of claim 13, wherein the plurality of instructions further cause the accelerator sled to:
- establish, with the memory access logic unit, a read queue in the memory, wherein the read queue is usable to track one or more write operations to be performed on the memory;
- provide, with the memory access logic unit and to the remote compute device, a unique identifier that identifies the queue.
18. The one or more machine-readable storage media of claim 13, wherein the plurality of instructions further cause the accelerator sled to receive, with the memory access logic unit, a request from the remote compute device to establish the read queue, wherein the request defines a length for the read queue and wherein to establish the read queue comprises to establish the read queue with the length defined in the request.
19. The one or more machine-readable storage media of claim 13, wherein the accelerator device is a first accelerator device, the memory is a first memory, the accelerator sled additionally includes a second accelerator device that includes a second memory, and the memory access request includes a unique identifier associated with a read queue or a write queue, wherein the plurality of instructions further cause the accelerator sled to determine, with the memory access logic unit and from the unique identifier, whether the direct memory access operation is to be performed on the first memory or the second memory.
20. The one or more machine-readable storage media of claim 13, wherein the accelerator device is a first accelerator device connected to the network interface controller, the accelerator sled further includes a second accelerator device that is indirectly connected to the network interface controller through the first accelerator device, and the memory access request includes a memory address on which the direct memory access operation is to be performed, wherein the plurality of instructions further cause the accelerator sled to determine, with the memory access logic unit and as a function of the memory address, whether the memory access request corresponds to the first accelerator device or the second accelerator device.
21. The one or more machine-readable storage media of claim 13, wherein the accelerator device is a first accelerator device, the accelerator sled further comprising a second accelerator sled that is connected to the network interface, and the memory access request includes a memory address on which the direct memory access operation is to be performed, wherein the plurality of instructions further cause the accelerator sled to determine, with the memory access logic unit and as a function of the memory address, whether the memory access request corresponds to the first accelerator device or the second accelerator device.
22. The one or more machine-readable storage media of claim 13, wherein to perform the direct memory access operation comprises to perform the direct memory access operation on a register of the accelerator device.
23. The one or more machine-readable storage media of claim 13, wherein to perform the direct memory access operation comprises to perform the direct memory access operation on a random access memory of the accelerator device.
24. The one or more machine-readable storage media of claim 13, wherein to perform the direct memory access operation comprises to perform a read operation.
25. An accelerator sled comprising:
- an accelerator device including a memory;
- a network interface controller including memory access manager circuitry to (i) determine a memory address region usable by a remote compute device to access the memory of the accelerator device, (ii) receive, from the remote compute device, a memory access request to remotely access the memory of the accelerator device associated with the memory address region, and (iii) perform, in response to the memory access request, a direct memory access operation on the memory.
26. A method comprising:
- determining, by a memory access logic unit of a network interface controller of an accelerator sled, a memory address region usable by a remote compute device to access the memory of an accelerator device of the accelerator sled;
- receiving, by the memory access logic unit and from the remote compute device, a memory access request to remotely access the memory of the accelerator device associated with the memory address region; and
- performing, by the memory access logic unit and in response to the memory access request, a direct memory access operation on the memory.
27. The method of claim 26, wherein performing the direct memory access operation comprises performing the direct memory access operation using a peripheral component interconnect express protocol in which the network interface controller is an endpoint device and the accelerator device is a root device.
28. The method of claim 26, further comprising:
- establishing, by the memory access logic unit, a write queue in the memory, wherein the write queue is usable to track one or more write operations to be performed on the memory;
- providing, by the memory access logic unit and to the remote compute device, a unique identifier that identifies the queue.
Type: Application
Filed: Dec 29, 2017
Publication Date: Feb 28, 2019
Inventor: Paul Dormitzer (Acton, MA)
Application Number: 15/858,549
