VARYING ENERGY BARRIERS OF MAGNETIC TUNNEL JUNCTIONS (MTJs) IN DIFFERENT MAGNETO-RESISTIVE RANDOM ACCESS MEMORY (MRAM) ARRAYS IN A SEMICONDUCTOR DIE TO FACILITATE USE OF MRAM FOR DIFFERENT MEMORY APPLICATIONS
Varying energy barriers of magnetic tunnel junctions (MTJs) in different magneto-resistive random access memory (MRAM) arrays in a semiconductor die to facilitate use of MRAM for different memory applications is disclosed. In one aspect, energy barriers of MTJs in different MRAM arrays are varied. The energy barrier of an MTJ affects its write performance as the amount of switching current required to switch the magnetic orientation of a free layer of the MTJ is a function of its energy barrier. Thus, by varying the energy barriers of the MTJs in different MRAM arrays in a semiconductor die, different MRAM arrays may be used for different types of memory provided in the semiconductor die while still achieving distinct performance specifications. The energy barrier of an MTJ can be varied by varying the materials, heights, widths, and/or other characteristics of MTJ stacks.
The technology of the disclosure relates generally to magneto-resistive random access memory (MRAM), and more particularly to magnetic tunnel junctions (MTJs) employed in MRAM.
II. BackgroundSemiconductor storage devices are used in integrated circuits (ICs) in electronic devices to provide data storage. One example of a semiconductor storage device is magneto-resistive random access memory (MRAM). MRAM is non-volatile memory in which data is stored by programming a magnetic tunnel junction (MTJ) as part of an MRAM bit cell. One advantage of MRAM is that MTJs in MRAM bit cells can retain stored information even when power is turned off. This is because data is stored in the MTJ as a small magnetic element rather than as an electric charge or current.
In this regard, an MTJ comprises a free ferromagnetic layer (“free layer”) disposed above or below a fixed or pinned ferromagnetic layer (“pinned layer”). The free and pinned layers are separated by a tunnel junction or barrier formed by a thin non-magnetic dielectric layer. The magnetic orientation of the free layer can be changed, but the magnetic orientation of the pinned layer remains fixed or “pinned.” Data can be stored in the MTJ according to the magnetic orientation between the free and pinned layers. When the magnetic orientations of the free and pinned layers are anti-parallel (AP) to each other, a first memory state exists (e.g., a logical ‘1’). When the magnetic orientations of the free and pinned layers are parallel (P) to each other, a second memory state exists (e.g., a logical ‘0’). The magnetic orientations of the free and pinned layers can be sensed to read data stored in the MTJ by sensing a resistance when current flows through the MTJ. Data can also be written and stored in the MTJ by applying a magnetic field to change the orientation of the free layer to either a P or AP magnetic orientation with respect to the pinned layer.
Recent developments in MTJ devices involve spin transfer torque (STT)-MRAM devices. In STT-MRAM devices, the spin polarization of carrier electrons, rather than a pulse of a magnetic field, is used to program the state stored in the MTJ (i.e., a ‘0’ or a ‘1’).
With continuing reference to
The write current Iw can change the magnetic orientation of the free layer 112 by transferring a sufficient amount of energy from the write current Iw to the free layer 112 of the MTJ 100. This amount of energy is called an energy barrier Eb of the MTJ 100. The energy barrier Eb of the MTJ 100 is the amount of energy required to switch the magnetic orientation of the MTJ 100. The energy barrier Eb is based in part on intrinsic characteristics of the MTJ stack 116. For example, varying material types, heights, and/or widths of the MTJ stack 116 can vary the energy barrier Eb of the MTJ 100. The energy barrier Eb of the MTJ 100 can also be varied by external influences, such as ambient temperature, for example.
Aspects of device performance, such as data retention rates and access times, can be controlled by varying the energy barriers of MTJs, such as the energy barrier Eb of the MTJ 100 in
In this manner, MTJs having a higher energy barrier may be better suited for memory applications requiring higher data retention rates and slower access times than for memory applications requiring faster access times and lower data retention rates. For example, an MTJ having a higher energy barrier may be better suited for a memory application such as eFlash memory, which requires a higher data retention rate at a tradeoff cost of slower access times, than for a memory application such as main memory, which requires faster access times at a tradeoff cost of lower data retention rates. In contrast, an MTJ having a lower energy barrier may be better suited for a memory application requiring faster access times at a tradeoff cost of a lower data retention rate. For example, level 2 (L2) and level 3 (L3) cache memory in a processor-based system may be specified to operate with faster access times, whereas main memory may be specified to have increased data retention as an acceptable tradeoff to faster access times. Thus, MRAM having a lower energy barrier might be better suited for L2/L3 cache memory than for main memory. However, since advanced IC designs place multiple types of memory proximate on the same IC, such as system-on-a-chip (SoC) technologies, the lower resolution limits of conventional fabrication processes can force different MRAM arrays to be fabricated with the same MTJ stack, resulting in different MRAM arrays having the same heights, widths, and other characteristics in proximity to one another. Consequently, the energy barriers of the MTJ stacks used in different types of memory are required to be the same and have essentially the same performance, although not optimal nor desired.
SUMMARY OF THE DISCLOSUREAspects disclosed in the detailed description include varying energy barriers of magnetic tunnel junctions (MTJs) in different magneto-resistive random access memory (MRAM) arrays in a semiconductor die to facilitate use of MRAM for different memory applications. Different memory applications may require different tradeoffs between access times and data retention performance as an example, where using MTJ stacks having the same energy barrier in these different memory applications may not allow the desired differences in performance to be realized. Thus, in this regard, in exemplary aspects disclosed herein, to facilitate use of MRAM for different types of memories having different performance requirements in a semiconductor die, the energy barriers of MTJs that form the MRAM bit cells in different MRAM arrays in the semiconductor die are varied. The energy barrier of an MTJ in an MRAM bit cell affects the write performance of the MRAM bit cell, because the amount of switching current required to switch the magnetic orientation of a free layer of the MTJ is a function of its energy barrier. Thus, by varying energy barriers of MTJs in MRAM bit cells in different MRAM arrays in a semiconductor die, different MRAM arrays may be used for different types of memory provided in the semiconductor die while still achieving distinct performance specifications, such as access times, data retention rates, bit cell endurances, array densities, and/or power consumption rates, as examples. The energy barrier of an MTJ in an MRAM bit cell can be varied by varying the materials, heights, widths, and/or other characteristics of MTJ stacks.
In other aspects disclosed herein, MTJs having different energy barriers are fabricated in the same layer(s) of the semiconductor die to avoid having to provide additional layers in the semiconductor die for different MRAMs. In one example, to fabricate MTJs having different energy barriers in the same layer(s) of the semiconductor die, a fabrication process is employed that includes forming a first blocking layer over a second bottom via, which is in an interconnect layer of a semiconductor die. Once the second bottom via is covered by the first blocking layer, a first MTJ stack film is deposited over a first bottom via in the interconnect layer of the semiconductor die. A portion of the first MTJ stack film is then removed to form a first MTJ stack from the first MTJ stack film. The first MTJ stack is then masked by a hard mask, and a second MTJ stack film is deposited over the second bottom via. A portion of the second MTJ stack film is then removed to form a second MTJ stack from the second MTJ stack film. Each MTJ stack can be formed at varying heights and/or widths, and from varying combinations of materials, as examples, such that the first MTJ stack can have an energy barrier different from the second MTJ stack. In this manner, the MTJs having different energy barriers can provide memory devices having varying performance specifications in the same layer(s) of a semiconductor die.
In this regard in one exemplary aspect, a semiconductor die comprising a first MTJ stack and a second MTJ stack is provided. The first MTJ stack comprises a first pinned layer having a first pinned layer magnetic moment, a first free layer having a first free layer magnetic moment, and a first tunnel barrier layer disposed between the first pinned layer and the first free layer. The first MTJ stack has a first energy barrier. The second MTJ stack comprises a second pinned layer having a second pinned layer magnetic moment, a second free layer having a second free layer magnetic moment, and a second tunnel barrier layer disposed between the second pinned layer and the second free layer. The second MTJ stack has a second energy barrier different from the first energy barrier.
In another exemplary aspect, a semiconductor die comprising a first means for storing data and a second means for storing data is provided. The first means for storing data comprises a first means for storing a fixed magnetic moment having a first fixed magnetic moment, a first means for storing a programmable magnetic moment having a first programmable magnetic moment, and a first means for transferring spin polarization of electrons disposed between the first means for storing a fixed magnetic moment and the first means for storing a programmable magnetic moment. The first means for storing data has a first energy barrier. The second means for storing data comprises a second means for storing a fixed magnetic moment having a second fixed magnetic moment, a second means for storing a programmable magnetic moment having a second programmable magnetic moment, and a second means for transferring spin polarization of electrons disposed between the second means for storing a fixed magnetic moment and the second means for storing a programmable magnetic moment. The second means for storing data has a second energy barrier different from the first energy barrier.
In another exemplary aspect, a method of varying energy barriers of MTJs in different MRAM array in a semiconductor die is provided. The method comprises forming a first blocking layer over a second via of a second MRAM array, wherein the second via is in an interconnect layer of the semiconductor die. A first MTJ stack film is deposited over a first via of a first MRAM array and at least a portion of the first blocking layer. The first via is in the interconnect layer of the semiconductor die. A first top electrode film is deposited over the first MTJ stack film. A first mask is deposited over a portion of the first top electrode film over the first MTJ stack film over the first via. A portion of the first top electrode film and a portion of the first MTJ stack film not under the first mask are removed to form a first top electrode layer over a first MTJ stack over the first via of the first MRAM array. At least a portion of the first blocking layer over the second via of the second MRAM array is removed. A second MTJ stack film is deposited over the second via of the second MRAM array. A second top electrode film is deposited over the second MTJ stack film. A second mask is then deposited over a portion of the second top electrode film over the second MTJ stack film over the second via. A portion of the second top electrode film and a portion of the second MTJ stack film not under the second mask are removed to form a second top electrode layer over a second MTJ stack over the second via of the second MRAM array.
In another exemplary aspect, a central processing unit (CPU) system comprising a system bus, at least one CPU core communicatively coupled to the system bus, a memory controller communicatively coupled to the system bus, and a memory system communicatively coupled to the system bus is provided. The memory system comprises a first MRAM bit cell of a first MRAM array and a second MRAM bit cell of a second MRAM array. The first MRAM bit cell of the first MRAM array comprises a first MTJ stack, a first MTJ, and a first access transistor. The first MTJ stack comprises a first pinned layer having a first pinned layer magnetic moment, a first free layer having a first free layer magnetic moment, and a first tunnel barrier layer disposed between the first pinned layer and the first free layer. The first MTJ stack has a first energy barrier. The first MTJ comprises a first top electrode layer and a first bottom electrode layer, wherein the first MTJ stack is disposed between the first top electrode layer and the first bottom electrode layer. The first access transistor comprises a first gate, a first source, and a first drain. The first access transistor is coupled to the first MTJ. The second MRAM bit cell of the second MRAM array comprises a second MTJ stack, a second MTJ, and a second access transistor. The second MTJ stack comprises a second pinned layer having a second pinned layer magnetic moment, a second free layer having a second free layer magnetic moment, and a second tunnel barrier layer disposed between the second pinned layer and the second free layer. The second MTJ stack has a second energy barrier different from the first energy barrier. The second MTJ comprises a second top electrode layer and a second bottom electrode layer, wherein the second MTJ stack is disposed between the second top electrode layer and the second bottom electrode layer. The second access transistor comprises a second gate, a second source, and a second drain.
With reference now to the drawing figures, several exemplary aspects of the present disclosure are described. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.
Aspects disclosed in the detailed description include varying energy barriers of magnetic tunnel junctions (MTJs) in different magneto-resistive random access memory (MRAM) arrays in a semiconductor die to facilitate use of MRAM for different memory applications. Different memory applications may require different tradeoffs between access times and data retention performance as an example, where using MTJ stacks having the same energy barrier in these different memory applications may not allow the desired differences in performance to be realized. Thus, in this regard, in exemplary aspects disclosed herein, to facilitate use of MRAM for different types of memories having different performance requirements in a semiconductor die, the energy barriers of MTJs that form the MRAM bit cells in different MRAM arrays in the semiconductor die are varied. The energy barrier of an MTJ in an MRAM bit cell affects the write performance of the MRAM bit cell, because the amount of switching current required to switch the magnetic orientation of a free layer of the MTJ is a function of its energy barrier. Thus, by varying energy barriers of MTJs in MRAM bit cells in different MRAM arrays in a semiconductor die, different MRAM arrays may be used for different types of memory provided in the semiconductor die while still achieving distinct performance specifications, such as access times, data retention rates, bit cell endurances, array densities, and/or power consumption rates, as examples. The energy barrier of an MTJ in an MRAM bit cell can be varied by varying the materials, heights, widths, and/or other characteristics of MTJ stacks.
In many processor-based systems, different memory applications can be provided. For example, cache memory can be provided to store data that is frequently accessed by a processor during operation. Main memory can be provided to store data that is accessed less often than data in cache memory, but more often than data in long-term memory. Long-term memory can be provided to store large amounts of data that are accessed less often than data in main memory. Since the data stored in each of these memory applications are accessed at varying frequencies, each memory application can have different access times requirements. For example, cache memory can be required to have faster access times than main memory because providing faster access times in cache memory can increase device speed to a greater extent than providing faster access times in main memory. Long-term memory access times can have even further reduced access times requirements for a similar reason. It would be desirable to use MRAM as the type of memory for all of these memory applications because MRAM has high data retention rates and consumes a low amount of power.
For example, eFlash memory, cache memory, and main memory using MRAM bit cells in MRAM arrays may be required on a single semiconductor die. In using MRAM for different memory applications, it is desirable to have high data retention rates and fast access times because high data retention rates increase device reliability and fast access times increase device speed. For example, for cache memory, reducing access times can be favored over increasing retention rates because the main goal of cache memory can be to enable high-speed processing. In long-term memory, such as eFlash memory for example, increasing retention rates can be favored over reducing access times because the main goal of eFlash can be to provide long-term reliable data storage. Main memory can favor performance specifications between those required for cache memory and those required for eFlash memory because main memory can be used as intermediate memory between long-term memory and cache memory.
However, in MRAM, increasing the retention rate can come at the expense of slowing down access times. Conversely, reducing the retention rate in MRAM can allow for faster access times. This is because retention rates and access times of an MTJ in an MRAM bit cell are based on an energy barrier of the MTJ. An energy barrier of an MTJ is an amount of energy required to change a magnetic orientation of a free layer of the MTJ. Factors that affect the energy barrier of an MTJ include widths and/or material types of the various layers of an MTJ. Increasing an energy barrier of an MTJ makes the MTJ more resilient to external effects such as temperature variation, leakage current, and stray capacitance, because such external effects must transfer a higher amount of energy to change the magnetic orientation of a free layer of the MTJ. However, increasing the energy barrier of the MTJ slows access times because a write current, for example, must transfer a higher amount of energy to the free layer of the MTJ, which requires a longer period of time at a fixed voltage. Therefore, although it is desirable to have high data retention rates and fast access times in MRAM, tradeoffs must be made between retention rates and access times.
In many applications, such as system-on-a-chip (SoC) devices, different types of memory requiring different performance specifications may be required in a memory system on a single semiconductor die. For example, it may be desired to use MRAM for eFlash memory, cache memory, and main memory on a single semiconductor die, because MRAM has high data retention rates and consumes a low amount of power. In this regard,
The MRAM bit cells 201(1)(1)-201(3)(P) provided in the MRAM arrays 208(1)-208(3) may require different access times based on their memory application. For example, the third plurality of MRAM bit cells 201(3) in the third MRAM array 208(3) used for eSRAM cache memory, for example, may require faster access times than the first plurality of MRAM bit cells 201(1) in the first MRAM array 208(1) used for eFlash memory, because eSRAM cache memory is used in high-speed processing more often than eFlash memory. Thus, lower data retention rates might be an acceptable tradeoff to provide faster access times for the MRAM bit cells 201(3)(1)-201(3)(P) in the third MRAM array 208(3) used for cache memory. Conversely, the first plurality of MRAM bit cells 201(1)(1)-201(1)(M) in the first MRAM array 208(1) used for eFlash memory may require higher data retention rates than the third plurality of MRAM bit cells 201(3) in the third MRAM array 208(3) used for cache memory, because eFlash memory is used in long-term memory requiring increased reliability more often than cache memory. Main memory (eDRAM) may require higher data retention rates than cache memory, but may also require faster access times than eFlash memory. This is because main memory (eDRAM) is often used as intermediate memory between long-term memory and cache memory (eSRAM). In this manner, the second plurality of MRAM bit cells 201(2) in the second MRAM array 208(2) used for main memory (eDRAM) may require performance specifications between those required for the first plurality of MRAM bit cells 201(1) in the first MRAM array 208(1) used for eFlash memory and those required for the third plurality of MRAM bit cells 201(3) in the third MRAM array 208(3) used for cache memory (eSRAM). Thus, for applications requiring different types of memory using MRAM on a semiconductor die, it may be desirable to provide MRAM bit cells in MRAM arrays having varying performance specifications on a single semiconductor die.
In examples discussed below, the MRAM bit cells 201(1)(1)-201(3)(P) in the MRAM arrays 208(1)-208(3) are fabricated to have varying performance specifications in the semiconductor die 200 by varying energy barriers of the MTJs 202(1)-202(3) in the MRAM bit cells 201(1)(1)-201(3)(P). For example,
In this regard, each MTJ 202(1)-202(3) in
In this example, and as will be discussed in more detail below, the MRAM arrays 208(1)-208(3) having MRAM bit cells 201(1)(1)-201(3)(P) with varying energy barriers Eb(1)-Eb(3) to vary performance specifications are also fabricated in a same layer of the semiconductor die 200 to avoid fabricating the MRAM arrays 208(1)-208(3) in different layers to avoid increasing the height of the semiconductor die 200 in the Y-axis direction. In this regard, each MTJ 202(1)-202(3) in
When reading or writing data to each MTJ 202(1)-202(3), the gate G1-G3 of the respective access transistor 228(1)-228(3) is activated by activating the respective associated word line WL1-WL3. In a write operation, for example, a write current is generated between the drain D1-D3 and the source S1-S3 of each access transistor 228(1)-228(3) and across each MTJ 202(1)-202(3). If the magnetic moment MFL(1)-MFL(3) of each free layer 211(1)-211(3) of each MTJ 202(1)-202(3) is to be changed from AP to P, a write current flowing from each free layer 211(1)-211(3) to each respective pinned layer 213(1)-213(3) is generated. If the magnetic moment MFL(1)-MFL(3) of each free layer 211(1)-211(3) of each MTJ 202(1)-202(3) is to be changed from P to AP relative to the respective pinned layer 213(1)-213(3), a write current flowing from each pinned layer 213(1)-213(3) to each respective free layer 211(1)-211(3) is generated. Thus, in this manner, each access transistor 228(1)-228(3) controls the read/write current across each respective MTJ 202(1)-202(3).
A read operation is different from a write operation in that the amount of current necessary to perform a write operation is higher than the amount of current necessary to perform a read operation. As noted above, a higher current transfers a higher amount of energy to a free layer of the MTJ. If one MTJ has a higher energy barrier than another MTJ, then the MTJ with the higher energy barrier can require a higher write current to perform a write operation on the MTJ. For example, performing a write operation on the first MTJ 202(1) in
Factors that affect the energy barriers Eb(1)-Eb(3) of the MTJs 202(1)-202(3) include the material(s) used to form the MTJ stacks 204(1)-204(3) as well as heights H1-H3 and widths W1-W3 of the layers in the MTJ stacks 204(1)-204(3). The materials used to form the MTJ stacks 204(1)-204(3) influence the respective energy barriers Eb(1)-Eb(3) because the energy barriers Eb(1)-Eb(3) of the respective MTJ stacks 204(1)-204(3) are associated with resistances of the respective MTJ stacks 204(1)-204(3). By fabricating the MTJ stacks 204(1)-204(3) from strong free layer magnetic moment materials, the MTJ stacks 204(1)-204(3) can have higher energy barriers Eb(1)-Eb(3). For example, forming the first free layer 211(1) of the first MTJ 202(1) from a first material can result in the first MTJ 202(1) having the first energy barrier Eb(1). Similarly, forming the second free layer 211(2) of the second MTJ 202(2) from a second material can result in the second MTJ 202(2) having the second energy barrier Eb(2) different from the first energy barrier Eb(1). If the first energy barrier Eb(1) is greater than the second energy barrier Eb(2), then the first MTJ 202(1) may have a higher data retention rate and a slower switching speed than the second MTJ 202(2). In this manner, the materials used to form the layers of the MTJ stacks 204(1)-204(3) can influence the energy barriers Eb(1)-Eb(3) of the MTJs 202(1)-202(3), and thus the performance specifications of the MTJs 202(1)-202(3).
The heights H1-H3 and widths W1-W3 of the layers in the MTJ stacks 204(1)-204(3) can also influence the energy barriers Eb(1)-Eb(3) of the MTJ stacks 204(1)-204(3). For example, forming the first free layer 211(1) of the first MTJ 202(1) to a first width W1 can result in the first MTJ 202(1) having the first energy barrier Eb(1). Similarly, forming the second free layer 211(2) of the second MTJ 202(2) to a second width W2 can result in the second MTJ 202(2) having the second energy barrier Eb(2) different from the first energy barrier Eb(1). Similar to the discussion above, if the first energy barrier Eb(1) is greater than the second energy barrier Eb(2), then the first MTJ 202(1) may have a higher data retention rate and a slower switching speed than the second MTJ 202(2). In this manner, the widths W1-W3 of the layers of the MTJ stacks 204(1)-204(3) can influence the energy barriers Eb(1)-Eb(3) of the respective MTJs 202(1)-202(3), and thus the performance specifications of the MTJs 202(1)-202(3).
As discussed above, to vary the energy barriers Eb(1)-Eb(3) among the MRAM bit cells 201(1)(1)-201(3)(P), the MTJ stacks 204(1)-204(3) can be formed from different material compositions that can affect the energy barriers Eb(1)-Eb(3) of the MTJs 202(1)-202(3). For example, the bottom electrode layer 210(1)-210(3) of each MTJ 202(1)-202(3) can include materials such as tantalum (Ta), tantalum (Ta) nitride (N) (TaN), tungsten (W), copper (Cu)-based materials, Ruthenium (Ru), platinum (Pt), Hafnium (Hf) iridide (Ir) (HfIr), Terbium (Tb)-Cobalt (Co)-Iron (Fe) (TbCoFe), and/or TbWFe, as non-limiting examples. The bottom electrode layer 210(1)-210(3) of each MTJ 202(1)-202(3) can include a thickness in the range of approximately 5-20 nanometers (nm), as non-limiting examples. The top electrode layer 209(1)-209(3) of each MTJ 202(1)-202(3) can include materials such as Ta, TaN, titanium (Ti), titanium nitride (TiN), Ru, W, Pt, HfIr, TbCoFe, and/or TbWFe, as non-limiting examples. The top electrode layer 209(1)-209(3) of each MTJ 202(1)-202(3) can include a thickness in the range of approximately 15-80 nm, as a non-limiting example.
Similarly, the free layers 211(1)-211(3) of the MTJ stacks 204(1)-204(3) can be formed from different material compositions that can affect the energy barriers Eb(1)-Eb(3) of the MTJs 202(1)-202(3). An energy barrier of an MTJ can be determined by calculating the effective anisotropy energy constant (Keff) of the MTJ, which is equal to the anisotropy field (Hk) times one-half the saturation magnetization (Ms). Since the anisotropy field (Hk) and the saturation magnetization (Ms) can both be measured, the effective anisotropy energy constant (Keff) can be calculated using the equation, Keff=Hk*Ms/2. Once the effective anisotropy energy constant (Keff) is calculated, the energy barrier Eb can be calculated using the equation, Eb=(Keff*V)/(KB*T), where V is the volume of the free layer, T is temperature, and KB is the Bohr magneton. Aspects disclosed herein can include, for a CoFeB-based free layer, an anisotropy field (Hk) between approximately 2000-5000 Oersteds (Oe), and a saturation magnetization (Ms) between approximately 300-1300 emu/cc. In at least one example, for the first free layer 211(1) of the first MTJ 202(1), materials can include Co, Fe, B, and CoFeB-based materials. In this manner, having the first MTJ 202(1) used for eFlash memory, for example, can include having a high Keff such that Hk is greater than 3500 Oe and Ms is greater than 800 emu/cc. The second free layer 211(2) of the second MTJ 202(2) can include materials such as Co, Fe, B, and CoFeB-based materials. In this regard, having the second MTJ 202(2) used for main memory (eDRAM), for example, can include having a Keff such that Hk is approximately equal to 3000 Oe and Ms is approximately between 600-800 emu/cc. The third free layer 211(3) of the third MTJ 202(3) can include materials such as Co, Fe, B, and CoFeB-based materials. In this regard, having the third MTJ 202(3) used for eSRAM cache memory, for example, can include having a Keff such that Hk is approximately less than 2500 Oe and Ms is approximately less than 600 emu/cc.
Similarly, to vary the energy barriers Eb(1)-Eb(3) between the MRAM bit cells 201(1)(1)-201(3)(P), the pinned layers 213(1)-213(3) of the MTJ stacks 204(1)-204(3) can be formed from different material compositions that can affect the energy barriers Eb(1)-Eb(3) of the MTJs 202(1)-202(3). For example, the first pinned layer 213(1) of the first MTJ 202(1) can include materials such as Co, Pt, Co/Pt-based materials, B, and/or CoFeB-based materials. The second pinned layer 213(2) of the second MTJ 202(2) can include materials such as Co, Nickel (Ni), Co/Ni-based materials, Pt, Co/Pt-based materials, B, and/or CoFeB-based materials. The third pinned layer 213(3) of the third MTJ 202(3) can include materials such as Co, Ni, CoNi-based materials, Fe, B, and/or CoFeB-based materials.
Similarly, to vary the energy barriers Eb(1)-Eb(3) among the MRAM bit cells 201(1)(1)-201(3)(P), the tunnel barrier layers 212(1)-212(3) of the MTJ stacks 204(1)-204(3) can be formed from different material compositions that can affect the energy barriers Eb(1)-Eb(3) of the MTJs 202(1)-202(3). For example, the first tunnel barrier layer 212(1) can include resistance area products (RAs) such as approximately 8-10 ohm-micrometers squared (Ωμm2) and tunnel magnetoresistances (TMRs) approximately 150%. The second tunnel barrier layer 212(2) can include RAs such as approximately 5-8 Ωμm2 and TMRs approximately 200%. The third tunnel barrier layer 212(3) can include RAs such as less than 5 Ωμm2 and TMRs approximately 200%.
Critical dimensions of the first MTJ 202(1) can include critical dimensions greater than seventy (70) nm. Critical dimensions of the second MTJ 202(2) can include critical dimensions between approximately thirty-five (35) and seventy (70) nm. Critical dimensions of the third MTJ 202(3) can include critical dimensions less than thirty-five (35) nm. Retention rates of the first MTJ 202(1) can include ten (10) years at one hundred twenty-five (125) degrees Celsius (C). Retention rates of the second MTJ 202(2) can include ten (10) years at eighty-five (85) degrees Celsius (C). Retention rates of the third MTJ 202(3) can include a few days or months at eighty-five (85) degrees Celsius (C). Energy barriers Eb(1)-Eb(3) can be in the range of approximately 80-100 electronvolts (eV) for eFlash, approximately 50-60 eV for eSRAM, and approximately 60-70 eV for eDRAM, as non-limiting examples. MTJ stacks 204(1)-204(3) can have heights between approximately 15-80 nm, as non-limiting examples. Pinned layers 213(1)-213(3) for eFlash can include Co/Pt-based materials for a multilayer (ML) and CoFeB-based materials for a synthetic antiferromagnetic (SAF) layer. Pinned layers 213(1)-213(3) for eDRAM can include Co/Pt-based materials for a ML and CoFeB-based materials for an SAF layer. Pinned layers 213(1)-213(3) for eSRAM for cache memory can include Co/Ni-based materials for a ML and CoFeB-based materials for an SAF layer, as non-limiting examples. Each access transistor 228(1)-228(3) can be a planar n-type metal-oxide semiconductor (MOS) (NMOS) or p-type MOS (PMOS) type transistor, an NMOS or PMOS Fin field-effect transistor (FinFET), or a silicon-on-insulator (SOI) NMOS or PMOS type transistor, as non-limiting examples. Each first bottom via 218(1)-218(3) can include materials such as Ta, TaN, W, and Cu-based materials, such that each first bottom via 218(1)-218(3) can have heights between approximately 5-20 nm, and widths larger or smaller than the width of each MTJ 202(1)-202(3), as non-limiting examples. Each second bottom via 222(1)-222(3) can include materials such as Cu, W, Ta, and/or Ta/TaN, and have heights between approximately 50-100 nm, as non-limiting examples. Each bottom metal line 220(1)-220(3) can include materials such as Cu, W, and/or Ta/TaN, and have heights between approximately 50-100 nm and widths between approximately 30-100 nm, as non-limiting examples. The diffusion barrier layer 224 can include materials such as silicon nitride (SiN), SiCON, and/or silicon oxynitride (SiON), and have heights such as approximately 10-30 nm, as non-limiting examples. The inter-metal layer 226 can include materials such as silicon dioxide (SiO2), SiON, and/or SiN, and have heights between approximately 50-100 nm, as non-limiting examples.
In
In this regard, a first step of the fabrication process 300 in
The semiconductor die 200 can be provided by processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), photolithography, reactive ion etching (RIE), etch, chemical mechanical planarization (CMP), and/or wet/dry cleaning processes, as non-limiting examples. The semiconductor layer 230 can comprise materials such as Si, SiO, a high-k oxide material, a metal gate material, B, phosphorous (P), arsenic (As), Ti, Co, Ni, and/or silicon germanium (SiGe), as non-limiting examples. The voltage source VS(1)-VS(3) of each access transistor 228(1)-228(3) can be a single voltage source or some combination of different voltage sources, and can provide voltages in the range of approximately 0.5-1.8 volts (V), as non-limiting examples. The bottom electrode film 434 can comprise materials including Ta, TaN, W, Cu, Ru, Ti, and/or TiN, and can have heights between approximately 10-20 nm, as non-limiting examples. The bottom electrode film 434 can be deposited using a process such as PVD, as a non-limiting example. The first blocking layer 432(1) can comprise materials such as SiO2, SiN, and/or SiCON, and can be formed using a process such as CVD, as a non-limiting example. The first photoresist mask 438(1) can be deposited using processes such as spin coating, as a non-limiting example.
Once the first blocking layer 432(1) is formed over the second bottom interconnect 214(2) in the Y-axis direction, the first MTJ stack film 436(1) can be deposited so as to later form the first MTJ stack 204(1) from the first MTJ stack film 436(1). The fabrication process 300 in
Once the first MTJ film stack 436(1) is deposited, a first mask, which is first hard mask 442(1) in this example, can be deposited over a portion of the first MTJ film stack 436(1) in the Y-axis direction in a later step to protect that portion while another portion is removed. The fabrication process 300 in
The fabrication process 300 in
The fabrication process 300 in
The fabrication process 300 in
The fabrication process 300 in
The fabrication process 300 in
In this regard,
In this regard,
In this regard,
In this regard,
Varying energy barriers of MTJs in different MRAM arrays in a semiconductor die to facilitate use of MRAM for different memory applications according to aspects disclosed herein may be provided in or integrated into any processor-based device. Examples, without limitation, include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter.
In this regard,
Other master and slave devices can be connected to the system bus 1008. As illustrated in
The CPU(s) 1002 may also be configured to access the display controller(s) 1020 over the system bus 1008 to control information sent to one or more displays 1026. The display controller(s) 1020 sends information to the display(s) 1026 to be displayed via one or more video processors 1028, which process the information to be displayed into a format suitable for the display(s) 1026. The display(s) 1026 can include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, etc.
In another example, a semiconductor die including a first means for storing data and a second means for storing data can be provided. The first means for storing data comprises a first means for storing a fixed magnetic moment having a first fixed magnetic moment, and a first means for storing a programmable magnetic moment having a first programmable magnetic moment. The first means for storing data also comprises a first means for transferring spin polarization of electrons disposed between the first means for storing the fixed magnetic moment and the first means for storing the programmable magnetic moment. The first means for storing data has a first energy barrier. The second means for storing data comprises a second means for storing a fixed magnetic moment having a second fixed magnetic moment, and a second means for storing a programmable magnetic moment having a second programmable magnetic moment. The second means for storing data also comprises a second means for transferring spin polarization of electrons disposed between the second means for storing the fixed magnetic moment and the second means for storing the programmable magnetic moment. The second means for storing data has a second energy barrier different from the first energy barrier.
Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer readable medium and executed by a processor or other processing device, or combinations of both. The arbiters, master devices, and slave devices described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).
The aspects disclosed herein may be embodied in hardware and in instructions that are stored in hardware, and may reside, for example, in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.
It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A semiconductor die, comprising:
- a first magnetic tunnel junction (MTJ) stack, comprising: a first pinned layer having a first pinned layer magnetic moment; a first free layer having a first free layer magnetic moment; and a first tunnel barrier layer disposed between the first pinned layer and the first free layer, wherein the first MTJ stack has a first energy barrier; and
- a second MTJ stack, comprising: a second pinned layer having a second pinned layer magnetic moment; a second free layer having a second free layer magnetic moment; and a second tunnel barrier layer disposed between the second pinned layer and the second free layer, wherein the second MTJ stack has a second energy barrier different from the first energy barrier.
2. The semiconductor die of claim 1, wherein:
- the first energy barrier of the first MTJ stack is an amount of energy to substantially invert a direction of the first free layer magnetic moment in the first free layer; and
- the second energy barrier of the second MTJ stack is an amount of energy to substantially invert a direction of the second free layer magnetic moment in the second free layer.
3. The semiconductor die of claim 2, wherein:
- the first pinned layer further comprises a first material; and
- the second pinned layer further comprises a second material different from the first material of the first pinned layer such that the second energy barrier of the second MTJ stack is different from the first energy barrier of the first MTJ stack.
4. The semiconductor die of claim 3, wherein:
- the first material of the first pinned layer comprises one or more of Cobalt (Co), Platinum (Pt), and Nickel (Ni); and
- the second material of the second pinned layer comprises one of more of Co, Pt, and Ni.
5. The semiconductor die of claim 2, wherein:
- the first free layer further comprises a first material; and
- the second free layer further comprises a second material different from the first material of the first free layer such that the second energy barrier of the second MTJ stack is different from the first energy barrier of the first MTJ stack.
6. The semiconductor die of claim 5, wherein:
- the first material of the first free layer comprises one or more of Cobalt (Co), Iron (Fe), and Boron (B) such that the first free layer has a first effective anisotropy energy constant; and
- the second material of the second free layer comprises one or more of Co, Fe, and B such that the second free layer has a second effective anisotropy energy constant less than the first effective anisotropy energy constant.
7. The semiconductor die of claim 2, wherein:
- the first tunnel barrier layer further comprises a first material; and
- the second tunnel barrier layer further comprises a second material different from the first material of the first tunnel barrier layer such that the second energy barrier of the second MTJ stack is different from the first energy barrier of the first MTJ stack.
8. The semiconductor die of claim 2, wherein:
- the first pinned layer further comprises a first width; and
- the second pinned layer further comprises a second width different from the first width of the first pinned layer such that the second energy barrier of the second MTJ stack is different from the first energy barrier of the first MTJ stack.
9. The semiconductor die of claim 2, wherein:
- the first free layer further comprises a first width; and
- the second free layer further comprises a second width different from the first width of the first free layer such that the second energy barrier of the second MTJ stack is different from the first energy barrier of the first MTJ stack.
10. The semiconductor die of claim 9, wherein:
- the first width of the first free layer comprises a width less than thirty-five (35) nanometers (nm), between thirty-five (35) nm and seventy (70) nm, or greater than seventy (70) nm; and
- the second width of the second free layer comprises a width less than thirty-five (35) nm, between thirty-five (35) nm and seventy (70) nm, or greater than seventy (70) nm.
11. The semiconductor die of claim 2, wherein:
- the first tunnel barrier layer further comprises a first width; and
- the second tunnel barrier layer further comprises a second width different from the first width of the first tunnel barrier layer such that the second energy barrier of the second MTJ stack is different from the first energy barrier of the first MTJ stack.
12. The semiconductor die of claim 11, wherein:
- the first width of the first tunnel barrier layer is associated with a first resistance area product of the first tunnel barrier layer such that the first resistance area product comprises a resistance area product of less than five (5) ohm-micrometers squared (Ωμm2), between five (5) and eight (8) Ωμm2, or between eight (8) and ten (10) Ωμm2; and
- the second width of the second tunnel barrier layer is associated with a second resistance area product of the second tunnel barrier layer such that the second resistance area product comprises a resistance area product of less than five (5) Ωμm2, between five (5) and eight (8) Ωμm2, or between eight (8) and ten (10) Ωμm2.
13. The semiconductor die of claim 1, further comprising:
- a third MTJ stack, comprising: a third pinned layer having a third pinned layer magnetic moment; a third free layer having a third free layer magnetic moment; and a third tunnel barrier layer disposed between the third pinned layer and the third free layer, wherein the third MTJ stack has a third energy barrier different from the first energy barrier and the second energy barrier.
14. The semiconductor die of claim 1, further comprising:
- a first magneto-resistive random access memory (MRAM) bit cell of a first MRAM array, comprising: a first MTJ comprising a first top electrode layer and a first bottom electrode layer, wherein the first MTJ stack is disposed between the first top electrode layer and the first bottom electrode layer; and a first access transistor comprising a first gate, a first source, and a first drain, the first access transistor coupled to the first MTJ; and
- a second MRAM bit cell of a second MRAM array, comprising: a second MTJ comprising a second top electrode layer and a second bottom electrode layer, wherein the second MTJ stack is disposed between the second top electrode layer and the second bottom electrode layer; and a second access transistor comprising a second gate, a second source, and a second drain, the second access transistor coupled to the second MTJ.
15. The semiconductor die of claim 14, wherein the first MTJ of the first MRAM bit cell of the first MRAM array and the second MTJ of the second MRAM bit cell of the second MRAM array are in a same layer of the semiconductor die.
16. The semiconductor die of claim 14, wherein:
- the first energy barrier of the first MTJ stack is lower than the second energy barrier of the second MTJ stack;
- the first MRAM bit cell of the first MRAM array is configured as an MRAM bit cell in embedded static random access memory (eSRAM); and
- the second MRAM bit cell of the second MRAM array is configured as an MRAM bit cell in embedded dynamic random access memory (eDRAM).
17. The semiconductor die of claim 14, wherein:
- the first energy barrier of the first MTJ stack is lower than the second energy barrier of the second MTJ stack;
- the first MRAM bit cell of the first MRAM array is configured as an MRAM bit cell in embedded static random access memory (eSRAM); and
- the second MRAM bit cell of the second MRAM array is configured as an MRAM bit cell in eFlash memory.
18. The semiconductor die of claim 14, wherein:
- the first energy barrier of the first MTJ stack is lower than the second energy barrier of the second MTJ stack;
- the first MRAM bit cell of the first MRAM array is configured as an MRAM bit cell in embedded dynamic random access memory (eDRAM); and
- the second MRAM bit cell of the second MRAM array is configured as an MRAM bit cell in eFlash memory.
19. The semiconductor die of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.
20. A semiconductor die, comprising:
- a first means for storing data, comprising: a first means for storing a fixed magnetic moment having a first fixed magnetic moment; a first means for storing a programmable magnetic moment having a first programmable magnetic moment; and a first means for transferring spin polarization of electrons disposed between the first means for storing the fixed magnetic moment and the first means for storing the programmable magnetic moment, wherein the first means for storing data has a first energy barrier; and
- a second means for storing data, comprising: a second means for storing a fixed magnetic moment having a second fixed magnetic moment; a second means for storing a programmable magnetic moment having a second programmable magnetic moment; and a second means for transferring spin polarization of electrons disposed between the second means for storing the fixed magnetic moment and the second means for storing the programmable magnetic moment, wherein the second means for storing data has a second energy barrier different from the first energy barrier.
21. A method of varying energy barriers of magnetic tunnel junctions (MTJs) in different magneto-resistive random access memory (MRAM) arrays in a semiconductor die, comprising:
- forming a first blocking layer over a second via of a second MRAM array, wherein the second via is in an interconnect layer of the semiconductor die;
- depositing a first MTJ stack film over a first via of a first MRAM array and at least a portion of the first blocking layer, wherein the first via is in the interconnect layer of the semiconductor die;
- depositing a first top electrode film over the first MTJ stack film;
- depositing a first mask over a portion of the first top electrode film over the first MTJ stack film over the first via;
- removing a portion of the first top electrode film and a portion of the first MTJ stack film not under the first mask to form a first top electrode layer over a first MTJ stack over the first via of the first MRAM array;
- removing at least a portion of the first blocking layer over the second via of the second MRAM array;
- depositing a second MTJ stack film over the second via of the second MRAM array;
- depositing a second top electrode film over the second MTJ stack film;
- depositing a second mask over a portion of the second top electrode film over the second MTJ stack film over the second via; and
- removing a portion of the second top electrode film and a portion of the second MTJ stack film not under the second mask to form a second top electrode layer over a second MTJ stack over the second via of the second MRAM array.
22. The method of claim 21, further comprising:
- removing the first mask; and
- forming a second blocking layer over the first MTJ stack of the first MRAM array, wherein: depositing the second MTJ stack film over the second via of the second MRAM array comprises depositing the second MTJ stack film over the second via of the second MRAM array and at least a portion of the second blocking layer.
23. The method of claim 22, wherein:
- depositing the first MTJ stack film over the first via of the first MRAM array and at least the portion of the first blocking layer comprises depositing a first pinned film, a first tunnel barrier film, and a first free film over the first via of the first MRAM array and at least the portion of the first blocking layer; and
- depositing the second MTJ stack film over the second via of the second MRAM array and at least the portion of the second blocking layer comprises depositing a second pinned film, a second tunnel barrier film, and a second free film over the second via of the second MRAM array and at least the portion of the second blocking layer, wherein the interconnect layer further comprises a bottom electrode film over the first via of the first MRAM array and the second via of the second MRAM array.
24. The method of claim 22, wherein:
- depositing the first MTJ stack film over the first via of the first MRAM array and at least the portion of the first blocking layer comprises depositing a first bottom electrode film, a first pinned film, a first tunnel barrier film, and a first free film over the first via of the first MRAM array and at least the portion of the first blocking layer; and
- depositing the second MTJ stack film over the second via of the second MRAM array and at least the portion of the second blocking layer comprises depositing a second bottom electrode film, a second pinned film, a second tunnel barrier film, and a second free film over the second via of the second MRAM array and at least the portion of the second blocking layer.
25. The method of claim 23, further comprising:
- removing a portion of the bottom electrode film not under the first MTJ stack and the second MTJ stack to form a first bottom electrode layer under the first MTJ stack and a second bottom electrode layer under the second MTJ stack.
26. The method of claim 25, further comprising:
- forming a spacer film adjacent to the first MTJ stack and the second MTJ stack;
- depositing a dielectric layer adjacent to the spacer film and over the first MTJ stack and the second MTJ stack;
- removing a portion of the dielectric layer over the first MTJ stack and the second MTJ stack to expose a first top surface of the first top electrode layer and a second top surface of the second top electrode layer;
- forming a first top electrode via over the first top surface of the first top electrode layer; and
- forming a second top electrode via over the second top surface of the second top electrode layer.
27. The method of claim 26, wherein forming the spacer film adjacent to the first MTJ stack and the second MTJ stack comprises forming the spacer film adjacent to the first MTJ stack and the second MTJ stack to expose a top surface of the interconnect layer of the semiconductor die.
28. The method of claim 22, further comprising:
- forming the first blocking layer over a third via of a third MRAM array, wherein the third via is in the interconnect layer of the semiconductor die;
- removing at least a portion of the first blocking layer over the third via of the third MRAM array;
- forming the second blocking layer over a third MTJ stack of the third MRAM array;
- removing at least a portion of the second blocking layer over the third via of the third MRAM array;
- depositing a third MTJ stack film over the third via of the third MRAM array;
- depositing a third top electrode film over the third MTJ stack film;
- depositing a third mask over a portion of the third top electrode film over the third MTJ stack film over the third via; and
- removing a portion of the third top electrode film and a portion of the third MTJ stack film not under the third mask to form a third top electrode layer over the third MTJ stack over the third via of the third MRAM array.
29. A central processing unit (CPU) system, comprising:
- a system bus;
- at least one CPU core communicatively coupled to the system bus;
- a memory controller communicatively coupled to the system bus; and
- a memory system communicatively coupled to the system bus, comprising: a first magneto-resistive random access memory (MRAM) bit cell of a first MRAM array, comprising: a first magnetic tunnel junction (MTJ) stack, comprising: a first pinned layer having a first pinned layer magnetic moment; a first free layer having a first free layer magnetic moment; and
- a first tunnel barrier layer disposed between the first pinned layer and the first free layer, wherein the first MTJ stack has a first energy barrier; a first MTJ comprising a first top electrode layer and a first bottom electrode layer, wherein the first MTJ stack is disposed between the first top electrode layer and the first bottom electrode layer; and a first access transistor comprising a first gate, a first source, and a first drain, the first access transistor coupled to the first MTJ; and
- a second MRAM bit cell of a second MRAM array, comprising: a second MTJ stack, comprising: a second pinned layer having a second pinned layer magnetic moment; a second free layer having a second free layer magnetic moment; and a second tunnel barrier layer disposed between the second pinned layer and the second free layer, wherein the second MTJ stack has a second energy barrier different from the first energy barrier; a second MTJ comprising a second top electrode layer and a second bottom electrode layer, wherein the second MTJ stack is disposed between the second top electrode layer and the second bottom electrode layer; and a second access transistor comprising a second gate, a second source, and a second drain, the second access transistor coupled to the second MTJ.
Type: Application
Filed: Aug 28, 2017
Publication Date: Feb 28, 2019
Inventors: Xia Li (San Diego, CA), Wei-Chuan Chen (San Diego, CA), Wah Nam Hsu (San Diego, CA), Seung Hyuk Kang (San Diego, CA)
Application Number: 15/688,212