SEMICONDUCTOR DEVICE
A semiconductor device includes an active layer, source electrodes, drain electrodes, gate electrodes, an insulating layer, gate metal layers, source metal layers, and drain metal layers. The source electrodes, drain electrodes, and gate electrodes are over the active layer, in which each of the gate electrodes includes a plurality of narrow portions and wider portions alternately arranged, and the wider portions of one of the gate electrodes extend toward the source electrode and directly connected to the wider portions of another one of the gate electrodes. The insulating layer is over the source electrodes, the drain electrodes, and the gate electrodes. The gate metal layers are over the gate electrodes and the insulating layer. The source metal layers are over the source electrodes and the insulating layer. The drain metal layers are over the drain electrodes and the insulating layer.
The present application is a Continuation Application of the U.S. application Ser. No. 15/236,497, filed Aug. 15, 2016, which are herein incorporated by reference in its entirety
BACKGROUND Field of DisclosureThe present disclosure relates to a semiconductor device. More particularly, the present disclosure relates to a high electron mobility transistor (HEMT).
Description of Related ArtA nitride semiconductor has high electric breakdown field and high electron saturation velocity. Thus, the nitride semiconductor is expected to be a semiconductor material for semiconductor devices having high breakdown voltage and low on-state resistance. Many of the conventional semiconductor devices using the nitride related materials may have heterojunctions. The heterojunction is configured with two types of nitride semiconductors having different bandgap energies from each other and is able to generate a two-dimensional electron gas layer (2 DEG layer) near the junction plane. The semiconductor devices having the heterojunction may achieve a low on-state resistance. These types of semiconductor devices are called high electron mobility transistors (HEMT).
SUMMARYAn aspect of the present disclosure provides a semiconductor device includes an active layer, a plurality of source electrodes, drain electrodes, and gate electrodes, an insulating layer, a plurality of gate metal layers, a plurality of source metal layers, and a plurality of drain metal layers. The source electrodes, drain electrodes, and gate electrodes are over the active layer, in which each of the gate electrodes includes a plurality of narrow portions and wider portions alternately arranged, and the wider portions of one of the gate electrodes extend toward the source electrode and are directly connected to the wider portions of another one of the gate electrodes. The insulating layer is over the source electrodes, the drain electrodes, and the gate electrodes. The gate metal layers are over the gate electrodes and the insulating layer. The source metal layers are over the source electrodes and the insulating layer. The drain metal layers are over the drain electrodes and the insulating layer.
In some embodiments of the present disclosure, the gate metal layers and the gate electrodes have substantially the same pattern.
In some embodiments of the present disclosure, the source electrodes include a plurality of source blocks spaced from each other.
In some embodiments of the present disclosure, the source blocks are disposed between the connected gate electrodes.
In some embodiments of the present disclosure, the wider portions of the gate electrodes extend in between the source blocks.
In some embodiments of the present disclosure, at least one of the source blocks is enclosed by the gate electrodes.
In some embodiments of the present disclosure, a projection of all of the gate electrodes onto the active layer in a direction normal to an upper surface of the active layer is separated from a projection of the source electrodes onto the active layer in a direction normal to an upper surface of the active layer and a projection of the drain electrodes onto the active layer in a direction normal to an upper surface of the active layer.
An aspect of the present disclosure provides a semiconductor device includes an active layer, a plurality of source electrodes, drain electrodes, and gate electrodes, an insulating layer, a plurality of gate metal layers, a plurality of source metal layers, and a plurality of drain metal layers. The source electrodes, drain electrodes, and gate electrodes are over the active layer, in which each of the source electrodes includes a plurality of source blocks spaced from each other. The insulating layer is over the source electrodes, the drain electrodes, and the gate electrodes. The gate metal layers are over the gate electrodes and the insulating layer. The source metal layers are over the source electrodes and the insulating layer. The drain metal layers are over the drain electrodes and the insulating layer.
In some embodiments of the present disclosure, portions of the gate electrodes extend to spaces between the source blocks of the source electrodes.
In some embodiments of the present disclosure, the semiconductor device further includes a plurality of vias electrically connecting the gate electrodes to the gate metal layers, in which the vias are directly connected to the portions of the gate electrodes extending to the spaces between the source blocks of the source electrodes.
In some embodiments of the present disclosure, each of the gate electrodes includes a plurality of narrow portions and wider portions alternately arranged.
In some embodiments of the present disclosure, the wider portions of one of the gate electrodes extend toward the source electrode and directly connected to the wider portions of another one of the gate electrodes.
In some embodiments of the present disclosure, the narrow portions and the wider portions are alternately arranged along a direction, and the source blocks are arranged along the direction.
In some embodiments of the present disclosure, at least one of the source metal layers includes a plurality of source blocks spaced from each other, and the source blocks of the at least one of the source metal layers overlap the source blocks of the at least one of the source electrodes.
An aspect of the present disclosure provides a semiconductor device includes an active layer, a plurality of source electrodes, drain electrodes, and gate electrodes, an insulating layer, a plurality of gate metal layers, a plurality of source metal layers, and a plurality of drain metal layers. The source electrodes, drain electrodes, and gate electrodes are over the active layer, in which at least two of the gate electrodes form a ladder-shape. The insulating layer is over the source electrodes, the drain electrodes, and the gate electrodes. The gate metal layers are over the gate electrodes and the insulating layer. The source metal layers are over the source electrodes and the insulating layer. The drain metal layers are over the drain electrodes and the insulating layer.
In some embodiments of the present disclosure, at least one of the source electrodes includes a plurality of source blocks.
In some embodiments of the present disclosure, the source blocks of the source electrodes are disposed between the gate electrodes formed in ladder-shape.
In some embodiments of the present disclosure, the source blocks of the source electrodes are spaced from each other by the gate electrodes formed in ladder-shape.
In some embodiments of the present disclosure, at least one of the source blocks of the source electrode is surrounded by the gate electrodes.
In some embodiments of the present disclosure, at least two of the gate metal layers form a ladder-shape.
Reference will now be made in detail to the present embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
An active layer 120 is formed on the substrate 110. The active layer 120 includes a buffer layer 122 and a barrier layer 124. The buffer layer 122 is disposed on the substrate 110, and the barrier layer 124 is disposed on the buffer layer 122. The buffer layer 122 can provide a uniform crystal structure for epitaxial deposition, and thus can be optionally included for improved device characteristics. In some embodiments, the buffer layer 122 can be a nitride based material to provide good adhesion for the layers formed thereon and also solve issues of lattice mismatch, but the present disclosure is not limited in this respect. The buffer layer 122 can be a single layer such as an InxAlyGa1-x-yN layer, or can be a composite layer. The barrier layer 124 can be made of materials having a larger band gap than the buffer layer 122, such as AlGaN. In some embodiments, the barrier layer 124 can be doped or undoped. A charge accumulates at the interface between the buffer layer 122 and the barrier layer 124 and creates a two dimensional electron gas (2 DEG) 123. The 2 DEG 123 has high electron mobility which gives the semiconductor device a high transconductance at high frequencies.
A plurality of gate layers 130 are formed on the substrate 110. For example, a semiconductor layer (not shown) is formed on the barrier layer 124, and is then patterned. The patterned semiconductor layers are doped to be the gate layers 130. The gate layer 130 includes p-type material.
Reference is made to
A plurality of source electrodes 150 and a plurality of drain electrodes 160 are respectively formed in the first openings 142 and the second openings 144. That is, the source electrodes 150 and the drain electrodes 160 are alternately arranged along a second direction D2 different from the first direction. For example, the second direction D2 is substantially perpendicular to the first direction D1. In some embodiments, the source electrodes 150 and the drain electrodes 160 are made of conductive materials, such as metal, and the source electrodes 150 and the drain electrodes 160 are electrically connected to the 2 DEG 123.
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Since the gate metal layers 210 are connected to the gate electrodes 170, the resistance of the whole gate (the gate electrodes 170 and the gate metal layers 210) of the semiconductor device can be reduced. Furthermore, the vias 196 are disposed between the wider portions 212 of the gate metal layers 210 and the wider portions 172 of the gate electrodes 170. The wider portions 172 of the gate electrodes 170 have flat top surface, such that the formation of the vias 196 can be improved, and the vias 196 provide good connection between the gate metal layers 210 and the gate electrodes 170.
The first source metal layers 220 are respectively formed above the source electrodes 150. That is, the vias 192 are disposed between and connected to the source electrodes 150 and the first source metal layers 220. In some embodiments, the first source metal layers 220 and the source electrodes 150 have the substantially same or similar patterns. For example, in
The drain metal layers 240 are respectively formed above the drain electrodes 160. That is, the vias 194 are disposed between and connected to the drain electrodes 160 and the drain metal layers 240. In some embodiments, the drain metal layers 240 and the drain electrodes 160 have the substantially same or similar patterns. For example, in
The second source metal layers 230 are disposed on the first insulating layer 180 and respectively between the gate metal layers 210 and the drain metal layers 240. The second source metal layers 230 are configured to disperse the electrical field of the semiconductor device to increase the breakdown voltage. At least one of the second metal layers 230 includes at least one wider portion 232 and at least one narrow portion 234 alternately arranged along the first direction D1. The width W7 of the wider portion 232 is wider than the width W8 of the narrow portion 234. For example, in
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A plurality of source blocks 152 and a plurality of drain electrodes 160 are respectively formed in the first openings 142 and the second openings 144. The source blocks 152 disposed between the adjacent gate layers 130 are arranged along the first direction D1 and form a source electrode 150. In other words, the source blocks 152 of the source electrode 150 are surrounded by the connected gate layers 130.
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Since the gate metal layers 210 are connected to the gate electrodes 170, the resistance of the whole gate (the gate electrodes 170 and the gate metal layers 210) of the semiconductor device can be reduced. Furthermore, the vias 196 are disposed between the wider portions 212 of the gate metal layers 210 and the wider portions 172 of the gate electrodes 170. The wider portions 172 of the gate electrodes 170 have flat top surface, such that the formation of the vias 196 can be improved, and the vias 196 provide good connection between the gate metal layers 210 and the gate electrodes 170.
The first source metal layers 220 are respectively formed above the source electrodes 150. At least one of the first source metal layers 220 includes a plurality of source blocks 222 separated from each other. The source blocks 222 of the first source metal layers 220 are respectively disposed above the source blocks 152 of the source electrodes 150. At least one of the source blocks 222 of the first source metal layers 220 is surrounded by the connected gate metal layers 210. The vias 192 are disposed between and connected to the source blocks 152 of the source electrodes 150 and the source blocks 222 of the first source metal layers 220. In some embodiments, the first source metal layers 220 and the source electrodes 150 have the substantially same or similar patterns. For example, in
The drain metal layers 240 are respectively formed above the drain electrodes 160. That is, the vias 194 are disposed between and connected to the drain electrodes 160 and the drain metal layers 240. In some embodiments, the drain metal layers 240 and the drain electrodes 160 have the substantially same or similar patterns. For example, in
The second source metal layers 230 are disposed on the first insulating layer 180 and respectively between the gate metal layers 210 and the drain metal layers 240. The second source metal layers 230 are configured to disperse the electrical field of the semiconductor device to increase the breakdown voltage. In
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Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure covers modifications and variations of this disclosure provided they fall within the scope of the following claims.
Claims
1. A semiconductor device comprising:
- an active layer;
- a plurality of source electrodes, drain electrodes, and gate electrodes over the active layer, wherein each of the gate electrodes comprises a plurality of narrow portions and wider portions alternately arranged, and the wider portions of one of the gate electrodes extend toward the source electrodes and are directly connected to the wider portions of another one of the gate electrodes;
- an insulating layer over the source electrodes, the drain electrodes, and the gate electrodes;
- a plurality of gate metal layers over the gate electrodes and the insulating layer;
- a plurality of source metal layers over the source electrodes and the insulating layer; and
- a plurality of drain metal layers over the drain electrodes and the insulating layer.
2. The semiconductor device of claim 1, wherein the gate metal layers and the gate electrodes have substantially the same pattern.
3. The semiconductor device of claim 1, wherein the source electrodes comprise a plurality of source blocks spaced from each other.
4. The semiconductor device of claim 3, wherein the source blocks are disposed between the connected gate electrodes.
5. The semiconductor device of claim 3, wherein the wider portions of the gate electrodes extend to spaces between the source blocks of the source electrodes.
6. The semiconductor device of claim 3, wherein at least one of the source blocks is enclosed by the gate electrodes.
7. The semiconductor device of claim 1, wherein a projection of all of the gate electrodes onto the active layer in a direction normal to an upper surface of the active layer is separated from a projection of the source electrodes onto the active layer in a direction normal to an upper surface of the active layer and a projection of the drain electrodes onto the active layer in a direction normal to an upper surface of the active layer.
8. A semiconductor device comprising:
- an active layer;
- a plurality of source electrodes, drain electrodes, and gate electrodes over the active layer, wherein each of the source electrodes comprises a plurality of source blocks spaced from each other;
- an insulating layer over the source electrodes, the drain electrodes, and the gate electrodes;
- a plurality of gate metal layers over the gate electrodes and the insulating layer;
- a plurality of source metal layers over the source electrodes and the insulating layer; and
- a plurality of drain metal layers over the drain electrodes and the insulating layer.
9. The semiconductor device of claim 8, wherein portions of the gate electrodes extend to spaces between the source blocks of the source electrodes.
10. The semiconductor device of claim 9, further comprising a plurality of vias electrically connecting the gate electrodes to the gate metal layers, wherein the vias are directly connected to the portions of the gate electrodes extending to the spaces between the source blocks of the source electrodes.
11. The semiconductor device of claim 8, wherein each of the gate electrodes comprises a plurality of narrow portions and wider portions alternately arranged.
12. The semiconductor device of claim 11, wherein the wider portions of one of the gate electrodes extend toward the source electrode and are directly connected to the wider portions of another one of the gate electrodes.
13. The semiconductor device of claim 11, wherein the narrow portions and the wider portions are alternately arranged along a direction, and the source blocks are arranged along the direction.
14. The semiconductor device of claim 8, wherein at least one of the source metal layers comprises a plurality of source blocks spaced from each other, and the source blocks of the at least one of the source metal layers overlap the source blocks of the at least one of the source electrodes.
15. A semiconductor device comprising:
- an active layer;
- a plurality of source electrodes, drain electrodes, and gate electrodes over the active layer, wherein at least two of the gate electrodes form a ladder-shape;
- an insulating layer over the source electrodes, the drain electrodes, and the gate electrodes;
- a plurality of gate metal layers over the gate electrodes and the insulating layer;
- a plurality of source metal layers over the source electrodes and the insulating layer; and
- a plurality of drain metal layers over the drain electrodes and the insulating layer.
16. The semiconductor device of claim 15, wherein at least one of the source electrodes comprises a plurality of source blocks.
17. The semiconductor device of claim 16, wherein the source blocks of the source electrodes are disposed between the gate electrodes formed in ladder-shape.
18. The semiconductor device of claim 16, wherein the source blocks of the source electrodes are spaced from each other by the gate electrodes formed in ladder-shape.
19. The semiconductor device of claim 15, wherein at least one of the source blocks of the source electrode is surrounded by the gate electrodes.
20. The semiconductor device of claim 15, wherein at least two of the gate metal layers form a ladder-shape.
Type: Application
Filed: Feb 14, 2019
Publication Date: Jun 20, 2019
Inventors: Li-Fan LIN (Taoyuan City), Chun-Chieh YANG (Taoyuan City)
Application Number: 16/275,345