MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND A COMMON PLATE
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a substrate, a conductive plate located over the substrate to couple a ground connection, a data line located between the substrate and the conductive plate, a memory cell, and a conductive line. The memory cell includes a first transistor and a second transistor. The first transistor includes a first region electrically coupled between the data line and the conductive plate, and a charge storage structure electrically separated from the first region. The second transistor includes a second region electrically coupled to the charge storage structure and the data line. The conductive line is electrically separated from the first and second regions and spans across part of the first region of the first transistor and part of the second region of the second transistor and forming a gate of the first and second transistors.
This application claims the benefit of priority to U.S. Provisional Application Ser. No. 62/892,988, filed Aug. 28, 2019, which is incorporated herein by reference in its entirety.
BACKGROUNDMemory devices are widely used in computers and many other electronic items to store information. Memory devices are generally categorized into two types: volatile memory devices and non-volatile memory devices. A memory device usually has numerous memory cells to store information. In a volatile memory device, information stored in the memory cells is lost if supply power is disconnected from the memory device. In a non-volatile memory device, information stored in the memory cells is retained even if supply power is disconnected from the memory device.
The description herein involves volatile memory devices. Most conventional volatile memory devices store information in the form of charge in a capacitor structure included in the memory cell. As demand for device storage density increases, many conventional techniques provide ways to shrink the size of the memory cell in order to increase device storage density for a given device area. However, physical limitations and fabrication constraints may pose a challenge to such conventional techniques if the memory cell size is to be shrunk to a certain dimension. Unlike some conventional memory devices, the memory devices described herein include features that can overcome challenges faced by conventional techniques.
The memory device described herein includes volatile memory cells in which each of the memory cells can include two transistors (2T). One of the two transistors has a charge storage structure, which can form a memory element of the memory cell to store information. The memory device described herein can have a structure (e.g., a 4F2 cell footprint) that allows the size of the memory device to be relatively smaller than the size of similar conventional memory devices. The described memory device can include a single access line (e.g., word line) to control two transistors of a memory cell. This can lead to reduced power dissipation and improved processing. Each of the memory cells of the described memory device can include a cross-point gain cell structure (and cross-point operation), such that a memory cell can be accessed using a single access line (e.g., word line) and single data line (e.g., bit line) during an operation (e.g., a read or write operation) of the memory device. Other improvements and benefits of the described memory device and its variations are discussed below with reference to
In a physical structure of memory device 100, each of memory cells 102 can include transistors (e.g., two transistors) formed vertically (e.g., stacked on different layers) in different levels over a substrate (e.g., semiconductor substrate) of memory device 100. Memory device 100 can also include multiple levels (e.g., multiple decks) of memory cells where one level (e.g., one deck) of memory cells can be formed over (e.g., stacked on) another level (e.g., another deck) of additional memory cells. The structure of memory array 101, including memory cells 102, can include the structure of memory arrays and memory cells described below with reference to
As shown in
Memory device 100 can include an address register 106 to receive address information ADDR (e.g., row address signals and column address signals) on lines (e.g., address lines) 107. Memory device 100 can include row access circuitry (e.g., X-decoder) 108 and column access circuitry (e.g., Y-decoder) 109 that can operate to decode address information ADDR from address register 106. Based on decoded address information, memory device 100 can determine which memory cells 102 are to be accessed during a memory operation. Memory device 100 can perform a write operation to store information in memory cells 102 and a read operation to read (e.g., sense) information (e.g., previously stored information) in memory cells 102. Memory device 100 can also perform an operation (e.g., a refresh operation) to refresh (e.g., to keep valid) the value of information stored in memory cells 102. Each of memory cells 102 can be configured to store information that can represent at most one bit (e.g., a single bit having a binary 0 (“0”) or a binary 1 (“1”), or more than one bit (e.g., multiple bits having a combination of at least two binary bits).
Memory device 100 can receive a supply voltage, including supply voltages Vcc and Vss, on lines 130 and 132, respectively. Supply voltage Vss can operate at a ground potential (e.g., having a value of approximately zero volts). Supply voltage Vcc can include an external voltage supplied to memory device 100 from an external power source such as a battery or an alternating current to direct current (AC-DC) converter circuitry.
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Memory device 100 can include sensing circuitry 103, select circuitry 115, and input/output (I/O) circuitry 116. Column access circuitry 109 can selectively activate signals on lines (e.g., select lines) based on address signals ADDR. Select circuitry 115 can respond to the signals on lines 114 to select signals on data lines 105. The signals on data lines 105 can represent the values of information to be stored in memory cells 102 (e.g., during a write operation) or the values of information read (e.g., sensed) from memory cells 102 (e.g., during a read operation).
I/O circuitry 116 can operate to provide information read from memory cells 102 to lines 112 (e.g., during a read operation) and to provide information from lines 112 (e.g., provided by an external device) to data lines 105 to be stored in memory cells 102 (e.g., during a write operation). Lines 112 can include nodes within memory device 100 or pins (or solder balls) on a package where memory device 100 can reside. Other devices external to memory device 100 (e.g., a hardware memory controller or a hardware processor) can communicate with memory device 100 through lines 107, 112, and 120.
Memory device 100 may include other components, which are not shown in
Each of memory cells 210 through 215 can include two transistors T1 and T2. Thus, each of memory cells 210 through 215 can be called a 2T memory cell (e.g., 2T gain cell). Each of transistors T1 and T2 can include a field-effect transistor (FET). As an example, transistor T1 can be a p-channel FET (PFET), and transistor T2 can be an n-channel FET (NFET). Part of transistor T1 can include a structure of a p-channel metal-oxide semiconductor (PMOS) transistor FET (PFET). Thus, transistor T1 can include an operation similar to that of a PMOS transistor. Part of transistor T2 can include a structure of an n-channel metal-oxide semiconductor (NMOS). Thus, transistor T2 can include an operation similar to that of a NMOS transistor.
Transistor T1 of memory device 200 can include a charge-storage based structure (e.g., a floating-gate based). As shown in
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Memory cells 210 through 215 can be arranged in memory cell groups 2010 and 2011.
Memory device 200 can perform a write operation to store information in memory cells 210 through 215 and a read operation to read (e.g., sense) information from memory cells 210 through 215. Memory device 200 can be configured to operate as a DRAM device. However, unlike some conventional DRAM devices that store information in a structure such as a container for a capacitor, memory device 200 can store information in the form of charge in charge storage structure 202 (which can be a floating gate structure). As mentioned above, charge storage structure 202 can be the floating gate of transistor T1. During an operation (e.g., a read or write operation) of memory device 200, an access line (e.g., a single access line) and a data line (e.g., a single data line) can be used to access a selected memory cell (e.g., target memory cell).
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In memory device 200, a single access line (e.g., a single word line) can be used to control (e.g., turn on or turn off) transistors T1 and T2 of a respective memory cell during either a read or write operation of memory device 200. Some conventional memory devices may use multiple (e.g., two separate) access lines to control access to a respective memory cell during read and write operations. In comparison with such conventional memory devices (that use multiple access lines for the same memory cell), memory device 200 uses a single access line (e.g., shared access line) in memory device 200 to control both transistors T1 and T2 of a respective memory cell to access the respective memory cell. This technique can save space and simplify operation of memory device 200. Further, some conventional memory devices may use multiple data lines to access a selected memory cell (e.g., during a read operation) to read information from the selected memory cell. In memory device 200, a single data line (e.g., data line 221 or 222) can be used to access a selected memory cell (e.g., during a read operation) to read information from the selected memory cell. This may also simplify the structure, operation, or both of memory device 200 in comparison with conventional memory devices use multiple data lines to access a selected memory cell.
In memory device 200, the gate of each of transistors T1 and T2 can be part of a respective access line (e.g., a respective word line). As shown in
The gate of each of transistors T1 and T2 of memory cell 212 can be part of access line 242. The gate of each of transistors T1 and T2 of memory cells 213 can be part of access line 242. For example, in the structure of memory device 200, four different portions of a conductive material (or materials) that form access line 242 can form the gates (e.g., four gates) of transistors T1 and T2 of memory cell 212 and the gates transistors T1 and T2 of memory cell 213, respectively.
The gate of each of transistors T1 and T2 of memory cell 214 can be part of access line 243. The gate of each of transistors T1 and T2 of memory cell 215 can be part of access line 243. For example, in the structure of memory device 200, four different portions of a conductive material (or materials) that form access line 243 can form the gates (e.g., four gates) of transistors T1 and T2 of memory cell 214 and the gates transistors T1 and T2 of memory cell 215, respectively.
Memory device 200 can include data lines (e.g., bit lines) 221 and 222 that can carry respective signals (e.g., bit line signals) BL1 and BL2. During a read operation, memory device 200 can use data line 221 to obtain information read (e.g., sense) from a selected memory cell of memory cell group 2010, and data line 222 to read information from a selected memory cell of memory cell group 2011. During a write operation, memory device 200 can use data line 221 to provide information to be stored in a selected memory cell of memory cell group 2010, and data line 222 to provide information to be stored in a selected memory cell of memory cell group 2011.
Memory device 200 can include a ground connection (e.g., ground plate) 297 coupled to each of memory cells 210 through 215. Ground connection 297 can be structured from a conductive plate (e.g., a layer of conductive material) that can be coupled to ground terminal of memory device 200. As an example, ground connection 297 can be a common conductive plate (e.g., formed over the memory cells (e.g., memory cells 210 through 215) of memory device 200. In this example, the common conductive plate can be formed over the elements (e.g., transistors T1 and T2) of each of the memory cells (e.g., memory cells 210 through 215) of memory device 200.
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Memory device 200 can include read paths (e.g., circuit paths). Information read from a selected memory cell during a read operation can be obtained through a read path coupled to the selected memory cell. In memory cell group 2010, a read path of a particular memory cell (e.g., memory cell 210, 212, or 214) can include a current path (e.g., read current path) through a channel region of transistor T1 of that particular memory cell, data line 221, and ground connection 297. In memory cell group 2011, a read path of a particular memory cell (e.g., memory cell 211, 213, or 215) can include a current path (e.g., read current path) through a channel region of transistor T1 of that particular memory cell, data line 222, and ground connection 297. In the example where transistor T1 is a PFET (e.g., a PMOS), the current in the read path (e.g., during a read operation) can include a hole conduction (e.g., hole conduction in the direction from data line 221 to ground connection 297 through the channel region of transistor T1). Since transistor T1 can be used in a read path to read information from the respective memory cell during a read operation, transistor T1 can be called a read transistor and the channel region of transistor T1 can be called a read channel region.
Memory device 200 can include write paths (e.g., circuit paths). Information to be stored in a selected memory cell during a write operation can be provided to the selected memory cell through a write path coupled to the selected memory cell. In memory cell group 2010, a write path of a particular memory cell can include transistor T2 (e.g., can include a write current path through a channel region of transistor T2) of that particular memory cell and data line 221. In memory cell group 2011, a write path of a particular memory cell (e.g., memory cell 211, 213, or 215) can include transistor T2 (e.g., can include a write current path through a channel region of transistor T2) of that particular memory cell and data line 222. In the example where transistor T2 is an NFET (e.g., NMOS), the current in a write path (e.g., during a write operation) can include an electron conduction (e.g., electron conduction in the direction from data line 221 to charge storage structure 202 through the channel region of transistor T2. Since transistor T2 can be used in a write path to store information in a respective memory cell during a write operation, transistor T2 can be called a write transistor and the channel region of transistor T1 can be called a write channel region.
Each of transistors T1 and T2 can have a threshold voltage (Vt). Transistor T1 has a threshold voltage Vt1. Transistor T2 has a threshold voltage Vt2. The values of threshold voltages Vt1 and Vt2 can be different (unequal values). For example, the value of threshold voltage Vt2 can be greater than the value of threshold voltage Vt1. The difference in values of threshold voltages Vt1 and Vt2 allows reading (e.g., sensing) of information stored in charge storage structure 202 in transistor T1 on the read path during a read operation without affecting (e.g., without turning on) transistor T2 on the write path (e.g., path through transistor T2). This can prevent leaking of charge (e.g., during a read operation) from charge storage structure 202 through transistor T2 of the write path.
In a structure of memory device 200, transistors T1 and T2 can be formed (e.g., engineered) such that threshold voltage Vt1 of transistor T1 can be less than zero volts (e.g., Vt1<0V) regardless of the value (e.g., “0” or “1”) of information stored in charge storage structure 202 of transistor T1, and Vt1<Vt2. Charge storage structure 202 can be in state “0” when information having a value of “0” is stored in charge storage structure 202. Charge storage structure 202 can be in state “1” when information having a value of “1” is stored in charge storage structure 202. Thus, in this structure, the relationship between the values of threshold voltages Vt1 and Vt2 can be expressed as follows, Vt1 for state “0”<Vt1 for state “1”<0V, and Vt2=0V (or alternatively Vt2>0V).
In an alternative structure of memory device 200, transistors T1 and T2 can be formed (e.g., engineered) such that Vt1 for state “0”<Vt1 for state “1,” where Vt1 for state “0”<0V (or alternatively Vt1 for state “0”=0V), Vt1 for state “1”>0V, and Vt1<Vt2.
In another alternative structure, transistors T1 and T2 can be formed (e.g., engineered) such that Vt1 (for state “0”)<Vt1 (for state “1”), where Vt1 for state “0”=0V (or alternatively Vt1 for state “0”>0V), and Vt1<Vt2.
During a read operation of memory device 200, only one memory cell of the same memory cell group can be selected at a time to read information from the selected memory cell. For example, memory cells 210, 212, and 214 of memory cell group 2010 can be selected one at a time during a read operation to read information from the selected memory cell (e.g., one of memory cells 210, 212, and 214 in this example). In another example, memory cells 211, 213, and 215 of memory cell group 2011 can be selected one at a time during a read operation to read information from the selected memory cell (e.g., one of memory cells 211, 213, and 215 in this example).
During a read operation, memory cells of different memory cell groups (e.g., memory cell groups 2010 and 2011) that share the same access line (e.g., access line 241, 242, or 243) can be concurrently selected (or alternatively can be sequentially selected). For example, memory cells 210 and 211 can be concurrently selected during a read operation to read (e.g., concurrently read) information from memory cells 210 and 211. Memory cells 212 and 213 can be concurrently selected during a read operation to read (e.g., concurrently read) information from memory cells 212 and 213. Memory cells 214 and 215 can be concurrently selected during a read operation to read (e.g., concurrently read) information from memory cells 214 and 215.
The value of information read from the selected memory cell of memory cell group 2010 during a read operation can be determined based on the value of a current detected (e.g. sensed) from a read path (described above) that includes data line 221, transistor T1 of the selected memory cell (e.g., memory cell 210, 212, or 214), and ground connection 297. The value of information read from the selected memory cell of memory cell group 2011 during a read operation can be determined based on the value of a current detected (e.g. sensed) from a read path that includes data line 222, transistor T1 of the selected memory cell (e.g., memory cell 211, 213, or 215), and ground connection 297.
Memory device 200 can include detection circuitry (not shown) that can operate during a read operation to detect (e.g., sense) a current (e.g., current I1, not shown) on a read path that includes data line 221 and detect a current (e.g., current I2, not shown) on a read path that includes data line 222. The value of the detected current can be based on the value of information stored in the selected memory cell. For example, depending on the value of information stored in the selected memory cell of memory cell group 2010, the value of the detected current (e.g., the value of current I1) on data line 221 can be zero or greater than zero. Similarly, depending on the value of information stored in the selected memory cell of memory cell group 2011, the value of the detected current (e.g., the value of current I2) on data line 222 can be zero or greater than zero. Memory device 200 can include circuitry (not shown) to translate the value of a detected current into the value (e.g., “0,” “1,” or a combination of multi-bit values) of information stored in the selected memory cell.
During a write operation of memory device 200, only one memory cell of the same memory cell group can be selected at a time to store information in the selected memory cell. For example, memory cell 210, 212, and 214 of memory cell group 2010 can be selected one at a time during a write operation to store information in the selected memory cell (e.g., one of memory cell 210, 212, and 214 in this example). In another example, memory cells 211, 213, and 215 of memory cell group 2011 can be selected one at a time during a write operation to store information in the selected memory cell (e.g., one of memory cell 211, 213, and 215 in this example).
During a write operation, memory cells of different memory cell groups (e.g., memory cell groups 2010 and 2011) that share the same access line (e.g., access line 241, 242, or 243) can be concurrently selected. For example, memory cells 210 and 211 can be concurrently selected during a write operation to store (e.g., concurrently store) information in memory cells 210 and 211. Memory cells 212 and 213 can be concurrently selected during a write operation to store (e.g., concurrently store) information in memory cells 212 and 213. Memory cells 214 and 215 can be concurrently selected during a write operation to store (e.g., concurrently store) information in memory cells 214 and 215.
Information to be stored in a selected memory cell of memory cell group 2010 during a write operation can be provided through a write path (described above) that includes data line 221 and transistor T2 of the selected memory cell (e.g., memory cell 210, 212, or 214). Information to be stored in a selected memory cell of memory cell group 2011 during a write operation can be provided through a write path (described above) that includes data line 222 and transistor T2 of the selected memory cell (e.g., memory cell 212, 213, or 215). As described above, the value (e.g., binary value) of information stored in a particular memory cell among memory cells 210 through 215 can be based on the amount of charge in charge storage structure 202 of that particular memory cell.
In a write operation, the amount of charge in charge storage structure 202 of a selected memory cell can be changed (to reflect the value of information stored in the selected memory cell) by applying a voltage on a write path that includes transistor T2 of that particular memory cell and the data line (e.g., data line 221 or 222) coupled to that particular memory cell. For example, a voltage having one value (e.g., 0V) can be applied on data line 221 (e.g., provide 0V to signal BL1) if information to be stored in a selected memory cell among memory cells 210, 212, and 214 has one value (e.g., “0”). In another example, a voltage having another value (e.g., a positive voltage) can be applied on data line 221 (e.g., provide a positive voltage to signal BL1) if information to be stored in a selected memory cell among memory cells 210, 212, and 214 has another value (e.g., “1”). Thus, information can be stored (e.g., directly stored) in charge storage structure 202 of a particular memory cell by providing the information to be stored (e.g., in the form of a voltage) on a write path (that includes transistor T2) of that particular memory cell.
In
In the read operation shown in
In the read operation shown in
In
The values of voltages V6 and V7 can be the same or different depending on the value (e.g., “0” or “1”) of information to be stored in memory cells 210 and 211. For example, the values of voltages V6 and V7 can be the same (e.g., V6=V7) if the memory cells 210 and 211 are to store information having the same value. As an example, V6=V7=0V if information to be stored in each memory cell 210 and 211 is “0”, and V6=V7=1V to 3V if information to be stored in each memory cell 210 and 211 is “1”).
In another example, the values of voltages V6 and V7 can be different (e.g., V6≠V7) if the memory cells 210 and 211 are to store information having different values. As an example, V6=0V and V7=1V to 3V if “0” to be stored in memory cell 210 and “1” is to be stored in memory cell 211). As another example, V6=1V to 3V and V7=0V if “1” is to be stored in memory cell 210 and “0” is to be stored in memory cell 211).
The range of voltage of 1V to 3V is used here as an example. A different range of voltages can be used. Further, instead of applying 0V (e.g., V6=0V or V7=0V) to a particular write data line (e.g., data line 221 or 222) for storing information having a value of “0” to the memory cell (e.g., memory cell 210 or 211) coupled to that particular write data line, a positive voltage (e.g., V6>0V or V7>0V) may be applied to that particular data line.
In a write operation of memory device 200 of
In the example write operation of
For simplicity,
The following description refers to
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Access line 241 (associated with signal WL1) can be structured by (can include) a combination of portions 541F and 541B (e.g., front and back conductive portions with respect to the Y-direction). Each of portions 541F and 541B can include a conductive material (or a combination of materials) that can be structured as a conductive line (e.g., conductive region) having a length extending continuously in the X-direction. Thus, portions 541F and 541B can be part of conductive lines that are opposite from each other (e.g., opposite from each other in the Y-direction).
Each of portions 541F and 541B can include a structure (e.g., a piece (e.g., a layer)) of conductive material (e.g., metal, conductively doped polysilicon, or other conductive materials). Each of portions 541F and 541B can have a length (shown in
Portions 541F and 541B can be electrically coupled to each other. For example, memory device 200 can include a conductive material (e.g., not shown) that can contact (e.g., electrically couple to) portions 541F and 541B, such that portions 541F and 541B (which are part of a single access line 241) can be concurrently applied by the same signal (e.g., signal WL1).
In an alternative structure of memory device 200, either portion 541F or portion 541B can be omitted, such that access line 241 can include only either portion 541F or portion 541B. In the structure shown in
Charge storage structure 202 can include a charge storage material (or a combination of materials), which can include a piece (e.g., a layer) of semiconductor material (e.g., polysilicon), a piece (e.g., a layer) of metal, or a piece of material (or materials) that can trap charge. The materials for charge storage structure 202 and portions 541F and 541B of access line 241 can be the same or can be different. As shown in
Memory device 200 can include material 520 located between data line 221 and charge storage structure 202. As shown in
Material 520 can form a source (e.g., source terminal), a drain (e.g., drain terminal), and a channel region (e.g., write channel region) between the source and the drain of transistor T2 of memory cell 210. Thus, as shown in
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Materials 520 and 521 can be the same. For example, each of materials 520 and 521 can include a structure (e.g., a piece (e.g., a layer) of semiconductor material. In the example where transistor T2 is an NFET (as described above), materials 520 and 521 can include n-type semiconductor material (e.g., n-type silicon).
In another example, the semiconductor material that forms material 520 or material 521 can include a piece of oxide material. Examples of the oxide material used for materials 520 and 521 include semiconducting oxide materials, transparent conductive oxide materials, and other oxide materials.
As an example, each of materials 520 and 521 can include at least one of zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnOx), indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium oxide (InOx, In2O3), tin oxide (SnO2), titanium oxide (TiOx), zinc oxide nitride (ZnxOyNz), magnesium zinc oxide (MgxZnyOz), indium zinc oxide (InxZnyOz), indium gallium zinc oxide (InxGayZnzOa), zirconium indium zinc oxide (ZrxInyZnzOa), hafnium indium zinc oxide (HfxInyZnzOa), tin indium zinc oxide (SnxInyZnzOa), aluminum tin indium zinc oxide (AlxSnyInzZnaOd), silicon indium zinc oxide (SixInyZnzOa), zinc tin oxide (ZnxSnyOz), aluminum zinc tin oxide (AlxZnySnzOa), gallium zinc tin oxide (GaxZnySnzOa), zirconium zinc tin oxide (ZrxZnySnzOa), indium gallium silicon oxide (InGaSiO), and gallium phosphide (GaP).
Using the material listed above in memory device 200 provides improvement and benefits for memory device 200. For example, during a read operation, to read information from a selected memory cell (e.g., memory cell 210 or 211), charge from charge storage structure 202 of the selected memory cell may leak to transistor T2 of the selected memory cell. Using the material listed above for the channel region (e.g., material 520 or 521) of transistor T2 can reduce or prevent such a leakage. This improves the accuracy of information read from the selected memory cell and improves the retention of information stored in the memory cells of the memory device (e.g., memory device 200) described herein.
The materials listed above are examples of materials 520 and 521. However, other materials (e.g., a relatively high band-gap material) different from the above-listed materials can be used.
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Memory cell 210 can include portions 510A electrically coupled to portion 580, data line 221, and ground connection 297. Portion 510A can include a structure (e.g., a piece (e.g., a layer)) of semiconductor material. Example materials for portion 510 include silicon, polysilicon (e.g., undoped or doped polysilicon), germanium, silicon-germanium, or other semiconductor materials, and semiconducting oxide materials (oxide semiconductors, e.g., SnO or other oxide semiconductors).
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The spanning (e.g., overlapping) of access line 241 across portion 510A and material 520 allows access line 241 (a single access line) to control (e.g., to turn on or turn off) both transistors T1 and T2 of memory cell 210 and both transistors of memory cell 211. Similarly, the spanning (e.g., overlapping) of access line 241 across portion 511A and material 521 allows access line 241 (a single access line) to control (e.g., turn on or turn off) both transistors T1 and T2 of memory cell 211.
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Dashed line 526D can indicate an imaginary boundary (e.g., boundary between adjacent cells) of each memory cells 210 and 211. As shown in
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The above description focuses on the structure of memory cell 210. Memory cell 211 can include elements structured in ways similar or identical to the elements of memory cell 210, described above. For example, as shown in
As described above with reference to
Substrate 799 can be similar to or identical to substrate 599 of memory device 200 of
Semiconductor material 780 can include the same material as portions 580 and 581 of
Material 702 can include the same material as charge storage structure 202 of memory cell 210 of
Material 720 can include the same material as write channel region (e.g., material 520) of transistor T2 of memory cell 210 of
Each of trenches 801 and 802 can have a length in the Y-direction, a width (shorter than the length) in the X-direction, and a bottom (not labeled) resting on (e.g., bounded by) a respective portion of dielectric material 790. Structures 811, 812, and 813 can include respective side walls (e.g., opposing vertical side walls) 861, 862, 863, and 864, which also form side walls of respective trenches 801 and 802. For example, structure 811 can include a side wall 861, structure 812 can include side walls 862 and 863, and structure 813 can include a side wall 864. Side walls 861 and 862 can form side walls of trench 801. Side walls 863 and 864 can form side walls of trench 802.
Dielectric materials 1431, 1432, and 1433 can be formed at the same time (e.g., formed in the same deposition process). Dielectric materials 1426 and 1426′ can be formed at the same time (e.g., formed in the same deposition process).
Dielectric materials 1431, 1432, and 1433 can be formed at the same time (e.g., formed in the same deposition process) as dielectric materials 1426 and 1426′. Alternatively, dielectric materials 1431, 1432, and 1433 can be formed at a different time (e.g., formed before or after) that dielectric materials 1426 and 1426′ are formed.
Trenches 1661-1664 can be formed by removing (e.g., cut in the X-direction) part of each of the materials at locations 1561-1564, including dielectric material 715, material 702 (under material 715 in
Conductive lines 1701-1706 can form part of access lines (e.g., word lines) to access memory cells 210′, 212′ and 214′ of memory device 700. Memory cells 210′, 212′, and 214′ can correspond to memory cells 210, 212, and 214, respectively, of memory device 200 of
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Similarly, conductive lines 1703 and 1704 can have respective portions (e.g., respective conductive regions) adjacent respective sides (opposite sides) in the Y-direction of a channel region (e.g., read channel region) of memory cell 212′. Conductive lines 1705 and 1706 can have respective portions (e.g., respective conductive regions) adjacent respective sides (opposite sides) in the Y-direction of a channel region (e.g., read channel region) of memory cell 214′. Another view of memory device 700 along line 18-18 is shown in
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Each of portions 1610, 1611, 1610′, and 1611′ can form a channel region (e.g., read channel region) of a transistor T1 of a respective memory cell among memory cells 208′, 209′, 210′, and 211′. Each of portions 1620 can form a channel region (e.g., write channel region) of a transistor T2 of a respective memory cell among memory cells 208′, 209′, 210′, and 211′.
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Similarly, part of each of conductive lines 1701 and 1702 can span across part of a read channel region (e.g., portion 1610′, 1611′, or 1611) and part of a write channel region (e.g., portion 1620 above data line 1319, 1320, or 1322) of each of memory cell 208′, 209′, and 211′.
The processes of forming memory device 700 in
The description of forming memory device 700 with reference to
The process of forming memory device 200 as described above can have a relatively reduced number of masks (e.g., reduced number of critical masks) in comparisons with some conventional processes. For example, by forming trenches 801 and 802 in the process associated with
As shown in
In
Each of portions 1620 can form part of a channel region (e.g., write channel region) of a transistor T2 of a respective memory cell among memory cells 209′, 210′, and 211′. For example, portion 1620 above data line 2021 can form part of a channel region (e.g., write channel region) of a transistor T2 of memory cell 210′.
The combination of portions 1610 and 1611′ (e.g., two semiconductor portions) can form part of a channel region (e.g., read channel region) of transistor T1 of memory cell 210′. Each of memory cells 209′ and 211′ of memory device 200 can also include two semiconductor portions that can form a channel region (e.g., read channel region) of transistor T1 of the memory cell. However, only one of two semiconductor portions of transistor T1 (not labeled) of each of memory cells 209′ and 211′ is shown in
Thus, each of the memory cells of memory device 2000 in
In
The description of forming memory device 2000 with reference to
As shown in
As shown in
Deck 27051 can include memory cells 27101, 27111, 27121, and 27131 (e.g., arranged in a row), memory cells 27201, 27211, 27221, and 27231 (e.g., arranged in a row), and memory cells 27301, 27311, 27321, and 27331 (e.g., arranged in a row).
Deck 27052 can include memory cells 27102, 27112, 27122, and 27132 (e.g., arranged in a row), memory cells 27202, 27212, 27222, and 27232 (e.g., arranged in a row), and memory cells 27302, 27312, 27322, and 27332 (e.g., arranged in a row).
Deck 27053 can include memory cells 27103, 27113, 27123, and 27133 (e.g., arranged in a row), memory cells 27203, 27213, 27223, and 27233 (e.g., arranged in a row), and memory cells 27303, 27313, 27323, and 27333 (e.g., arranged in a row).
As shown in
Decks 27050, 27051, 27052, and 27053 can be formed one deck at a time. For example, decks 27050, 27051, 27052, and 27053 can be formed sequentially in the order of decks 27050, 27051, 27052, and 27053 (e.g., deck 27051 is formed first and deck 27053 is formed last). In this example, the memory cell of one deck (e.g., deck 27051) can be formed either after formation of the memory cells of another deck (e.g., deck 27050) or before formation of the memory cells of another deck (e.g., deck 27052). Alternatively, decks 27050, 27051, 27052, and 27053 can be formed concurrently (e.g., simultaneously), such that the memory cells of decks 27050, 27051, 27052, and 27053 can be concurrently formed. For example, the memory cells in levels 2750, 2751, 2752, and 2753 of memory device 2700 can be concurrently formed.
The structures of the memory cells of each of decks 27050, 27051, 27052, and 27053 can include the structures of the memory cells described above with reference to
Memory device 2700 can include data lines (e.g., bit lines) and access lines (e.g., word lines) to access the memory cells of decks 27050, 27051, 27052, and 27053. For simplicity, data lines and access lines of memory cells are omitted from
The illustrations of apparatuses (e.g., memory devices 100, 200, 700, 2000, and 2700) and methods (e.g., operations of memory devices 100 and 200, and methods of forming memory devices 700 and 2000) are intended to provide a general understanding of the structure of various embodiments and are not intended to provide a complete description of all the elements and features of apparatuses that might make use of the structures described herein. An apparatus herein refers to, for example, either a device (e.g., any of memory devices 100, 200, 700, 2000, and 2700) or a system (e.g., an electronic item that can include any of memory devices 100, 200, 700, 2000, and 2700).
Any of the components described above with reference to
The memory devices (e.g., memory devices 100, 200, 700, 2000, and 2700) described herein may be included in apparatuses (e.g., electronic circuitry) such as high-speed computers, communication and signal processing circuitry, single- or multi-processor modules, single or multiple embedded processors, multicore processors, message information switches, and application-specific modules including multilayer, multichip modules. Such apparatuses may further be included as subcomponents within a variety of other apparatuses (e.g., electronic systems), such as televisions, cellular telephones, personal computers (e.g., laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radios, video players, audio players (e.g., MP3 (Motion Picture Experts Group, Audio Layer 3) players), vehicles, medical devices (e.g., heart monitor, blood pressure monitor, etc.), set top boxes, and others.
The embodiments described above with reference to
In the detailed description and the claims, the term “on” used with respect to two or more elements (e.g., materials), one “on” the other, means at least some contact between the elements (e.g., between the materials). The term “over” means the elements (e.g., materials) are in close proximity, but possibly with one or more additional intervening elements (e.g., materials) such that contact is possible but not required. Neither “on” nor “over” implies any directionality as used herein unless stated as such.
In the detailed description and the claims, a list of items joined by the term “at least one of” can mean any combination of the listed items. For example, if items A and B are listed, then the phrase “at least one of A and B” means A only; B only; or A and B. In another example, if items A, B, and C are listed, then the phrase “at least one of A, B and C” means A only; B only; C only; A and B (excluding C); A and C (excluding B); B and C (excluding A); or all of A, B, and C. Item A can include a single element or multiple elements. Item B can include a single element or multiple elements. Item C can include a single element or multiple elements.
In the detailed description and the claims, a list of items joined by the term “one of” can mean only one of the list items. For example, if items A and B are listed, then the phrase “one of A and B” means A only (excluding B), or B only (excluding A). In another example, if items A, B, and C are listed, then the phrase “one of A, B and C” means A only; B only; or C only. Item A can include a single element or multiple elements. Item B can include a single element or multiple elements. Item C can include a single element or multiple elements.
The above description and the drawings illustrate some embodiments of the inventive subject matter to enable those skilled in the art to practice the embodiments of the inventive subject matter. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Examples merely typify possible variations. Portions and features of some embodiments may be included in, or substituted for, those of others. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description.
Claims
1. An apparatus comprising:
- a substrate;
- a conductive plate located over the substrate to couple a ground connection;
- a data line located between the substrate and the conductive plate;
- a memory cell including: a first transistor including a first region electrically coupled between the data line and the conductive plate, and a charge storage structure electrically separated from the first region; and a second transistor including a second region electrically coupled to the charge storage structure and the data line; and
- a conductive line electrically separated from the first and second regions, part of the conductive line spanning across part of the first region of the first transistor and forming a gate of the first and second transistors.
2. The apparatus of claim 1, wherein the first region includes p-type semiconductor material, and the second region includes n-type semiconductor material.
3. The apparatus of claim 1, wherein the second region comprises a semiconducting oxide material.
4. The apparatus of claim 1, further comprising:
- an additional data line located between the substrate and the conductive plate; and
- an additional memory cell, the additional memory cell including: a first additional transistor including a first additional region electrically coupled to the additional data line and the conductive plate, and an additional charge storage structure electrically separated from the first additional region; and a second additional transistor including a second additional region electrically coupled to the additional charge storage structure and the additional data line; wherein the conductive line is electrically separated from the first and second additional regions, and an additional part of the conductive line spans across part of the first additional region of the first additional transistor and part of the second additional region of the second additional transistor.
5. The apparatus of claim 1, wherein the first and second transistors have different threshold voltages.
6. The apparatus of claim 1, wherein the first transistor has a first threshold voltage less than zero when the charge storage structure is in a first state, and the first transistor has a second threshold voltage less than zero when the charge storage structure is in a second state, and the first and second states represent different values of information stored in the memory cell.
7. The apparatus of claim 1, further comprising an additional memory cell, wherein the memory cell is included in a first deck of memory cells of the apparatus, the additional memory cell is included in a second deck of additional memory cells of the apparatus, and the first deck of memory cells and the second deck of memory cells are located in different levels of the apparatus.
8. An apparatus comprising:
- a first conductive region located in a first level of the apparatus;
- a second conductive region located in the first level of the apparatus and electrically separated from the first conductive region;
- a conductive plate located in a second level of the apparatus;
- a first memory cell including a first charge storage structure, a first region to conduct a current between the first conductive region and the conductive plate during a first operation of the apparatus, and a second region to conduct a current between the first conductive region and the first charge storage structure during a second operation of the apparatus;
- a second memory cell including a second charge storage structure, a first additional region to conduct a current between the second conductive region and the conductive plate during a third operation of the apparatus, and a second additional region to conduct a current between the second conductive region and the second charge storage structure during a fourth operation of the apparatus;
- a dielectric between the first and second memory cells, the dielectric including a first side contacting the first region, and a second side contacting the first additional region; and
- a conductive line electrically separated from the first and second regions and the first and second additional regions, and part of the conductive line spanning across part of the first and second regions and part of the first and second additional regions.
9. The apparatus of claim 8, further comprising a substrate, wherein the first and second conductive regions are between the conductive plate and the substrate.
10. The apparatus of claim 9, wherein the conductive plate includes a ground plate.
11. The apparatus of claim 8, wherein the first and second regions include materials of different conductivity types, and first and second additional regions include materials of different conductivity types.
12. The apparatus of claim 8, wherein:
- the first conductive region is part of a first data line of the apparatus;
- the second conductive region is part of a second data line of the apparatus; and
- the conductive line is part of a word line of the apparatus.
13. The apparatus of claim 8, further comprising an additional conductive line opposite from the conductive line, wherein:
- an additional conductive line is electrically separated from the first and second regions and the first and second additional regions, and part of the additional conductive line spans across part of the first and second regions and part of the first and second additional regions.
14. The apparatus of claim 13, wherein the additional conductive line is electrically coupled to the conductive line.
15. The apparatus of claim 8, wherein each of the second region and the second additional region comprises at least one of zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnOx), indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium oxide (InOx, In2O3), tin oxide (SnO2), titanium oxide (TiOx), zinc oxide nitride (ZnxOyNz), magnesium zinc oxide (MgxZnyOz), indium zinc oxide (InxZnyOz), indium gallium zinc oxide (InxGayZnzOa), zirconium indium zinc oxide (ZrxInyZnzOa), hafnium indium zinc oxide (HfxInyZnzOa), tin indium zinc oxide (SnxInyZnzOa), aluminum tin indium zinc oxide (AlxSnyInzZnaOd), silicon indium zinc oxide (SixInyZnzOa), zinc tin oxide (ZnxSnyOa), aluminum zinc tin oxide (AlxZnySnzOa), gallium zinc tin oxide (GaxZnySnzOa), zirconium zinc tin oxide (ZrxZnySnzOa), indium gallium silicon oxide (InGaSiO), and gallium phosphide (GaP).
16. A method comprising:
- forming data lines over a substrate;
- forming memory cells over the substrate, such that each of the memory cells includes a first transistor and a second transistor, the first transistor includes a charge storage structure located over a data line of the data lines, and a first channel region contacting the data line, the second transistor includes a second channel region electrically separated from the first channel region and formed over and contacting the charge storage structure and the data line;
- forming conductive lines such that each of the conductive lines is electrically separated from the first and second channel region of a respective memory cell of the memory cells, and such that part of each of the conductive lines spans across part of each of the first and second channel regions of a respective memory cell of the memory cells; and
- forming a ground plate over the conductive lines and contacting the first channel region of the first transistor of each of the memory cells.
17. The method of claim 16, wherein forming the memory cells includes:
- forming levels of materials over the substrate;
- forming trenches in the levels of materials, such that each of the trenches includes a length in a first direction, a side wall formed by a portion of a remaining part of each of the levels of materials, and the side wall includes a side wall portion formed by a portion of a respective data line among the data lines; and
- forming the first channel region of each of the memory cell of the memory cells in a respective trench of the first trenches, such that the first channel region contacts the side wall portion of the side wall a respective trench of the trenches.
18. The method of claim 17, wherein forming the conductive lines includes:
- forming additional trenches in the remaining part of each of the levels of materials, such that each of the additional trenches includes a length in a second direction; and
- forming the conductive lines in the additional trenches, such that each of the conductive lines is formed in a respective trench of the additional trenches.
19. The method of claim 17, wherein forming the levels of materials over the substrate includes:
- forming a first semiconductor material;
- forming a conductive material over the first semiconductor material;
- forming a second semiconductor material over the conductive material; and
- forming a charge storage material over the additional semiconductor material.
20. The method of 19, wherein forming the data lines includes:
- removing a portion of the conductive material at locations of the trenches when the trenches are formed to form the data lines from a remaining portion of the conductive material.
21. The method of 19, wherein forming the memory cells includes:
- removing a portion of the second semiconductor material at locations of the trenches when the trenches are formed to form the second channel region of each of the memory cells from a remaining portion of the second semiconductor material; and
- removing a portion of the charge storage material at locations of the trenches when the trenches are formed to form the charge storage structure of each of the memory cells from a remaining portion of the charge storage material.
22. The method of claim 19, wherein the second semiconductor material comprises a semiconducting oxide material.
23. A method comprising:
- forming levels of materials over a substrate;
- forming first trenches in the levels of materials by removing part of the levels of materials, such that each of the first trenches includes a length in a first direction, a first side wall formed by a first portion of a remaining part of each of the levels of materials, and a second side wall formed by a second portion of the remaining part of each of the levels of materials;
- forming a first dielectric on a first portion of the first side wall of each of the first trenches;
- forming a first additional dielectric on a first portion of the second side wall of each of the first trenches;
- forming a first semiconductor material adjacent the first dielectric and contacting a second portion of the first side wall of each of the first trenches;
- forming a first additional semiconductor material adjacent the first additional dielectric and contacting a second portion of the second side wall of each of the first trenches;
- forming a second dielectric between the first semiconductor material and the first additional semiconductor material in each of the first trenches; and
- forming second trenches in a second direction by removing a portion of the remaining part of each of the levels of materials, a portion of each of the first dielectric, a portion of the first additional dielectric, a portion of the second dielectric, a portion of the semiconductor material, and a portion of the additional material to form memory cells, such that a first memory cell of the memory cells includes at least part of a remaining portion of the semiconductor material, and a second memory cell of the memory cells includes at least part of a remaining portion of the additional semiconductor material.
24. The method of claim 23, wherein forming the levels of materials over the substrate includes:
- forming a semiconductor material;
- forming a conductive material over the semiconductor material;
- forming an additional semiconductor material over the conductive material; and
- forming a charge storage material over the additional semiconductor material.
25. The method of claim 24, wherein the semiconductor material has a p-type conductivity.
26. The method of claim 24, wherein the additional semiconductor material comprises a semiconducting oxide material.
27. The method of claim 24, wherein the additional semiconductor material comprises at least one of zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnOx), indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium oxide (InOx, In2O3), tin oxide (SnO2), titanium oxide (TiOx), zinc oxide nitride (ZnxOyNz), magnesium zinc oxide (MgxZnyOz), indium zinc oxide (InxZnyOz), indium gallium zinc oxide (InxGayZnzOa), zirconium indium zinc oxide (ZrxInyZnzOa), hafnium indium zinc oxide (HfxInyZnzOa), tin indium zinc oxide (SnxInyZnzOa), aluminum tin indium zinc oxide (AlxSnyInzZnaOd), silicon indium zinc oxide (SixInyZnzOa), zinc tin oxide (ZnxSnyOz), aluminum zinc tin oxide (AlxZnySnzOa), gallium zinc tin oxide (GaxZnySnzOa), zirconium zinc tin oxide (ZrxZnySnzOa), indium gallium silicon oxide (InGaSiO), and gallium phosphide (GaP).
28. The method of claim 24, wherein the second portion of the first side wall is formed from a first portion of the conductive material, and the second portion of the second side wall is formed from a second portion of the conductive material.
29. The method of claim 24, wherein:
- the first memory cell includes a charge storage structure formed from one of the levels of materials adjacent the first portion of the first side wall of a trench of the first trenches; and
- the second memory cell includes a charge storage structure formed from one of the levels of materials adjacent the first portion of the second side wall of the trench of the first trenches.
30. The method of claim 24, further comprising:
- forming a conductive plate contacting the remaining part of the semiconductor material and the remaining part of the additional semiconductor.
31. The method of claim 24, further comprising:
- forming a conductive line in each of the second trenches, such that the conductive line has a length in the second direction, and the conductive line is electrically separated from the memory cells.
32. The method of claim 24, further comprising:
- forming an additional conductive line in each of the second trenches, such that the additional conductive line has a length in the second direction, and the additional conductive line is electrically separated from the memory cells.
Type: Application
Filed: Aug 26, 2020
Publication Date: Mar 4, 2021
Patent Grant number: 11665880
Inventors: Kamal M. Karda (Boise, ID), Karthik Sarpatwari (Boise, ID), Haitao Liu (Boise, ID), Durai Vishak Nirmal Ramaswamy (Boise, ID)
Application Number: 17/003,037