3D Integrated Circuit and Methods of Forming the Same
An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.
This application is a divisional of U.S. patent application Ser. No. 17/034,526, filed Sep. 28, 2020, and entitled “3D Circuit and Methods of Forming the Same,” which application is a continuation of U.S. patent application Ser. No. 16/149,972, filed Oct. 2, 2018, and entitled “3D Circuit and Methods of Forming the Same,” now U.S. Pat. No. 10,790,189 issued on Sep. 29, 2020, which is a continuation of U.S. patent application Ser. No. 15/018,422, filed Feb. 8, 2016, and entitled “3D Circuit and Methods of Forming the Same,” now U.S. Pat. No. 10,090,196 issued on Oct. 2, 2018, which is a divisional of U.S. patent application Ser. No. 14/056,345, filed Oct. 17, 2013, and entitled “3D Integrated Circuit and Methods of Forming the Same,” now U.S. Pat. No. 9,257,399 issued Feb. 9, 2016, which applications are incorporated herein by reference.
BACKGROUNDIn wafer-to-wafer bonding technology, various methods have been developed to bond two package components (such as wafers) together. The available bonding methods include fusion bonding, eutectic bonding, direct metal bonding, hybrid bonding, and the like. In the fusion bonding, an oxide surface of a wafer is bonded to an oxide surface or a silicon surface of another wafer. In the eutectic bonding, two eutectic materials are placed together, and are applied with a specific pressure and temperature. In various conditions, the eutectic materials are melted. When the melted eutectic materials are solidified, the wafers are bonded together. In the direct metal-to-metal bonding, two metal pads are pressed against each other at an elevated temperature, and the inter-diffusion of the metal pads causes the bonding of the metal pads. In the hybrid bonding, the metal pads of two wafers are bonded to each other through direct metal-to-metal bonding, and an oxide surface of one of the two wafers is bonded to an oxide surface or a silicon surface of the other wafer.
The previously developed bonding methods have their disadvantages. For example, regarding the fusion bonding, extra electrical connections are needed to interconnect he bonded wafers. Accuracy of the eutectic bonding is low, and there may be metal-squeeze due to the melting of the bonding metals. Throughput of the direct metal-to-metal bonding is also low. In the hybrid bonding, the metal pads have higher Coefficients of Thermal Expansion (CTEs) than the dielectric layers at the surfaces of the bonded wafers. This results in problems in bonding the dielectric layers. For example, the bonds between the metal pads may delaminate if the expanded volume of the metal pads is smaller than the dishing volume of the metal pads. Conversely, if the expanded volume of the metal pads is significantly greater than the dishing volume, the bonds between the dielectric layers may delaminate.
For a more complete understanding of the embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
The making and using of various embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are illustrative, and do not limit the scope of the disclosure.
A package including hybrid bonding and methods of forming the same are provided in accordance with various exemplary embodiments. Intermediate stages of forming the package are illustrated. Variations of the embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.
In alternative embodiments, package component 100 is an interposer wafer, which is free from active devices therein. Package component 100 may, or may not, include passive devices (not shown) such as resistors, capacitors, inductors, transformers, and the like in accordance with some embodiments.
In yet alternative embodiments, package component 100 is a package substrate. In some embodiments, package component 100 is a laminate package substrate, wherein conductive traces 106 are embedded in laminate dielectric layers 108 as schematically illustrated. In alternative embodiments, package components 100 are built-up package substrates, which comprise cores (not shown), and conductive traces (represented by traces 106) built on opposite sides of the cores. The core of a built-up package substrate includes a fiber layer (not shown) and metallic features (not shown) penetrating through the fiber layer, with the conductive traces interconnected through the metallic features. The conductive traces 106 are interconnected through conductive features in the cores.
In various embodiments wherein package component 100 is a device wafer, an interposer wafer, a package substrate, or the like, dielectric layer 110 is formed, which may be a top IMD layer. In some embodiments, dielectric layer 110 is a low-k dielectric layer having k value lower than about 3.0, lower than about 2.5, or lower than about 2.0. In alternative embodiments, dielectric layer 110 comprises silicon oxide, silicon oxynitride, silicon nitride, or the like. Metal features 112 are formed in dielectric layer 110, and may be electrically coupled to active devices 104 through metal lines and vias 106. Metal features 112 may be metal lines or metal pads. Metal features 112 may also be formed of copper, aluminum, nickel, tungsten, alloys of the above-mentioned metals, or other appropriate materials. The top surface of dielectric layer 110 and the top surfaces of metal features 112 may be substantially level with each other. In the embodiments wherein package component 100 is a device wafer, dielectric layer 110 and metal features 112 may be on the front side (the side with active devices 104) or the backside (the side underlying substrate 102) of substrate 102. For example,
Each or some of metal lines and vias 106 and metal features 112 may include a copper-containing region (not shown) and a conductive barrier layer separating the copper-containing region from the respective dielectric. The conductive barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like.
Referring to
Porous dielectric layer 118 may also be a low-k dielectric having a k value lower than 3.8, or lower than about 3.0. The low-k dielectric materials having k values lower than 3.8 are low-k dielectric materials. The k value of dielectric layer 118 may also be between about 2.5 and 3.0. Furthermore, the porosity of porous dielectric layer 118 is higher than the porosity of non-porous dielectric layer 116. For example, the porosity of porous dielectric layer 118 may be higher than about 5 percent and about 40 percent. When the porosity of porous dielectric layer 118 reaches about 5 percent, porous dielectric layer 118 starts to cause releasing the stress generated due to the subsequent bonding of package components 100 and 200 (
Dielectric barrier layer 120 comprises a dielectric material, which may be, for example, a silicon-based dielectric such as silicon nitride, silicon oxynitride, or the like. Dielectric barrier layer 120 has the function of bonding to another die/wafer through fusion bonding, and may also block copper from diffusing through.
Referring to
Next, conductive barrier layer 126 and metallic material 128 are filled into openings 122, resulting in a structure shown in
A Planarization such as a Chemical Mechanical Polish (CMP) is then performed. Dielectric barrier layer 120 may be used as a CMP stop layer. As a result, the top surface of the remaining metallic material 128 is coplanar with the top surface of dielectric barrier layer 120. The resulting structure is shown in
In some embodiments, dielectric barrier layer 120 comprises a siloxane-based polymer. For example, the siloxane-based polymer may be the SINR™ provided by Shin-Etsu Chemical Co., LTD. Thickness T1 of dielectric barrier layer 120 may be smaller than about 1 μm, so that in the subsequent bonding process, the expanded metallic material 128 (when heated, for example) may protrude out of the top surface of dielectric barrier layer 120, and contact the metal pad in another wafer/die.
Package component 200 may also be selected from a device wafer, an interposer wafer, a package substrate, and the like. In the illustrated
In some embodiments, package component 200 may also include etch stop layer 214, non-porous dielectric layer 216, porous dielectric layer 218, dielectric barrier layer 220, and bond pads 230. Bond pads 230 may further include conductive barrier layer 226 and copper-containing metallic material 228 over dielectric barrier layer 216.
In alternative embodiments, package component 200 may not include porous dielectric layer 218. Rather, conductive barrier layer 226 may be formed directly over and contacting non-porous dielectric layer 216, which may comprise USG, silicon oxide, or the like. In these embodiments, the stress applied to the bonded bond pads 130/230 (
Next, as shown in
In the embodiments wherein dielectric barrier layers 120 and 220 are formed of organic materials such as SINR, pre-bonding may be performed at an elevated temperature in the range between about 140° C. and about 160° C. The pre-bonding may last, for example, for a period of time in the range between about 1 minute and about 5 minutes. Furthermore, after the pre-bonding, a curing process may be performed to drive solvents in dielectric barrier layers 120 and 220 out of the respective package components 100 and 200. In some exemplary embodiments, the curing is performed at a temperature in the range between about 170° C. and about 190° C. The curing may last, for example, for a period of time in the range between about 60 minutes and about 120 minutes. In the embodiments wherein dielectric barrier layers 120 and 220 are formed of inorganic materials, the curing step may be skipped.
After the pre-bonding, dielectric barrier layers 120 and 220 are bonded to each other. The bonding strength, however, are improved in a subsequent annealing step, in some embodiments. The bonded package components 100 and 200 may be annealed at a temperature between about 300° C. and about 400° C., for example. The annealing may be performed for a period of time between about 1 hour and 2 hours. When temperature rises, the hydroxide (OH) bonds (if any) in surface dielectric layers 110 and 210 break to form strong Si—O—Si bonds, and hence package components 100 and 200 are bonded to each other through fusion bonds (and through Van Der Waals force). In addition, during the annealing, the metal, such as copper, in bond pads 130 and 230 inter-diffuse to each other, so that metal-to-metal bonds are also formed. In various embodiments, the resulting bonds between package components 100 and 200 are called hybrid bonds, which include both the metal-to-metal bonds and Si—O—Si bonds and are different from the metal-to-metal bonds only or Si—O—Si bonds only. After the bonding, the bonded package components 100 and 200 are sawed into a plurality of packages 300. Each of the packages includes die 100′ and die 200′, which are the separated portions of package components 100 and 200, respectively.
In the bonding process, temperature is increased above room temperature (for example, about 21° C.), and bond pads 130 and 230 expand. The Coefficient of Thermal Expansion (CTE) of bond pads 130 and 230 is higher than that of dielectric materials such as 114/214, 116/216, 118/218, and 120/210. Therefore, a stress may be applied to pull dielectric barrier layers 120 and 220 apart from each other. After the elevated temperature of the bonding process, package components 100 and 200 are cooled. During the cooling stage of the bonding process, on the other hand, bond pads 130 and 230 shrink, which causes stresses to be generated. The stresses are applied on the bond pads and dielectric materials. These stresses may cause the delamination of bond pads and dielectric layers. In various embodiments of the present disclosure, the porous dielectric layers have the function of absorbing the stress, and hence the delamination of metal pads and dielectric layers is reduced.
In the bonded structure as shown in
In accordance with some embodiments, an integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.
In accordance with other embodiments, an integrated circuit structure includes a first die and a second die. The first die includes a top IMD including a low-k dielectric material, a top metal feature in the top IMD, an etch stop layer overlying the top metal feature and the top IMD, a non-porous dielectric layer over and contacting the etch stop layer, and a porous dielectric layer over and contacting the porous dielectric layer. The first die further includes a first dielectric barrier layer over the porous dielectric layer, and a first bond pad extends from a top surface of the first dielectric barrier layer to the top metal feature. The second die includes a second bond pad bonded to the first bond pad, and a second dielectric barrier layer bonded to the first dielectric barrier layer.
In accordance with yet other embodiments, a method includes forming a first die, which includes forming a non-porous dielectric layer over a top metal feature, forming a porous dielectric layer over and contacting the porous dielectric layer, forming a first dielectric barrier layer over the porous dielectric layer, and etching the non-porous dielectric layer and the porous dielectric layer to form an opening, wherein the top metal feature is exposed through the opening. The formation of the first die further includes filling the opening with a metallic material to form a first bond pad in the opening. The first die is then bonded to a second die, wherein the first bond pad is bonded to a second bond pad in the second die, and wherein the first dielectric barrier layer is bonded to a second dielectric barrier layer in the second die.
Although various embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure.
Claims
1. A three-dimensional bonded semiconductor structure comprising:
- a first semiconductor structure including a first wafer, a first interconnect structure, and a first bonding oxide layer containing first nitride-oxide regions and at least one first metallic bonding structure embedded therein; and
- a second semiconductor structure including a second wafer, a second interconnect structure, and a second bonding oxide layer containing second nitride-oxide regions and at least one second metallic bonding structure embedded therein, wherein a bonding interface is present between said first and second nitride-oxide regions and another bonding interface is present between said at least one first and second metallic bonding structures.
2. The three-dimensional bonded semiconductor structure of claim 1, wherein each of said first and second interconnect structures comprises at least one interconnect dielectric material and one or more interconnect metallic structures embedded therein.
3. The three-dimensional bonded semiconductor structure of claim 2, wherein said at least one or more interconnect metallic structures are composed of copper.
4. The three-dimensional bonded semiconductor structure of claim 2, wherein said one or more interconnect metallic structures include a same metal or metal alloy as said at least one first and second metallic bonding structures.
5. The three-dimensional bonded semiconductor structure of claim 4, wherein said same metal or metal alloy comprises copper.
6. The three-dimensional bonded semiconductor structure of claim 1, wherein at least one said first and second metallic bonding structures are composed of copper.
7. The three-dimensional bonded semiconductor structure of claim 1, wherein said at least one first metallic bonding structure extends entirely through said first bonding oxide layer and contacts at least a portion of an interconnect metallic structure of said first interconnect structure, and said at least one second metallic bonding structure extends entirely through said second bonding oxide layer and contacts at least a portion of an interconnect metallic structure of said second interconnect structure.
8. The three-dimensional bonded semiconductor structure of claim 1, wherein the first bonding oxide layer comprises:
- a first oxide layer with a first porosity; and
- a second oxide layer with a second porosity different from the first porosity.
9. A three-dimensional bonded semiconductor structure comprising:
- a first semiconductor substrate;
- a first oxide layer over the first semiconductor substrate;
- a first nitrogen-oxygen layer along a top surface of the first oxide layer;
- a first metallic bonding structure embedded within both the first nitrogen-oxygen layer and the first oxide layer;
- a second nitrogen-oxygen layer bonded to the first nitrogen-oxygen layer;
- a second oxide layer along a surface of the second nitrogen-oxygen layer;
- a second metallic bonding structure embedded within both the second nitrogen-oxygen layer and the second oxide layer; and
- a second semiconductor substrate over the second oxide layer.
10. The three-dimensional bonded semiconductor structure of claim 9, further comprising a first interconnect structure located between the first semiconductor substrate and the first oxide layer.
11. The three-dimensional bonded semiconductor structure of claim 10, wherein the first interconnect structure comprises at least one interconnect conductive structure, the at least one interconnect conductive structure composed of copper.
12. The three-dimensional bonded semiconductor structure of claim 8, wherein the first interconnect structure comprises at least one interconnect conductive structure, wherein said one or more interconnect conductive structure includes a same metal or metal alloy as said first metallic bonding structure.
13. The three-dimensional bonded semiconductor structure of claim 12, wherein the same metal or metal alloy comprises copper.
14. The three-dimensional bonded semiconductor structure of claim 8, wherein the first nitrogen-oxygen layer comprises silicon oxynitride.
15. A three-dimensional bonded semiconductor structure comprising:
- first layer bonded to a second layer along an interface, wherein each of the first layer and the second layer comprises nitrogen and oxygen;
- a first oxide layer on an opposite side of the first layer from the interface;
- a second oxide layer on an opposite side of second layer from the interface;
- a first metallization layer on an opposite side of the first oxide layer from the interface;
- a second metallization layer on an opposite side of the second oxide layer from the interface;
- a first semiconductor substrate on an opposite side of the first metallization layer from the interface;
- a second semiconductor substrate on an opposite side of the second metallization layer from the interface;
- a first conductive structure extending through the first layer and the first oxide layer; and
- a second conductive structure extending through the second layer and the second oxide layer, the second conductive structure being bonded to the first conductive structure.
16. The three-dimensional bonded semiconductor structure of claim 15, wherein the first metallization layer comprises at least one interconnect conductive structure, the at least one interconnect conductive structure composed of copper.
17. The three-dimensional bonded semiconductor structure of claim 15, wherein the first layer comprises silicon oxynitride.
18. The three-dimensional bonded semiconductor structure of claim 17, wherein the second layer comprises silicon oxynitride.
19. The three-dimensional bonded semiconductor structure of claim 15, wherein the first oxide layer comprises a first oxide sub-layer with a first porosity and a second oxide sub-layer with a second porosity different from the first porosity.
20. The three-dimensional bonded semiconductor structure of claim 19, wherein the second oxide layer comprises a third oxide sub-layer with the first porosity and a fourth oxide sub-layer with the second porosity.
Type: Application
Filed: Jan 4, 2021
Publication Date: May 20, 2021
Inventors: Hsun-Chung Kuang (Hsinchu), Yen-Chang Chu (Tainan City), Cheng-Tai Hsiao (Tainan City), Ping-Yin Liu (Yonghe City), Lan-Lin Chao (Sindian City), Yeur-Luen Tu (Taichung), Chia-Shiung Tsai (Hsinchu), Xiaomeng Chen (Baoshan Township)
Application Number: 17/140,794