SEMICONDUCTOR DEVICE HAVING BODY CONTACT REGIONS AND CORRESPONDING METHODS OF MANUFACTURE
A semiconductor device includes a contact opening extending through a source region and a body region of the device. An electrically insulative spacer lines sidewalls of the semiconductor substrate formed by the contact opening, and is recessed along the sidewalls such that at least part of the source region or body region is uncovered by the electrically insulative spacer. A body contact plug is in the contact opening. A first body contact region formed adjacent a bottom of the contact opening adjoins the body contact plug at the bottom of the contact opening. A second body contact region formed in the part of the source region or body region uncovered by the electrically insulative spacer adjoins the body contact plug along the part of the source region or body region uncovered by the electrically insulative spacer.
The channel dimensions of power MOSFETs are routinely reduced to increase performance. The distance between the channel and the groove contact to the body region of the device also becomes smaller, resulting in several crucial trade-offs including: the interaction of the p+ contact implant into the groove with channel dopants; and the slope of the threshold voltage characteristic decreases as parasitic source capacitance increases and gate control is reduced by depletion capacitance.
The distance between the channel and the groove contact can be kept large enough, but this results in higher Rdson (on-state resistance). The decrease in the slope of the threshold voltage characteristic can be addressed by using thinner oxide which yields smaller gate capacitance. However, smaller gate capacitance increases gate total charge Figure of Merit (FOMg).
Hence, new power MOSFETs with smaller channel dimensions and acceptable FOMg are needed.
SUMMARYAccording to an embodiment of a semiconductor device, the semiconductor device comprises: a trench extending into a first main surface of a semiconductor substrate; a gate electrode and a gate dielectric in the trench, the gate dielectric separating the gate electrode from the semiconductor substrate; a first region having a first conductivity type formed in the semiconductor substrate at the first surface and adjacent the trench; a second region having a second conductivity type formed in the semiconductor substrate below the first region and adjacent the trench; a third region having the first conductivity type formed in the semiconductor substrate below the second region and adjacent the trench; a contact opening in the semiconductor substrate which extends into the second region; an electrically insulative spacer on sidewalls of the semiconductor substrate formed by the contact opening; and an electrically conductive material in the contact opening and adjoining the electrically insulative spacer on the sidewalls of the semiconductor substrate formed by the contact opening. Corresponding methods of manufacture are also provided.
Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.
The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. The features of the various illustrated embodiments can be combined unless they exclude each other. Embodiments are depicted in the drawings and are detailed in the description which follows.
The embodiments described herein provide power MOSFETs with reduced channel dimensions and good FOMg, and corresponding methods of manufacture. By introducing a spacer dielectric along sidewalls of the contact to the highly-doped body contact region of a power device, the lateral dimension of the channel region can be further reduced while also reducing source capacitance and increasing the distance between the highly-doped body contact region and the channel region. The small fin-like portion of the device body region between the contact opening/groove in the semiconductor substrate and the gate trench is in parallel with the contact opening/groove, reducing the swing of the IV curve and DIBL (drain-induced barrier lowering). The highly-doped body contact region is decoupled from the channel region by the spacer dielectric along the contact opening/groove, improving threshold voltage stability. The dielectric spacer also introduces stress along the channel side, which should reduce Rdson and leakage.
A first (source/emitter) region 116 having a first conductivity type (e.g. n-type in the case of an n-channel device, or p-type in the case of a p-channel device) is formed in the semiconductor substrate 102 at the front surface 106 and adjacent each gate trench 104. A second (body) region 118 having a second conductivity type (e.g. p-type in the case of an n-channel device, or n-type in the case of a p-channel device) is formed in the semiconductor substrate 102 below the source/emitter region 116 and adjacent each gate trench 104. A third (drift) region 120 having the first conductivity type is formed in the semiconductor substrate 102, e.g. as part of an epitaxial layer, below the body region 118 and adjacent each gate trench 104. A drain/collector region 122 of the first conductivity type is formed at the back surface 124 of the semiconductor substrate 102 opposite the front surface 106, and is doped more heavily than the drift region 120.
The semiconductor device 100 shown in
An interlayer dielectric 128 such a silicon dioxide, silicon nitride, tetraethoxysilane (TEOS), etc. is formed on the front surface 106 of the semiconductor substrate 102 to separate one or more overlying metal layers (not shown) from the underlying semiconductor substrate 102. A contact opening 130 extends through the interlayer dielectric 128 and into the semiconductor substrate 102. In one embodiment, the minimum width (w1) of the contact opening 130 is larger in the interlayer dielectric 128 than the minimum width (w2) of the contact opening 130 in the semiconductor substrate 102. The width of the drift region 120 between adjacent gate trenches 104 is labelled w3 in
The contact opening 130 extends at least into the body region 118. In the embodiment illustrated in
An electrically insulative spacer 138 is disposed on sidewalls 140 of the semiconductor substrate 102 formed by the contact opening 130. The electrically conductive material 132 in the contact opening 130 adjoins the electrically insulative spacer 138 on the sidewalls 140 of the semiconductor substrate 102 formed by the contact opening 130. By providing the electrically insulative spacer 138 along the sidewalls 140 of the semiconductor substrate 102 formed by the contact opening 130, the lateral dimension of the channel regions 126 can be reduced while also reducing source capacitance and increasing the distance between the body contact plug 134 and the channel regions 126. As a result, the body contact plug 134 is better decoupled from the channel regions 126 by the electrically insulative spacer 138 disposed on the sidewalls 140 of the semiconductor substrate 102 formed by the contact opening 130. Any suitable electrically insulating material can be used for the electrically insulative spacer 140, such as oxide, nitride, carbon, TEOS, etc.
According to the embodiment shown in
In some embodiments, the source/collector region 116 has a depth in a range between 10 nm to 50 nm, the body region 118 has a depth in a range between 100 nm and 200 nm, the interlayer dielectric 128 has a thickness in a range between 50 nm and 300 nm, the contact opening 130 in the interlayer dielectric 128 has a minimum width w1 in a range between 200 nm and 220 nm, the contact (groove) opening 130 in the semiconductor body 100 has a minimum width w2 in a range between 100 nm and 140 nm, the length of the channel regions 126 in the vertical direction is in a range between 50 nm and 200 nm, and/or the lateral channel length is less than 250 nm. Other depth, thickness, width and length ranges are contemplated.
Further according to the embodiment illustrated in
The semiconductor devices 700, 800, 900, 1000 illustrated in
The superjunction charge-balance structure formed by the p-type and n-type pillars/columns/stripes 1124, 1136 results in reduced on-resistance while maintaining required breakdown voltage. By providing dielectric spacers 1151 in the body contact openings to separate the channel regions 1174 from the underlying p-type pillars/columns/stripes 1124, the width needed for the p-type pillars/columns/stripes 1124 can be reduced which in turn decreases the energy levels needed to implant the p-type pillars/columns/stripes 1124 which are used to form a superjunction structure and achieve charge balance. With a deep body contact opening and the contact trench with underlying p-type pillars/columns/stripes, the required voltage can be sustained while also relocating the impact ionization location to the vicinity of the p-type pillars/columns/stripes. Such a construction causes a greater portion of avalanche current to go directly through the p-type pillars/columns/stripes and disperse to the source metal, and by doing so, effectively avoids high current density surrounding the source/emitter region and subsequent turn on the parasitic BJT which could otherwise destroy the device. The depth of the gate trenches 1138 can be varied to adjust gate charge and gate resistance.
The Schottky barrier diode 1202 has low leakage, low forward voltage and when merged with a power MOSFET, low reverse recovery charge Qrr. Gate trenches 104 with underlying superjunction structures formed by pillar/column/stripe region 702 of the second conductivity type and the drift region 120 of the first conductivity type flank both the gate regions and the diode mesas. The superjunction structures underneath the body contacts 136 at the bottom of the contact openings/grooves 130 reduce leakage when the device 1200 is off at both the Schottky barrier and at the body diode of the transistor. The conductivity types of the device regions can be reversed in
Spatially relative terms such as “under”, “below”, “lower”, “over”, “upper” and the like, are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to different orientations than those depicted in the figures. Further, terms such as “first”, “second”, and the like, are also used to describe various elements, regions, sections, etc. and are also not intended to be limiting. Like terms refer to like elements throughout the description.
As used herein, the terms “having”, “containing”, “including”, “comprising” and the like are open-ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles “a”, “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.
With the above range of variations and applications in mind, it should be understood that the present invention is not limited by the foregoing description, nor is it limited by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.
Claims
1. A semiconductor device, comprising:
- a semiconductor substrate having a first main surface;
- a trench extending from the first main surface into the semiconductor substrate;
- a gate electrode in the trench and insulated from the semiconductor substrate;
- a source region having a first conductivity type and formed in the semiconductor substrate at the first surface and adjacent the trench;
- a body region having a second conductivity type and formed in the semiconductor substrate below the first region and adjacent the trench;
- a drift region having the first conductivity type and formed in the semiconductor substrate below the second region and adjacent the trench;
- a contact opening extending through the source region and into the body region;
- an electrically insulative spacer on sidewalls of the semiconductor substrate formed by the contact opening, wherein the electrically insulative spacer is recessed below the first main surface along the sidewalls such that at least part of the source region or body region is uncovered by the electrically insulative spacer;
- a body contact plug in the contact opening;
- a first body contact region having the second conductivity type and formed in the semiconductor substrate adjacent a bottom of the contact opening, wherein the first body contact region adjoins the body contact plug at the bottom of the contact opening; and
- a second body contact region having the second conductivity type and formed in the part of the source region or body region uncovered by the electrically insulative spacer, wherein the second body contact region adjoins the body contact plug along the part of the source region or body region uncovered by the electrically insulative spacer.
2. The semiconductor device of claim 1, wherein the source region extends to the sidewalls, wherein at least part of the source region is uncovered by the electrically insulative spacer, and wherein the second body contact region adjoins the body contact plug along the part of the source region uncovered by the electrically insulative spacer.
3. The semiconductor device of claim 1, wherein the source region is separated from the sidewalls by the body region, wherein at least part of the body region is uncovered by the electrically insulative spacer, and wherein the second body contact region adjoins the body contact plug along the part of the body region uncovered by the electrically insulative spacer.
4. The semiconductor device of claim 1, wherein the contact opening terminates within the body region such that the body contact plug is separated from the drift region by a section of the body region.
5. The semiconductor device of claim 1, wherein the contact opening terminates within the body region, and wherein the first body contact region is formed in the body region.
6. The semiconductor device of claim 5, wherein the source region is separated from the sidewalls by the body region, wherein at least part of the body region is uncovered by the electrically insulative spacer, and wherein the second body contact region adjoins the body contact plug along the part of the body region uncovered by the electrically insulative spacer.
7. The semiconductor device of claim 5, wherein the source region is separated from the sidewalls by the body region, wherein at least part of the body region is uncovered by the electrically insulative spacer, and wherein the second body contact region adjoins the body contact plug along the part of the body region uncovered by the electrically insulative spacer.
8. The semiconductor device of claim 1, wherein the contact opening extends through the body region, and wherein the first body contact region is formed in the drift region.
9. The semiconductor device of claim 8, wherein the source region is separated from the sidewalls by the body region, wherein at least part of the body region is uncovered by the electrically insulative spacer, and wherein the second body contact region adjoins the body contact plug along the part of the body region uncovered by the electrically insulative spacer.
10. The semiconductor device of claim 1, further comprising a drain region having the first conductivity type and formed at a second main surface of the semiconductor substrate opposite the first main surface, wherein the drain region is doped more heavily than the drift region.
11. The semiconductor device of claim 1, further comprising a field plate in the trench below the gate electrode, wherein the field plate is electrically insulated from the gate electrode.
12. The semiconductor device of claim 1, further comprising an interlayer dielectric on the first main surface of the semiconductor substrate, wherein the contact opening extends through the interlayer dielectric and into the semiconductor substrate, and wherein a width of the contact opening is larger in the interlayer dielectric than in the semiconductor substrate such that the electrically conductive material has a stepped profile in the contact opening.
13. The semiconductor device of claim 1, further comprising an interlayer dielectric on the first main surface of the semiconductor substrate, wherein the contact opening extends through the interlayer dielectric and into the semiconductor substrate, and wherein the electrically insulative spacer extends onto the first main surface of the semiconductor substrate and along sidewalls of the interlayer dielectric formed by the contact opening.
14. The semiconductor device of claim 1, wherein the electrically insulative spacer extends onto the first main surface of the semiconductor substrate.
15. The semiconductor device of claim 1, wherein the electrically insulative spacer comprises oxide, nitride, carbon or tetraethoxysilane.
16. A method of producing a semiconductor device, the method comprising:
- forming a trench that extends from a first main surface of a semiconductor substrate into the semiconductor substrate;
- forming a gate electrode in the trench and insulated from the semiconductor substrate;
- forming a source region having a first conductivity type in the semiconductor substrate at the first surface and adjacent the trench;
- forming a body region having a second conductivity type in the semiconductor substrate below the first region and adjacent the trench;
- forming a drift region having the first conductivity type in the semiconductor substrate below the second region and adjacent the trench;
- forming a contact opening that extends through the source region and into the body region;
- forming an electrically insulative spacer on sidewalls of the semiconductor substrate formed by the contact opening, wherein the electrically insulative spacer is recessed below the first main surface along the sidewalls such that at least part of the source region or body region is uncovered by the electrically insulative spacer;
- forming a body contact plug in the contact opening;
- forming a first body contact region having the second conductivity type in the semiconductor substrate adjacent a bottom of the contact opening, wherein the first body contact region adjoins the body contact plug at the bottom of the contact opening; and
- forming a second body contact region having the second conductivity type in the part of the source region or body region uncovered by the electrically insulative spacer, wherein the second body contact region adjoins the body contact plug along the part of the source region or body region uncovered by the electrically insulative spacer.
17. The method of claim 16, wherein the source region extends to the sidewalls, the method further comprising:
- removing the electrically insulative spacer from at least part of the source region,
- wherein the second body contact region adjoins the body contact plug along the part of the source region from which the electrically insulative spacer was removed.
18. The method of claim 16, wherein the source region is separated from the sidewalls by the body region, the method further comprising:
- removing the electrically insulative spacer from at least part of the body region,
- wherein the second body contact region adjoins the body contact plug along the part of the body region from which the electrically insulative spacer was removed.
19. The method of claim 16, further comprising:
- terminating the contact opening within the body region; and
- forming the first body contact region in the body region.
20. The method of claim 16, further comprising:
- extending the contact opening through the body region; and
- forming the first body contact region in the drift region.
Type: Application
Filed: May 17, 2021
Publication Date: Sep 2, 2021
Inventors: Wei-Chun Huang (Torrance, CA), Martin Poelzl (Ossiach), Thomas Feil (Villach), Maximilian Roesch (St. Magdalen)
Application Number: 17/321,695