CARRIER INJECTION CONTROL FAST RECOVERY DIODE STRUCTURES AND METHODS OF FABRICATION
Semiconductor devices and methods of fabrication are provided. The semiconductor device includes a Charge Injection Controlled (CIC) Fast Recovery Diode (FRD) to control charge injection by lowering carrier storage. The device can have a first conductivity type semiconductor substrate, and a drift region that includes a doped buffer region, a doped middle region and a doped field stop region or carrier storage region. The device can also include a second conductivity type shield region including a deep junction encircling (or substantially laterally beneath) the buffer region and a second conductivity type shallow junction anode region in electrical contact with a second conductivity type anode electrode. The deep junction can have a range of doping concentrations surrounding the buffer regions to deplete buffer charge laterally as well as vertically to prevent premature device breakdown. The first conductivity type may be N type and the second conductivity type may be P type.
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The present application is a divisional application of U.S. patent application Ser. No. 16/450,351 filed on Jun. 24, 2019, which is now U.S. Pat. No. 11,069,770 issued on Jul. 20, 2021, and claims the benefit of U.S. Provisional Application Ser. No. 62/739,820 filed Oct. 1, 2018.
FIELDThe present technology pertains in general to power semiconductor devices and more specifically, to fast recovery diode structures.
BACKGROUNDThe approaches described in this section could be pursued, but are not necessarily approaches previously conceived or pursued. Therefore, unless otherwise indicated, it should not be assumed that any of the approaches described in this section qualify as prior art merely by virtue of their inclusion in this section.
Every Insulated Gate Bipolar Transistor (IGBT) requires a Fast Recovery Diode (FRD) across its collector and emitter terminals to handle current conduction during inductive switching type applications such as motor control. To minimize switching losses and lower circuit noise of an FRD, the FRD should have short reverse recovery time, low peak reverse recovery current, soft recovery current, and should also operate at between 150 to 175 Degree C. junction temperature. To lower reverse recovery peak current and shorten recovery time, minority carrier lifetime of the FRDs can be reduced by using gold, platinum or electron beam irradiation.
There are some drawbacks with minority carrier lifetime reduction including more voltage spikes and oscillations being generated during the FRD reverse recovery; leakage current increasing during the blocking stage, especially at higher temperatures such as 150 Degree C. and above; and forward voltage drop (Vf) also increasing as a result of minority carrier lifetime reduction.
SUMMARYThis summary is provided to introduce a selection of concepts in a simplified form that are further described in the Detailed Description below. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
Various embodiments of FRD structures control charge injection by lowering carrier storage and also in some embodiments reducing minority carrier life time in the close vicinity of the Anode rather than reducing minority carrier lifetime in the n-region to avoid adverse effects of the lifetime reduction.
In some embodiments, a method is provided for fabricating a Charge Injection Controlled (CIC) Fast Recovery Diode (FRD), the method comprising forming a drift region of a first conductivity type on top of a heavily doped semiconductor substrate by epitaxial growth, the drift region supporting blocking of high voltage and comprising a buffer region on the top region of the drift region, a lightly doped middle region, and a medium level doped charge storage region; forming trenches, in the drift region, having depth ranging from 2-6 microns; ion implanting dopants of a second conductivity type into the trenches for forming a shield region of the second conductivity type, the shield region comprising a deep junction substantially spreading laterally beneath the buffer region of the first conductivity type; filling the trenches with poly silicon having lightly doped second conductivity type impurities encircling the buffer region of the first conductivity type; after planarizing the poly silicon in the trenches, ion implanting dopants of the second conductivity type to define a lightly doped anode; depositing Boron-doped Phospho Silicate Glass layer (BPSG) or Phospho Silicate Glass layer (PSG) for defining a contact; depositing poly silicon and ion implanting with the second conductivity type dopants with varying doping level for, at least in part, controlling carrier injection.
Embodiments are illustrated by way of example, and not by limitation, in the figures of the accompanying drawings, in which like references indicate similar elements and in which:
While this technology is susceptible of embodiment in many different forms, there is shown in the drawings and will herein be described in detail several specific embodiments with the understanding that the present disclosure is to be considered as an exemplification of the principles of the technology and is not intended to limit the technology to the embodiments illustrated. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the technology. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that like or analogous elements and/or components, referred to herein, may be identified throughout the drawings with like reference characters. It will be further understood that several of the figures are merely schematic representations of the present technology. As such, some of the components may have been distorted from their actual scale for pictorial clarity.
The present disclosure is related to various embodiments of systems and methods for providing Fast Recovery Diode structures to control the charge injection by lowering the carrier storage rather than reducing the minority carrier lifetime to avoid adverse effects of the lifetime reduction with the exception of local minority carrier life time reduction in the close vicinity of the Anode in some embodiments.
For the FRDs with anode Charge Injection Control (CIC) structures 200 and 210 in
FIG. 4A1 illustrates that, for an example poly anode CIC FRD, the process includes, identified at 402, starting a wafer with n-n-n epi on an n+ Substrate.
including a high energy boron ion implant and drive; and depositing oxide and chemical mechanical planarization (CMP) oxide to planarize the wafer surface.
FIG. 4B1 illustrates, according to various embodiments, aspects of the process flow for the example mask, the process flow including, identified at 406, trenching etch for deep P junctions with an nn-n type wafer; etching a 2-3 microns deep and 0.5 to 1 microns wide trench;
including a high energy boron ion implant and drive; depositing oxide and CMP oxide to planarize the wafer surface; and having a high energy phosphor ion implant and drive in without a mask.
FIG. 4B2 illustrates, according to various embodiments, aspects of the process flow for an example mask, the process flow including, identified at 408, trenching etch for deep P junctions; etching a 2-3 microns deep and 0.5 to 1 microns wide trench; including a high energy boron ion implant and drive; depositing un-doped poly silicon and etch or CMP poly silicon to planarize the wafer surface; and having a high energy phosphor ion implant and drive in without a mask.
FIG. 4G1 illustrates, according to various embodiments, aspects of the process including, identified at 420, for cathode electrode formation for a poly anode CIC FRD, after pad mask, grinding the wafers, if n+ substrate and deposit backside metal Ti/Ni/Ag or Gold to form a cathode electrode; and having final structures with un-doped poly silicon filling the trenches.
In various embodiments, using poly silicon as an anode instead of crystalline silicon reduces minority carrier lifetime in the vicinity of P+ poly Silicon anode.
In various embodiments, filling trenches with P+ poly silicon reduces minority carrier lifetime in the vicinity of P+ poly Silicon and P anode region without increasing the leakage of the FRD during high voltage blocking mode, because depletion does not reach into the highly defective Poly Silicon regions which is guarded by P shield vertically and P anode.
Even though
FIG. 8D1 shows an example Mask 802, of
FIG. 8D2 shows an alternative embodiment of the example Mask 802, of
FIG. 8F1 illustrates an example Mask 803, of
FIG. 8F2 shows an alternative embodiment of the example Mask 803, poly/metal mask for an alternative embodiments of the active FRD region. For the example in FIG. 8F2, the process includes depositing poly Si and implanting boron as an anode to control hole injection, and depositing metal and etching of the metal and poly Si from the defined regions.
FIG. 8F3 shows another example an alternative embodiment of the Mask 803, poly/metal mask for another alternative embodiments of the active FRD region. For the example in FIG. 8F3, the process includes filling the trenches with the poly Si, planarizing and implanting Boron after Mask 801 as an anode to control hole injection; depositing metal (Al:Si:Cu) and etching off the metal.
In various embodiments, in addition to controlling the hole and electron injection by P+ poly Si anode doping, n+ poly Si cathode and the n buffer doping concentration, localized minority carrier lifetime reduction can be achieve by creating poly Silicon filled trenches as recombination centers. The process flow as shown in the examples in
The 5 mask process of the example in
The description of the present technology has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. Exemplary embodiments were chosen and described in order to best explain the principles of the present technology and its practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
Claims
1. A method of fabricating a Charge Injection Controlled (CIC) Fast Recovery Diode (FRD), the method comprising:
- forming a drift region of a first conductivity type on top of a heavily doped semiconductor substrate by epitaxial growth, the drift region supporting blocking of high voltage and comprising a buffer region on the top region of the drift region, a lightly doped middle region, and a medium level doped charge storage region;
- forming trenches, in the drift region, having depth ranging from 2-6 microns;
- ion implanting dopants of a second conductivity type into the trenches for forming a shield region of the second conductivity type, the shield region comprising a deep junction substantially spreading laterally beneath the buffer region of the first conductivity type;
- filling the trenches with poly silicon having lightly doped second conductivity type impurities encircling the buffer region of the first conductivity type;
- after planarizing the poly silicon in the trenches, ion implanting dopants of the second conductivity type to define a lightly doped anode;
- depositing Boron-doped Phospho Silicate Glass layer (BPSG) or Phospho Silicate Glass layer (PSG) for defining a contact;
- depositing poly silicon and ion implanting with the second conductivity type dopants with varying doping level for, at least in part, controlling carrier injection.
2. The method of claim 1, further comprising forming a high voltage termination region surrounding an active area, the high voltage termination region comprising a plurality of floating rings of additional poly silicon filled trenches on top of the second conductivity type shield region.
3. The method of claim 1, further comprising forming a Schottky contact on the surface of the buffer region surrounded on two or all sides by the shield region for forming a hybrid schottky and junction Fast Recovery Diode (HSJ FRD).
4. A method of fabricating a Charge Injection Controlled (CIC) Fast Recovery Diode (FRD), the method comprising:
- forming a drift region of a first conductivity type on top of a heavily doped semiconductor substrate by epitaxial growth, the drift region supporting blocking of high voltage and comprising: a medium level doped buffer region on the top region of the drift region, a lightly doped middle region, and a medium level doped field stop region;
- forming trenches, in the drift region, having depth ranging from 2-6 microns;
- ion implanting dopants of a second conductivity type into the trenches for forming a shield region of the second conductivity type, the shield region comprising a deep junction substantially expanding laterally in the lightly doped middle region;
- filling trenches with a dielectric layer encircling medium level doped buffer region of the drift region;
- forming a shallow and lightly doped junction anode region of the second conductivity type;
- depositing a poly silicon layer doped by ion implantation as an anode, of the second conductivity type, after depositing and defining contact regions;
- depositing a frontside metal and passivation layer; and
- grinding a FRD wafer backside and etching to thin the wafer and depositing backside metal Titanuim:Nickel:Silver (Ti:Ni:Ag) alloy or gold (Au) to form at least an anode electrode;
- wherein the first conductivity type is N type and the second conductivity type is P type.
5. A method of fabrication Charge Injection Controlled (CIC) Fast Recovery Diode (FRD), the method comprising:
- forming a drift region of a first conductivity type on top of a lightly doped semiconductor substrate, the drift region supporting blocking of high voltage and comprising: a buffer region on the top region of the drift region, a lightly doped middle region, and a medium level doped field stop region;
- forming trenches, in the drift region, having depth ranging from 2-6 microns;
- ion implanting dopants of a second conductivity type into the trenches for forming a shield region of the second conductivity type, the shield region comprising a deep junction substantially expanding laterally in the lightly doped middle region;
- filling trenches;
- forming a shallow junction anode region of the second conductivity type;
- depositing a poly silicon layer doped by ion implantation as an anode, of the second conductivity type, after depositing and defining contact regions;
- depositing a frontside metal and passivation layer;
- grinding a FRD wafer backside and etching to thin the wafer down to a predetermined thickness;
- sputtering N+ silicon or N+ poly S as a cathode to a whole or certain portion of the wafer backside, depositing a dielectric layer to the wafer backside, wherein cathode contacts are opened via a mask before the sputtering of the N+ Silicon or N+ poly Si; and
- depositing metal Ti:Ni:Ag or Au to the wafer backside and sintering for completing fabrication of the wafer for the FRD;
- wherein the first conductivity type is N type and the second conductivity type is P type.
6. The method of claim 5,
- wherein the buffer region of the drift region is medium level doped; and
- wherein the trenches are filled with the second conductivity type poly silicon encircling the medium level doped buffer region.
7. The method of claim 5,
- wherein the buffer region of the drift region is high level doped; and
- wherein the trenches are filled with a dielectric (SiO2) and a CMP dielectric layer to planarize a surface of the wafer surrounding the buffer region.
8. A method of fabrication Charge Injection Controlled (CIC) Fast Recovery Diode (FRD), the method comprising:
- forming a drift region of a first conductivity type on top of a heavily doped semiconductor substrate by epitaxial growth, the drift region supporting blocking of high voltage and comprising: a medium level doped buffer region on the top region of the drift region, a lightly doped middle region, and a medium level doped field stop region;
- forming trenches, in the drift region, having depth ranging from 2-6 microns;
- ion implanting dopants of a second conductivity type into the trenches for forming a shield region of the second conductivity type, the shield region comprising a deep junction substantially expanding laterally in the lightly doped middle region;
- filling trenches with poly silicon of the second conductivity type formed by ion implantation surrounding two or all sides of the medium level doped buffer region;
- an anode electrode electrically in contact with the second conductivity type poly silicon filling the trenches;
- varying the doping concentration of the poly silicon filling the trenches to control, at least in part, the carrier injection and resulting reverse recovery time of the FRD;
- depositing a BPSG or PSG for defining contact regions;
- depositing metal and passivation layer; and
- grinding a FRD wafer backside and etching to thin the wafer down to a predetermined thickness and depositing backside metal Ti:Ni:Ag alloy or Au.
9. The method of claim 8, further comprising forming side wall spacers, the forming including depositing or thermally growing oxide inside the trenches reactive-ion etching (RIE) etching the oxide from the bottom of the trenches before filling the trenches.
Type: Application
Filed: Jul 20, 2021
Publication Date: Jan 13, 2022
Applicant: IPOWER SEMICONDUCTOR (Gilroy, CA)
Inventor: HAMZA YILMAZ (GILROY, CA)
Application Number: 17/381,125