SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A method includes forming a semiconductor fin over a substrate; forming first, second, and third gate structures crossing the semiconductor fin; forming first source/drain epitaxy structures over the semiconductor fin and on opposite sides of the first gate structure and forming second source/drain epitaxy structures over the semiconductor fin and on opposite sides of the second gate structure, wherein bottom of the first source/drain epitaxy structures and bottom of the second source/drain epitaxy structures are lower than a top surface of the semiconductor fin; removing the third gate structure to expose the top surface of the semiconductor fin; forming an isolation structure in the semiconductor fin, wherein a bottom of the isolation structure is lower than the bottom of the first source/drain epitaxy structures and the bottom the second source/drain epitaxy structures.
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This application is a Divisional Application of U.S. application Ser. No. 15/628,728, filed Jun. 21, 2017, now U.S. Pat. No. 11,387,232, issued on Jul. 12, 2022, which claims priority to U.S. Provisional Application Ser. No. 62/475,330, filed Mar. 23, 2017, which are herein incorporated by references.
BACKGROUNDThe semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.
Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. For example, a three dimensional transistor, such as a fin-like field-effect transistor (FinFET), has been introduced to replace a planar transistor.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
The present disclosure is directed to, but not otherwise limited to, a FinFET device. The FinFET device, for example, may be a complementary metal-oxide-semiconductor (CMOS) device comprising a P-type metal-oxide-semiconductor (PMOS) FinFET device and an N-type metal-oxide-semiconductor (NMOS) FinFET device. The following disclosure will continue with a FinFET example to illustrate various embodiments of the present invention. It is understood, however, that the application should not be limited to a particular type of device, except as specifically claimed.
Reference is made to
Some exemplary substrate 100 also includes an insulator layer. The insulator layer includes suitable materials, including silicon oxide, sapphire, and/or combinations thereof. An exemplary insulator layer may be a buried oxide layer (BOX). The insulator is formed by one or more suitable process(es), such as implantation (e.g., SIMOX), oxidation, deposition, and/or other suitable process. In some exemplary semiconductor substrate 100, the insulator layer is a component (e.g., layer) of a silicon-on-insulator substrate.
The substrate 100 may also include various doped regions. The doped regions may be doped with p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; or combinations thereof. The doped regions may be formed directly on the substrate 100, in a P-well structure, in an N-well structure, in a dual-well structure, and/or using a raised structure. The substrate 100 may further include various active regions, such as regions configured for an N-type metal-oxide-semiconductor transistor device and regions configured for a P-type metal-oxide-semiconductor transistor device.
In some embodiments, the substrate 100 also includes a fin structure 110. The fin structure 110 may be patterned by any suitable method. For example, the fin structure 110 may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fin structure 110.
A plurality of isolation structures 105 are formed on the substrate 100 and adjacent to the fin structure 110. The isolation structures 105, which act as a shallow trench isolation (STI) around the fin structure 110 may be formed by chemical vapor deposition (CVD) techniques using tetra-ethyl-ortho-silicate (TEOS) and oxygen as a precursor. In yet some other embodiments, the isolation structures 105 are insulator layers of a SOI wafer.
A gate dielectric 115, a dummy gate material layer 120, and a mask layer 131 are deposited sequentially on a substrate 100 by, for example, low pressure CVD (LPCVD) and plasma enhanced (PECVD).
A photo resist pattern (not shown) is coated on the mask layer 131 and is exposed and developed to form a desire pattern. The mask layer 131 is dry etched (such as plasma etching) in turn with the photo resist pattern as a mask, until the dummy gate material layer 120 is exposed. As a result, the patterned mask layer 131 is formed. The plasma etching gas may include gas containing halogen, for example, fluoro-gases such as fluorocarbon gas (CxHyFZ), NF3, SF6, or other halogen-containing gases such as Cl2, Br2, HBr, HCl, or it may include oxidants such as oxygen, ozone and oxynitride. In some embodiments, after etching, wet cleaning is performing with de-ionized water and the like or dry cleaning is performing with oxygen, fluorinated gas and the like to completely remove the resultant of etching.
The gate dielectric 115 may be formed by thermal oxidation, chemical vapor deposition, sputtering, or other methods known and used in the art for forming a gate dielectric. The gate dielectric 115 may include, for example, a high-k dielectric material such as metal oxides, metal nitrides, metal silicates, transition metal-oxides, transition metal-nitrides, transition metal-silicates, oxynitrides of metals, metal aluminates, zirconium silicate, zirconium aluminate, or combinations thereof.
The dummy gate material layer 120 may include materials having different etching selectivity from the materials of the mask layer 131, such as polycrystalline silicon, amorphous silicon and/or microcrystal silicon. The mask layer 131, which is used as a hard mask layer during etching later, may include silicon oxide, silicon nitride and/or silicon oxynitride. In some embodiments, the dummy gate material layer 120 may include polycrystalline-silicon (poly-Si) or poly-crystalline silicon-germanium (poly-SiGe). Further, the dummy gate material layer 120 may be doped poly-silicon with uniform or non-uniform doping.
The mask layer 131, in some other embodiments, may include silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), SiOC, spin-on glass (SOG), a low-K film, tetraethylorthosilicate (TEOS), plasma enhanced CVD oxide (PE-oxide), high-aspect-ratio-process (HARP) formed oxide, amorphous carbon material, tetraethylorthosilicate (TEOS), other suitable materials, and/or combinations thereof.
Reference is made to
In some embodiments, the dummy gate material layer 120 and the gate dielectric 115 (see
Reference is made to
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Reference is made to
In some embodiments, the source/drain features 152 and 154 may be epitaxy structures, and may also be referred to as epitaxy structures 152 and 154. The source/drain features 152 and 154 may be formed using one or more epitaxy or epitaxial (epi) processes, such that Si features, SiGe features, and/or other suitable features can be formed in a crystalline state on the fin structure 110. In some embodiments, lattice constants of the source/drain features 152 and 154 are different from lattice constants of the fin structure 110, and the source/drain features 152 and 154 are strained or stressed to enable carrier mobility of the semiconductor device and enhance the device performance. The source/drain features 152 and 154 may include semiconductor material such as germanium (Ge) or silicon (Si); or compound semiconductor materials, such as gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), silicon germanium (SiGe), silicon carbide (SiC), or gallium arsenide phosphide (GaAsP).
In some embodiments, for a NMOS transistor, the source/drain features 152 and 154 may include SiP, SiC, SiPC, Si, III-V compound semiconductor materials, or combinations thereof for the n-type epitaxy structure. During the formation of the n-type epitaxy structure, n-type impurities such as phosphorous or arsenic may be doped with the proceeding of the epitaxy. For example, when the source/drain features 152 and 154 include SiC or Si, n-type impurities are doped. The epitaxy processes include CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and/or other suitable processes. The epitaxy process may use gaseous and/or liquid precursors, which interact with the composition of the fin structure 110 (e.g., silicon). Thus, a strained channel can be achieved to increase carrier mobility and enhance device performance. The source/drain features 152 and 154 may be in-situ doped. If the source/drain features 152 and 154 are not in-situ doped, a second implantation process (i.e., a junction implant process) is performed to dope the source/drain features 152 and 154. One or more annealing processes may be performed to activate the source/drain features 152 and 154. The annealing processes include rapid thermal annealing (RTA) and/or laser annealing processes.
Reference is made to
Reference is made to
The dummy gate 122 is removed to from a recess 114 in the second region 184. The recess 114 exposes portions of the fin structure 110 of the substrate 100 in the second region 184. In some embodiments, the dummy gate 122 is removed by a selective etch process, including a selective wet etch or a selective dry etch, and carries vertical profile of the gate spacers 140. With the selective etch process, the recess 114 is formed with a self-alignment nature, which relaxes process constrains, such as misalignment, and/or overlay issue in lithograph process, recess profile controlling in etch process, pattern loading effect, and etch process window.
Reference is made to
Reference is made to
A replacement gate (RPG) process scheme is employed. In some embodiments, in a RPG process scheme, a dummy gate is formed first and is replaced later by a metal gate after high thermal budget processes are performed. Accordingly, the dummy gate 121 (see
Reference is made to
In some embodiments, the gate metal 214 included in the first gate stack 210 may include a single layer or alternatively a multi-layer structure, such as various combinations of a metal layer with a work function to enhance the device performance (work function metal layer), liner layer, wetting layer, adhesion layer and a conductive layer of metal, metal alloy or metal silicide). For example, the gate metal 214 may be an n-type or p-type work function layer. Exemplary p-type work function metals include TIN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function metals include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. The work function layer may include a plurality of layers. The work function layer(s) may be deposited by CVD, PVD, electro-plating and/or other suitable process. In some embodiments, the first gate stack 210 formed is a p-type metal gate including a p-type work function layer. In some embodiments, the capping layer included in the first gate stack 210 may include refractory metals and their nitrides (e.g. TiN, TaN, W2N, TiSiN, TaSiN). The cap layer may be deposited by PVD, CVD, Metal-organic chemical vapor deposition (MOCVD) and ALD. In some embodiments, the fill layer included in the first gate stack 210 may include tungsten (W). The metal layer may be deposited by ALD, PVD, CVD, or other suitable process.
In some embodiments, the interfacial layer may include a dielectric material such as silicon oxide (SiO2), HfSiO, and/or silicon oxynitride (SiON). The interfacial layer may be formed by chemical oxidation, thermal oxidation, ALD, CVD, and/or other suitable method. The gate dielectric 212 may include a high-K dielectric layer such as hafnium oxide (HfO2). Alternatively, the gate dielectric 212 may include other high-K dielectrics, such as TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), Al2O3, Si3N4, oxynitrides (SiON), combinations thereof, or other suitable material. The high-K gate dielectric 212 may be formed by ALD, PVD, CVD, oxidation, and/or other suitable methods.
Reference is made to
A replacement gate (RPG) process scheme is employed to the dummy gate 123 (see
The gate metal 234 of the second gate stack 230 is different from the gate metal 214 of the first gate stack 210 to define different threshold voltage (VT) region. That is, a metal component of the first gate stack 210 is different from a metal component of the second gate stack 230. As a result, the first region 182 and the third region 186 may also be referred to as a first VT region 182 and a second VT region 186, respectively. Moreover, the dielectric structure 190′ may act as an isolation structure to separated different VT regions. Accordingly, the second region 184 may be referred to as an isolation region 184, and the dielectric structure 190′ may also be referred to as an isolation structure 190′.
Reference is made to
Since the dummy gates 121, 122, and 123 have substantially the same profiles, the first gate stack 210, the dielectric structure 190, and the second gate stack 230 accordingly have substantially the same profiles (or shapes). As a result, the length T2 of the dielectric structure 190′ is substantially equal to the gate lengths T1 and T3 of the first gate stack 210 and the second gate stack 230. A distance D1 between a first side 210A of the first gate stack 210 and the first side 190A of the dielectric structure 190′ is substantially equal to a distance D2 between a first side 190A of the dielectric structure 190′ and the first side 230A of the second gate stack 230. In other words, the distance D1 (or D2) is substantially equal to half of a distance D3 between a first side 210A of the first gate stack 210 and the first side 230A of the second gate stack 230. The distances D1 and D2 may also be referred to as gate pitches. From another perspective, a distance D11 between the first gate stack 210 and the dielectric structure 190′ is substantially equal to a distance D22 between the dielectric structure 190′ and the second gate stack 230.
Reference is made to
At least one of the source/drain features 152 is disposed over the substrate 100 and between the first gate stack 210 and the dielectric structure 190′, and at least one of the source/drain features 154 is disposed over the substrate 100 and between the second gate stack 230 and the dielectric structure 190′. Moreover, a bottom surface 210S of the first gate stack 210, a bottom surface 230S of the second gate stack 230, and a bottom surface 192 of the dielectric structure 190′ are substantially coplanar.
Reference is made to
Reference is made to
Reference is made to
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Reference is made to
According to the aforementioned embodiments, a dummy gate is replaced by a dielectric structure to isolate at least two gate stacks having different metal components. The formation of the dielectric structure may reduce the device scale, such as a distance between two active gates. With this configuration, the performance of the semiconductor device can be improved.
According to some embodiments, a method includes forming a semiconductor fin over a substrate; forming first, second, and third gate structures crossing the semiconductor fin; forming first source/drain epitaxy structures over the semiconductor fin and on opposite sides of the first gate structure and forming second source/drain epitaxy structures over the semiconductor fin and on opposite sides of the second gate structure, wherein bottom of the first epitaxy structures and bottom of the second epitaxy structures are lower than a top surface of the semiconductor fin; removing the third gate structure to expose the top surface of the semiconductor fin; forming an isolation structure in the semiconductor fin, wherein a bottom of the isolation structure is lower than the bottom of the first epitaxy structures and the bottom of the second epitaxy structures.
According to some embodiments, a method includes forming a semiconductor fin over a substrate; forming first, second, and third gate structures crossing the semiconductor fin; forming first spacers on opposite sidewalls of the first gate structure, second spacers on opposite sidewalls of the second gate structure, and third spacers on opposite sidewalls of the third gate structure; forming first epitaxy structures over the semiconductor fin and on opposite sides of the first gate structure and forming second epitaxy structures over the semiconductor fin and on opposite sides of the second gate structure; removing the third gate structure to form a trench between the third spacers to expose a portion of the semiconductor fin; etching the portion of the semiconductor fin exposed by the trench between the third spacers; and forming a dielectric structure filling an entirety of the trench between the third spacers.
According to some embodiments, a method includes forming a semiconductor fin over a substrate; forming first, second, and third gate structures crossing the semiconductor fin; forming first epitaxy structures over the semiconductor fin and on opposite sides of the first gate structure and forming second epitaxy structures over the semiconductor fin and on opposite sides of the second gate structure; removing the third gate structure to expose a portion of the semiconductor fin; performing an implantation process to form an implantation region in the exposed portion of the semiconductor fin; and forming a dielectric structure over the implantation region in the semiconductor fin.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims
1. A method, comprising:
- forming a semiconductor fin over a substrate;
- forming first, second, and third gate structures crossing the semiconductor fin;
- forming first epitaxy structures in the semiconductor fin and on opposite sides of the first gate structure, and forming second epitaxy structures in the semiconductor fin and on opposite sides of the second gate structure, wherein bottom of the first epitaxy structures and bottom of the second epitaxy structures are lower than a top surface of the semiconductor fin;
- removing the third gate structure to form a recess in the semiconductor fin;
- forming an isolation structure in the recess, wherein a bottom of the isolation structure is lower than the bottom of the first epitaxy structures and the bottom of the second epitaxy structures.
2. The method of claim 1, wherein the isolation structure has a curved bottom from a cross-sectional view.
3. The method of claim 1, further comprising forming shallow trench isolation structures laterally surrounding the semiconductor fin, wherein the bottom of the isolation structure is lower than top surfaces of the shallow trench isolation structures.
4. The method of claim 1, further comprising forming an implantation region interfacing the bottom of the isolation structure.
5. The method of claim 1, further comprising after forming the isolation structure, replacing the first and second gate structures with first and second metal gate structures, respectively.
6. The method of claim 1, further comprising forming spacers on opposite sidewalls of the first, second, and third gate structures, wherein removing the third gate structure is performed to form a trench between a pair of the spacers, and the isolation structure is formed in contact with the pair of the spacers.
7. The method of claim 1, wherein the isolation structure has a greater width variation below the top surface of the semiconductor fin than above the top surface of the semiconductor fin.
8. The method of claim 1, wherein a width of the isolation structure above the top surface of the semiconductor fin is substantially equal to a width of the first and second gate structures.
9. The method of claim 1, wherein the isolation structure is made of a single material.
10. A method, comprising:
- forming a semiconductor fin over a substrate;
- forming first, second, and third gate structures crossing the semiconductor fin;
- forming first spacers on opposite sidewalls of the first gate structure, second spacers on opposite sidewalls of the second gate structure, and third spacers on opposite sidewalls of the third gate structure;
- forming first epitaxy structures in the semiconductor fin and on opposite sides of the first gate structure and forming second epitaxy structures in the semiconductor fin and on opposite sides of the second gate structure;
- removing the third gate structure to form a trench between the third spacers to expose a portion of the semiconductor fin;
- etching the portion of the semiconductor fin exposed by the trench between the third spacers; and
- forming a dielectric structure filling an entirety of the trench between the third spacers.
11. The method of claim 10, further comprising after forming the dielectric structure, replacing the first and second gate structures with first and second metal gate structures, respectively.
12. The method of claim 10, further comprising performing an implantation process to form an implantation region in a portion of the semiconductor fin directly below the trench between the third spacers.
13. The method of claim 12, wherein the implantation region is lower than bottoms of the first and second epitaxy structures.
14. The method of claim 10, further comprising performing a planarization process to the dielectric structure.
15. A method, comprising:
- forming a semiconductor fin over a substrate;
- forming first, second, and third gate structures crossing the semiconductor fin;
- forming first epitaxy structures in the semiconductor fin and on opposite sides of the first gate structure and forming second epitaxy structures in the semiconductor fin and on opposite sides of the second gate structure;
- removing the third gate structure to expose a portion of the semiconductor fin;
- performing an implantation process to form an implantation region in the exposed portion of the semiconductor fin; and
- forming a dielectric structure over the implantation region in the semiconductor fin.
16. The method of claim 15, further comprising:
- after forming the dielectric structure, replacing the first gate structure with a first metal gate structure; and
- after replacing the first gate structure with the first metal gate structure, replacing the second gate structure with a second metal gate structure, wherein the first and second gate structures have different compositions.
17. The method of claim 15, further comprising forming first spacers on opposite sidewalls of the first gate structure, second spacers on opposite sidewalls of the second gate structure, and third spacers on opposite sidewalls of the third gate structure, wherein removing the third gate structure is performed to form a trench between the third spacers, and a widest width of the implantation region is substantially equal to a distance between the third spacers.
18. The method of claim 15, wherein a bottom of the implantation region is higher than bottoms of the first and second epitaxy structures.
19. The method of claim 15, wherein a height of the dielectric structure is substantially equal to heights of the first and second gate structures.
20. The method of claim 15, wherein a top surface of the implantation region is level with a top surface of the semiconductor fin.
Type: Application
Filed: Jun 24, 2022
Publication Date: Oct 6, 2022
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. (Hsinchu)
Inventors: Cheng-Han WU (Hsinchu City), Chie-Iuan LIN (Hsinchu County), Kuei-Ming CHANG (New Taipei City), Rei-Jay HSIEH (Miaoli County)
Application Number: 17/848,875