Controlling a real-time rendering engine using a list-based control mechanism
A system and method for controlling a real-time rendering engine includes a control program for defining in regions of system memory a block header and a list of flow-control instructions.
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Claims
1. A method for controlling a real-time rendering engine comprising the steps of:
- defining in a first region of system memory, a block header comprising
- an instructions count field for storing the number of instructions within a block;
- an instruction identification field for defining the format of the corresponding instructions;
- a hardware version number field for identifying the supported hardware version level; and
- enable/bypass fields for programmably enabling or bypassing rendering functions;
- where the block header is to be processed before the corresponding instructions; and
- defining in a second region of said memory, flow-control instructions.
2. The method of claim 1, further comprising the step of defining in the block header a vertex replace-mode field for controlling automatic generation of `strip` and `fan` forms of triangle chains.
3. The method of claim 1, wherein said flow-control instructions comprise time-deferred vertex-based draw lists.
4. The method of claim 1, wherein said flow-control instructions comprise `immediate` instructions for issuing commands to the rendering engine on a non-time-deferred basis.
5. A computer-readable memory device encoded with a block header for controlling a real-time rendering engine, comprising:
- an instructions count field for storing the number of instructions within a block;
- an instruction identification field for defining the format of the corresponding instructions;
- a hardware version number field for identifying the supported hardware version level; and
- enable/bypass fields for programmably enabling or bypassing rendering functions.
6. The computer-readable memory device of claim 5, further comprising a list of flow-control instructions.
7. The computer-readable memory device of claim 5, wherein the flow-control instructions comprise time-deferred vertex-based draw lists.
8. The computer-readable memory device of claim 5, wherein said flow-control instructions comprise `immediate` instructions for issuing commands to the rendering engine on a non-time-deferred basis.
9. The computer-readable memory device of claim 5, wherein the block header comprises a vertex replace-mode field for controlling automatic generation of `strip` and `fan` forms of triangle chains.
10. A system for controlling a real-time rendering engine comprising:
- a central processing unit (CPU);
- coupled to the CPU, a memory comprising a control program for defining in a first region of system memory, a block header comprising:
- an instructions count field for storing the number of instructions within a block;
- an instruction identification field for defining the format of the corresponding instructions;
- a hardware version number field for identifying the supported hardware version level; and
- enable/bypass fields for programmably enabling or bypassing rendering functions;
- coupled to the CPU, a memory comprising a control program for defining in a second region of system memory, flow-control instructions.
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Type: Grant
Filed: May 10, 1995
Date of Patent: Aug 25, 1998
Assignee: Cagent Technologies, Inc. (Redwood City, CA)
Inventors: Adrian Sfarti (Sunnyvale, CA), Nicholas Robert Baker (Sunnyvale, CA), Robert William Laker (Fremont, CA), Adam Craig Malamy (Palo Alto, CA)
Primary Examiner: Phu K. Nguyen
Assistant Examiner: Rudolph Buchel
Law Firm: Fenwick & West LLP
Application Number: 8/438,860
International Classification: G06T 1500;
