Synchronous semiconductor memory device realizing high speed and accurate operation

A synchronous semiconductor memory device is provided with a delay circuit between an input latch circuit and a pad. The synchronous semiconductor memory device can operate at a higher speed since respective external input signals supplied to a plurality of pads are delayed such that the time required for transmission from respective pads to the input latch circuit is equal, and that skew is eliminated.

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Claims

1. A synchronous semiconductor memory device operating in synchronization with a clock signal, comprising:

latch means responsive to said clock signal for latching internal signals;
a plurality of input buffering means connected to said latch means, for buffering supplied external signals and for generating said internal signals, respectively; and
delay means connected between at least one of said plurality of input buffering means and said latch means, for delaying the internal signal generated by said at least one input buffering means, wherein
a time period when said internal signal is transmitted from said at least one input buffering means to said latch means is the same as a time period when the other of said internal signals is transmitted from the other of said input buffering means to said latch means.

2. A synchronous semiconductor memory device operating in synchronization with an external clock signal, comprising:

internal clock signal generating means responsive to said external clock signal for generating an internal clock signal;
a plurality of output buffers connected to said internal clock signal generating means responsive to said internal clock signal for outputting data, respectively;
delay means connected between at least one of said plurality of output buffers and said internal clock signal generating means for delaying said internal clock signal to be supplied to said at least one output buffer such that said internal clock signal generated in said internal clock signal generating means is simultaneously transmitted to said plurality of output buffers.

3. A synchronous semiconductor memory device operating in synchronization with an external clock signal, comprising:

clock buffering means for buffering said external clock signal and for generating an internal clock signal;
input buffering means for buffering an externally supplied control signal or address signal and for generating an internal control signal or an internal address signal;
data buffering means for buffering externally supplied data;
latch means responsive to said internal clock signal for latching the data buffered by said data buffering means and one of said internal control signal and said internal address signal; and
delay means connected between said data buffering means and said latch means for delaying the data buffered by said buffering means, wherein
a time period when said data is transmitted from said data buffering means to said latch means is the same as a time period when said internal control signal or said internal address signal is transmitted from said input buffering means to said latch means.

4. The synchronous semiconductor memory device according to claim 3, wherein

the synchronous semiconductor memory device is used as a memory module arranged on a module substrate, said synchronous semiconductor memory device further comprising:
an input/output terminal connected to an input/output data pin on said module substrate; and
input terminals connected to a control signal input pin or an address signal input pin on said module substrate, larger in number than said input/output terminal.

5. The synchronous semiconductor memory device according to claim 4, wherein

said delay means delays the data buffered by said data buffering means for a time period equal to difference between the delay time caused when said control signal or said address signal is transmitted from said control signal input pin or said address signal input pin to one of said input terminals and the delay time caused when said externally supplied data is transmitted from said input/output data pin to said input/output terminal.
Referenced Cited
U.S. Patent Documents
5444667 August 22, 1995 Obara
5454116 September 26, 1995 Harigai et al.
5535171 July 9, 1996 Kim et al.
5581512 December 3, 1996 Kitamura
5623453 April 22, 1997 Shinozaki
5627794 May 6, 1997 Lee
Foreign Patent Documents
6-311012 November 1994 JPX
7-86916 March 1995 JPX
7-141860 June 1995 JPX
Patent History
Patent number: 5805603
Type: Grant
Filed: Jan 7, 1997
Date of Patent: Sep 8, 1998
Assignee: Mitsubishi Denki Kabushiki Kaisha (Tokyo)
Inventors: Takashi Araki (Hyogo), Yasuhiro Konishi (Hyogo), Hisashi Iwamoto (Hyogo)
Primary Examiner: Robert W. Beausoliel, Jr.
Assistant Examiner: Nadeem Iqbal
Law Firm: Lowe, Price, LeBlanc & Becker
Application Number: 8/779,068
Classifications
Current U.S. Class: 371/1; 395/552
International Classification: G11C 800;