Flash memory and method of fabricating the same
In a method of fabricating a flash memory, a substrate with isolation structures formed therein and a dielectric layer and a floating gate formed thereon between isolation structures is provided. A mask layer is formed on the substrate, covering the isolation structures in a periphery region and the isolation structure in a cell region adjacent to the periphery region. The isolation structures in the cell region not covered by the mask layer are partially removed. Therefore, a first height difference is between surfaces of the isolation structures in the periphery region and a surface of the dielectric layer, and between a surface of the isolation structure in the cell region adjacent to the periphery region and the surface of the dielectric layer. A second height difference smaller than the first height difference is between surfaces of other isolation structures in the cell region and the surface of the dielectric layer.
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1. Field of the Invention
The present invention relates to a memory and a method of fabricating the same, and more particularly to a flash memory and a method of fabricating the same.
2. Description of Related Art
A non-volatile memory allows multiple data writing, reading and erasing operations. Moreover, the stored data are retained even after the power of a device has been shut down. With these advantages, the non-volatile memory has become one of the most widely adopted memories for personal computers and electronic equipments. Generally, a typical memory device includes a stacked gate structure constituted by a floating gate and a control gate. The floating gate is disposed between the control gate and a substrate and is in a floating state. The control gates are connected to word lines. Moreover, a tunneling dielectric layer is disposed between the substrate and the floating gates, and a inter-gate dielectric layer is disposed between the floating gates and the control gates.
Conventionally, the floating gates are disposed between isolation structures, and surfaces of the floating gates are, for instance, aligned with surfaces of the isolation structures. Therefore, area of the exposed surfaces of the floating gates is increased by removing a portion of the isolation structures disposed between the floating gates. Consequently, contact areas between the floating gates and the control gates are increased so as to enhance a gate-coupling ratio (GCR).
However, the memory device includes a cell region and a periphery region. In order to remove a portion of the isolation structures between the floating gates in the cell region, a portion of the isolation structures in the periphery region is usually removed simultaneously. In the periphery region, a gate dielectric layer on the substrate disposed between the isolation structures is exposed when isolation structures are excessively removed. As a result, the gate dielectric layer is degraded in the following etching process and cleansing process, thereby affecting electrical properties of devices in the periphery region. In addition, a inter-gate dielectric layer is formed on the substrate after a portion of isolation structures is removed. After that, the inter-gate dielectric layer and the floating gates in the periphery region are removed subsequently. If a height difference between surfaces of the isolation structures in the periphery region and surfaces of the floating gates is great, the subsequent etching process for removing the inter-gate dielectric layer and the floating gates in the periphery region will be difficult to proceed due to a spacer effect.
Hence, how to remove a portion of the isolation structures in the cell region and the periphery region to enhance the GCR of the memory device and maintain excellent electrical property is a critical issue to be solved urgently.
SUMMARY OF THE INVENTIONThe present invention is directed to a method of fabricating a flash memory to obtain high GCR and excellent electrical property.
The present invention is directed to a method of fabricating a flash memory. Firstly, a substrate including a cell region and a periphery region is provided. A plurality of isolation structures is formed on the substrate, and a first dielectric layer and a floating gate are formed on the substrate between the isolation structures. Next, a mask layer is formed on the substrate for covering the isolation structures in the periphery region and the isolation structure in the cell region and adjacent to the periphery region. Thereafter, a portion of the isolation structures in the cell region is removed by using the mask layer as a mask, so that a first height difference is present between surfaces of the isolation structures in the periphery region and a surface of the first dielectric layer. The first height difference is present between a surface of the isolation structure in the cell region and adjacent to the periphery region and the surface of the first dielectric layer. A second height difference is present between surfaces of the other isolation structures in the cell region and the surface of the first dielectric layer. Here, the first height difference is greater than the second height difference, and the surfaces of the isolation structures are higher than the surface of the first dielectric layer. Then, the mask layer is removed. Afterward, an inter-gate dielectric layer is formed on the substrate. The inter-gate dielectric layer and the floating gate in the periphery region are removed. After then, a conductive layer is formed on the substrate.
In one embodiment of the present invention, the first dielectric layer in the periphery region is removed and a second dielectric layer is formed on the substrate between the isolation structures in the periphery region after the inter-gate dielectric layer and the floating gate in the periphery region are removed.
In one embodiment of the present invention, the surfaces of the isolation structures in the periphery region are higher than a surface of the second dielectric layer. Moreover, a third height difference is present between the surfaces of the isolation structures in the periphery region and the surface of the second dielectric layer. Here, the third height difference is greater than the second height difference.
In light of the foregoing, in the method of fabricating the flash memory in the present invention, the mask layer is used to cover the periphery region for removing a portion of the isolation structures in the cell region. As a result, the height difference between the surfaces of the isolation structures in the cell region and a surface of a tunneling dielectric layer is greater than a height difference between the surfaces of the isolation structures in the periphery region and a surface of a gate dielectric layer. Hence, the contact area between the floating gate and a control gate is increased and the integrity of the gate dielectric layer in the periphery region is maintained for the flash memory to obtain high GCR and excellent electrical property.
In order to make the aforementioned and other features and advantages of the present invention more comprehensible, several embodiments accompanied with figures are described in detail below.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
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Then, a portion of the isolation structures 114 in the cell region is removed to form isolation structures 114a by using the mask layer 122 as a mask. Consequently, other than the isolation structures 114′ adjacent to the periphery region 104, surfaces 124 of the other isolation structures 114a in the cell region 102 are lower than surfaces 126 of the isolation structures 116 in the periphery region 104. In other words, surfaces 124, 125, 126 of the isolation structures 114a, 114′, 116 are higher than surfaces 109 of the tunneling dielectric layer 108. Moreover, a first height difference H1 is present between the surfaces 126 of the isolation structures 116 in the periphery region 104 and the surface 109 of the tunneling dielectric layer 108. The first height difference H1 is also present between the surface 125 of the isolation structure 114′ in the cell region 102 and adjacent to the periphery region 104 and the surfaces 109 of the tunneling dielectric layer 108. In addition, a second height difference H2 which is smaller than the first height difference H1 is present between the surfaces 124 of the other isolation structures 114a in the cell region 102 and the surfaces 109 of the tunneling dielectric layer 108.
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Next, a portion of the isolation structures 114a in the cell region 102 is removed to form isolation structures 114b by using the mask layer 122 as a mask. As a result, other than the isolation structure 114′a adjacent to the periphery region 104, surfaces 124 of the other isolation structures 114b in the cell region 102 are lower than the surfaces 126 of the isolation structures 116a in the periphery region 104. In other words, the first height difference H1 is still present between the surfaces 126 of the isolation structures 116a in the periphery region 104 and the surface 109 of the tunneling dielectric layer 108. Furthermore, the first height difference H1 is still present between the surface 125 of the isolation structure 114a′ in the cell region 102 and adjacent to the periphery region 104 and the surface 109 of the tunneling dielectric region 108. However, the second height difference H2 which is smaller than the first height difference H1 is present between the surfaces 124 of the other isolation structures 114b in the cell region 102 and the surfaces 109 of the tunneling dielectric layer 108.
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In summary, the mask layer is used to cover the periphery region and the cell region adjacent to the periphery region, so that the isolation structures in the cell region and the isolation structures in the periphery region are removed in different extents. Hence, the height difference between the surfaces of the isolation structures and the surfaces of the tunneling dielectric layer in the cell region is greater than the height difference between the surfaces of the isolation structures and the surface of the gate dielectric layer in the periphery region. In the cell region, since more isolation structures have been removed, the contact area between the floating gates and the control gate is increased, thereby enhancing the GCR. In the periphery region, since less isolation structures have been removed, the gate dielectric layer is prevented from degradation resulted from exposure, so that the memory device obtains excellent electrical property. In other words, the method of fabricating the flash memory in the present invention increases the contact area between the floating gates and the control gate and maintains the integrity of the gate dielectric layer in the periphery region, so that the flash memory obtains high GCR and excellent electrical property.
Although the present invention has been described with reference to the above embodiments, it will be apparent to one of the ordinary skill in the art that modifications to the described embodiment may be made without departing from the spirit of the invention. Accordingly, the scope of the invention will be defined by the attached claims not by the above detailed descriptions.
Claims
1. A method of fabricating a flash memory, comprising:
- providing a substrate comprising a cell region and a periphery region, wherein a plurality of isolation structures is formed on the substrate, and a first dielectric layer and a floating gate are sequentially formed on the substrate between the isolation structures;
- forming a mask layer on the substrate, the mask layer covering the isolation structures in the periphery region and the isolation structure in the cell region and adjacent to the periphery region;
- removing a portion of the isolation structures in the cell region by using the mask layer as a mask, so that a first height difference is present between surfaces of the isolation structures in the periphery region and a surface of the first dielectric layer, the first height difference is present between a surface of the isolation structure in the cell region and adjacent to the periphery region and the surface of the first dielectric layer, and a second height difference is present between surfaces of the other isolation structures in the cell region and the surface of the first dielectric layer, wherein the first height difference is greater than the second height difference and the surfaces of the isolation structures are higher than the surface of the first dielectric layer;
- removing the mask layer;
- forming an inter-gate dielectric layer on the substrate;
- removing the inter-gate dielectric layer and the floating gates in the periphery region; and
- forming a conductive layer on the substrate.
2. The method of fabricating the flash memory as claimed in claim 1, further comprising performing a blanket removal to the isolation structures after removing the mask layer.
3. The method of fabricating the flash memory as claimed in claim 2, wherein a method of the blanket removal comprises a wet etching method or a dry etching method.
4. The method of fabricating the flash memory as claimed in claim 1, further comprising performing the blanket removal to the isolation structures before forming the mask layer.
5. The method of fabricating the flash memory as claimed in claim 4, wherein a method of the blanket removal comprises the wet etching method or the dry etching method.
6. The method of fabricating the flash memory as claimed in claim 1, further comprising removing the first dielectric layer in the periphery region and forming a second dielectric layer on the substrate between the isolation structures in the periphery region after removing the inter-gate dielectric layer and the floating gates in the periphery region.
7. The method of fabricating the flash memory as claimed in claim 6, wherein the surfaces of the isolation structures in the periphery region are higher than a surface of the second dielectric layer, and a third height difference is present between the surfaces of the isolation structures in the periphery region and the surface of the second dielectric layer, wherein the third height difference is greater than the second height difference.
8. The method of fabricating the flash memory as claimed in claim 1, wherein a material of the mask layer comprises a photoresist material.
9. The method of fabricating the flash memory as claimed in claim 1, wherein a material of the isolation structures comprises silicon oxide.
10. The method of fabricating the flash memory as claimed in claim 1, wherein a material of the first dielectric layer comprises silicon oxide.
11. The method of fabricating the flash memory as claimed in claim 1, wherein a material of the second dielectric layer comprises silicon oxide.
12. The method of fabricating the flash memory as claimed in claim 1, wherein a material of the floating gates comprises doped polysilicon.
13. The method of fabricating the flash memory as claimed in claim 1, wherein a material of the inter-gate dielectric layer comprises silicon oxide/silicon nitride/silicon oxide.
14. The method of fabricating the flash memory as claimed in claim 1, wherein a material of the conductive layer comprises doped polysilicon.
6762095 | July 13, 2004 | Hsieh |
20070161187 | July 12, 2007 | Hwang et al. |
Type: Grant
Filed: Sep 2, 2009
Date of Patent: Mar 15, 2011
Assignee: Winbond Electronics Corp. (Taichung County)
Inventors: Lu-Ping Chiang (Hsinchu), Hsiu-Han Liao (Hsinchu)
Primary Examiner: Charles D Garber
Assistant Examiner: Yasser A Abdelaziez
Attorney: J.C. Patents
Application Number: 12/552,777
International Classification: H01L 21/336 (20060101);