Semiconductor package
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Description
FIG. 1 is a perspective view of a semiconductor package showing our new design;
FIG. 2 is a top plan view thereof;
FIG. 3 is a left side elevational view thereof;
FIG. 4 is a front elevational view thereof;
FIG. 5 is a bottom plan view thereof;
FIG. 6 is a right side elevational view thereof;
FIG. 7 is a rear elevational view thereof;
FIG. 8 is a perspective view of another embodiment of a semiconductor package showing our new design; and,
FIG. 9 is a front elevational view of the embodiment of FIG. 8. The rest of views of the embodiment of FIG. 8 are the same as those of the embodiment of FIG. 1.
Referenced Cited
Patent History
Patent number: D396696
Type: Grant
Filed: Jan 30, 1997
Date of Patent: Aug 4, 1998
Assignee: Sony Corporation (Tokyo)
Inventors: Yuichi Takagi (Tokyo), Kazuhiko Ueda (Tokyo)
Primary Examiner: James Gandy
Assistant Examiner: Cathron B. Matta
Law Firm: Foley & Lardner
Application Number: 0/65,264
Type: Grant
Filed: Jan 30, 1997
Date of Patent: Aug 4, 1998
Assignee: Sony Corporation (Tokyo)
Inventors: Yuichi Takagi (Tokyo), Kazuhiko Ueda (Tokyo)
Primary Examiner: James Gandy
Assistant Examiner: Cathron B. Matta
Law Firm: Foley & Lardner
Application Number: 0/65,264
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)
International Classification: 1303;
International Classification: 1303;