Substrate for a semiconductor element
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Description
FIG. 1 is a right side elevational view of a substrate for a semiconductor element, showing our new design; the opposite side being an identical image thereof;
FIG. 2 is a top plan view thereof; the opposite side being an identical image thereof;
FIG. 3 is a front elevational view thereof; and,
FIG. 4 is a rear elevational view thereof.
Claims
The ornamental design for a substrate for a semiconductor element, as shown and described.
Referenced Cited
Patent History
Patent number: D457146
Type: Grant
Filed: May 29, 2001
Date of Patent: May 14, 2002
Assignee: Kabushiki Kaisha Toshiba (Tokyo)
Inventors: Kazuhiro Yamamoto (Ninomiya-machi), Tadaharu Hashiguchi (Yokohama)
Primary Examiner: Ted Shooman
Assistant Examiner: Selina Sikder
Attorney, Agent or Law Firm: Banner & Witcoff, Ltd.
Application Number: 29/142,483
Type: Grant
Filed: May 29, 2001
Date of Patent: May 14, 2002
Assignee: Kabushiki Kaisha Toshiba (Tokyo)
Inventors: Kazuhiro Yamamoto (Ninomiya-machi), Tadaharu Hashiguchi (Yokohama)
Primary Examiner: Ted Shooman
Assistant Examiner: Selina Sikder
Attorney, Agent or Law Firm: Banner & Witcoff, Ltd.
Application Number: 29/142,483
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)
International Classification: 1303;
International Classification: 1303;