Integrated circuits substrate
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Description
FIG. 1 is a front, top and right side perspective view of an integrated circuits substrate, showing my new design;
FIG. 2 is a front elevational view thereof, the rear elevational view is omitted as that is symmetrical to the front elevational view thereof;
FIG. 3 is a top plan view thereof;
FIG. 4 is a bottom plan view thereof;
FIG. 5 is a right side elevational view thereof;
FIG. 6 is a left side elevational view thereof; and,
FIG. 7 is an enlarged cross-sectional view thereof, taken along line 7—7 of FIG. 2, with the internal system omitted.
The broken lines in all views are shown for illustrative purposes only and form no part of the claimed design.
Claims
The ornamental design for an integrated circuits substrate, as shown and described.
Referenced Cited
U.S. Patent Documents
Foreign Patent Documents
5138438 | August 11, 1992 | Masayuki et al. |
5352852 | October 4, 1994 | Chun |
5677570 | October 14, 1997 | Kondoh et al. |
5777265 | July 7, 1998 | Bhattacharyya et al. |
5824950 | October 20, 1998 | Mosley et al. |
5912808 | June 15, 1999 | Ikemoto |
D432097 | October 17, 2000 | Song et al. |
6211564 | April 3, 2001 | Hatano |
6316825 | November 13, 2001 | Park et al. |
6462408 | October 8, 2002 | Wehrly, Jr. |
11-40745 | February 1999 | JP |
Patent History
Patent number: D475981
Type: Grant
Filed: Aug 16, 2002
Date of Patent: Jun 17, 2003
Assignee: Mitsubishi Denki Kabushiki Kaisha (Tokyo)
Inventor: Kazunari Michii (Tokyo)
Primary Examiner: Ted Shooman
Assistant Examiner: Selina Sikder
Attorney, Agent or Law Firm: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
Application Number: 29/165,700
Type: Grant
Filed: Aug 16, 2002
Date of Patent: Jun 17, 2003
Assignee: Mitsubishi Denki Kabushiki Kaisha (Tokyo)
Inventor: Kazunari Michii (Tokyo)
Primary Examiner: Ted Shooman
Assistant Examiner: Selina Sikder
Attorney, Agent or Law Firm: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
Application Number: 29/165,700
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)
International Classification: 1303;
International Classification: 1303;