Grooves formed around a semiconductor device on a circuit board
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Description
The special dot-dash broken line defines the boundary of the claimed design; the gray stippling indicates the surface of the groove bed; the broken lines show unclaimed subject matter forming no part of the claimed design.
Claims
The ornamental design for grooves formed around a semiconductor device on a circuit board, as shown and described.
Referenced Cited
U.S. Patent Documents
3676748 | July 1972 | Kobayashi et al. |
D279670 | July 16, 1985 | Lukits |
D288556 | March 3, 1987 | Wallgren |
D295401 | April 26, 1988 | Klees |
5008614 | April 16, 1991 | Shreeve et al. |
D318271 | July 16, 1991 | Hasegawa et al. |
D319629 | September 3, 1991 | Hasegawa et al. |
D374541 | October 15, 1996 | Garza |
5969590 | October 19, 1999 | Gutierrez |
6114937 | September 5, 2000 | Burghartz et al. |
D487430 | March 9, 2004 | Asaka et al. |
D510103 | September 27, 2005 | Allard et al. |
Patent History
Patent number: D577691
Type: Grant
Filed: Feb 19, 2008
Date of Patent: Sep 30, 2008
Assignee: Nitto Denko Corporation (Osaka)
Inventors: Tetsuya Ohsawa (Ibaraki), Emiko Tani (Ibaraki)
Primary Examiner: Daniel Bui
Assistant Examiner: Thomas J Johannes
Attorney: Osha • Liang LLP
Application Number: 29/303,833
Type: Grant
Filed: Feb 19, 2008
Date of Patent: Sep 30, 2008
Assignee: Nitto Denko Corporation (Osaka)
Inventors: Tetsuya Ohsawa (Ibaraki), Emiko Tani (Ibaraki)
Primary Examiner: Daniel Bui
Assistant Examiner: Thomas J Johannes
Attorney: Osha • Liang LLP
Application Number: 29/303,833
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)