Process tube for manufacturing semiconductor wafers

- Tokyo Electron Limited
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Description

FIG. 1 is a front view of the design for a process tube for manufacturing semiconductor wafers in accordance with the invention;

FIG. 2 is a rear view thereof;

FIG. 3 is a right side view thereof;

FIG. 4 is a left side view thereof;

FIG. 5 is a top view thereof;

FIG. 6 is a bottom view thereof;

FIG. 7 is a sectional view thereof along line 7—7 of FIG. 5;

FIG. 8 is a sectional view thereof along line 8—8 of FIG. 5;

FIG. 9 is a sectional view thereof along line 9—9 of FIG. 1; and,

FIG. 10 is a front, perspective view thereof.

In the preferred embodiment, the entire body of the process tube is transparent such that the inside of the tube can be seen. Dash lines show the boundary of the claimed design.

The broken lines define portions of the process tube that form no part of the claimed design.

Claims

The ornamental design for a process tube for manufacturing semiconductor wafers, as shown and described.

Referenced Cited
U.S. Patent Documents
5618349 April 8, 1997 Yuuki
D404368 January 19, 1999 Shimazu
D405062 February 2, 1999 Shimazu
D406113 February 23, 1999 Hanagata et al.
5948300 September 7, 1999 Gero et al.
6251189 June 26, 2001 Odake et al.
6538237 March 25, 2003 Yang et al.
D520467 May 9, 2006 Ishii et al.
D521464 May 23, 2006 Ishii et al.
20020014483 February 7, 2002 Suzuki et al.
Patent History
Patent number: D586768
Type: Grant
Filed: Apr 11, 2007
Date of Patent: Feb 17, 2009
Assignee: Tokyo Electron Limited (Tokyo)
Inventors: Hisashi Inoue (Tokyo), Atsushi Endo (Tokyo)
Primary Examiner: Selina Sikder
Attorney: Smith, Gambrell & Russell, LLP
Application Number: 29/274,293