Top contact layout board in an electrical system
Latest Celadon Systems, Inc. Patents:
Description
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Claims
The ornamental design for a top contact layout board in an electrical system, as shown and described.
Referenced Cited
U.S. Patent Documents
D225434 | December 1972 | Cleeland |
3795845 | March 1974 | Cass et al. |
4495377 | January 22, 1985 | Johnson et al. |
D320361 | October 1, 1991 | Karasawa |
5091822 | February 25, 1992 | Takashima |
5210682 | May 11, 1993 | Takashima |
5491364 | February 13, 1996 | Brandenburg et al. |
6160716 | December 12, 2000 | Perino et al. |
6310398 | October 30, 2001 | Katz |
6556454 | April 29, 2003 | D'Amato et al. |
6664620 | December 16, 2003 | Siu et al. |
6793500 | September 21, 2004 | Budell et al. |
D552048 | October 2, 2007 | He |
7808110 | October 5, 2010 | Wang et al. |
20020060318 | May 23, 2002 | Katz |
Patent History
Patent number: D639757
Type: Grant
Filed: Aug 16, 2010
Date of Patent: Jun 14, 2011
Assignee: Celadon Systems, Inc. (Apple Valley, MN)
Inventors: Bryan J. Root (Apple Valley, MN), William A. Funk (Eagan, MN)
Primary Examiner: Selina Sikder
Attorney: Hamre, Schumann, Mueller & Larson, P.C.
Application Number: 29/367,935
Type: Grant
Filed: Aug 16, 2010
Date of Patent: Jun 14, 2011
Assignee: Celadon Systems, Inc. (Apple Valley, MN)
Inventors: Bryan J. Root (Apple Valley, MN), William A. Funk (Eagan, MN)
Primary Examiner: Selina Sikder
Attorney: Hamre, Schumann, Mueller & Larson, P.C.
Application Number: 29/367,935
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)