Tip for integrated circuit test pin

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Description

FIG. 1 is a front and rear (the pin is symmetric front to back) plan view of the tip with the remaining portion of the pin shown in broken lines.

FIG. 2 is a front/side perspective view thereof.

FIG. 3 is a top plan view thereof.

FIG. 4 is a side plan view thereof.

FIG. 5 is the other side view thereof.

FIG. 6 is a bottom plan view thereof.

FIG. 7 is a bottom front perspective view thereof.

FIG. 8 is a bottom rear perspective view thereof.

FIG. 9 is rear plan view thereof.

FIG. 10 is a rear perspective view thereof.

FIG. 11 is a top front perspective partial view of the tip portion only.

FIG. 12 is a front plan view of an alternate embodiment thereof.

FIG. 13 is a perspective view of an alternate embodiment thereof.

FIG. 14 is top plan view of an alternate embodiment thereof.

FIG. 15 is a side plan view of an alternate embodiment thereof.

FIG. 16 is the other side plan view of an alternate embodiment thereof.

FIG. 17 is a bottom plan view of an alternate embodiment thereof.

FIG. 18 is a front perspective view of an alternate embodiment thereof.

FIG. 19 is a bottom perspective view of an alternate embodiment of the other side thereof.

FIG. 20 is a close up partial top perspective view of the alternate embodiment thereof.

FIG. 21 is a front plan view thereof; and,

FIG. 22 is a bottom perspective view thereof.

The features shown in broken line depict environmental subject matter only and form no part of the claimed design.

Claims

The ornamental design for a tip for integrated circuit test pin, as shown and described.

Referenced Cited
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Patent History
Patent number: D942290
Type: Grant
Filed: Jul 12, 2019
Date of Patent: Feb 1, 2022
Assignee: JOHNSTECH INTERNATIONAL CORPORATION (Minneapolis, MN)
Inventor: John Nelson (Brooklyn Park, MN)
Primary Examiner: Antoine Duval Davis
Application Number: 29/697,992