Semiconductor device

- Panasonic
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Description

FIG. 1 is a perspective view of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a front view thereof;

FIG. 3 is a rear view thereof;

FIG. 4 is a left side view thereof;

FIG. 5 is a right side view thereof;

FIG. 6 is a top view thereof;

FIG. 7 is a bottom view thereof;

FIG. 8 is a cross sectional view thereof taken along line 8-8;

FIG. 9 is a perspective view of a semiconductor device according to a second embodiment of the present invention;

FIG. 10 is a front view thereof;

FIG. 11 is a rear view thereof;

FIG. 12 is a left side view thereof,

FIG. 13 is a right side view thereof;

FIG. 14 is a top view thereof;

FIG. 15 is a bottom view thereof;

FIG. 16 is a cross sectional view thereof taken along line 16-16;

FIG. 17 is a perspective view of a semiconductor device according to a third embodiment of the present invention;

FIG. 18 is a front view thereof;

FIG. 19 is a rear view thereof;

FIG. 20 is a left side view thereof;

FIG. 21 is a right side view thereof;

FIG. 22 is a top view thereof;

FIG. 23 is a bottom view thereof; and,

FIG. 24 is a cross sectional view thereof taken along line 26-26.

The dash-dash broken lines in the drawings are for the purpose of illustrating portions of the article that form no part of the claimed design. The dash-dot broken lines in the drawings are for the purpose of illustrating a boundary and form no part of the claimed design.

Claims

We claim the ornamental design for a semiconductor device, as shown and described.

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Patent History
Patent number: D986840
Type: Grant
Filed: Nov 11, 2020
Date of Patent: May 23, 2023
Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD. (Osaka)
Inventors: Toshifumi Ishida (Osaka), Kensuke Takahashi (Hyogo)
Primary Examiner: Christy Nemeth
Assistant Examiner: Leah E Hoeferkamp
Application Number: 29/758,000