Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices
A method for fabricating a low resistance, low inductance device for high current semiconductor flip-chip products. A structure is produced, which comprises a semiconductor chip with metallization traces, copper lines in contact with the traces, and copper bumps located in an orderly and repetitive arrangement on each line so that the bumps of one line are positioned about midway between the corresponding bumps of the neighboring lines. A substrate is provided which has elongated copper leads with first and second surfaces, the leads oriented at right angles to the lines. The first surface of each lead is connected to the corresponding bumps of alternating lines using solder elements. Finally, the assembly is encapsulated in molding compound so that the second lead surfaces remain un-encapsulated.
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This application is an application for the reissue of U.S. Pat. No. 7,335,536; moreover, more than one reissue patent application has been filed for the reissue of U.S. Pat. No. 7,335,536, which includes reissue application Ser. No. 13/870,579, filed on Aug. 20, 2013, which is a divisional of this pending reissue application, and also continuation reissue application Ser. No. 14/023,281, filed on Sep. 10, 2013, which claims priority to the present reissue.
FIELD OF THE INVENTIONThe present invention is related in general to the field of semiconductor devices and processes and more specifically to a fabrication method of high performance flip-chip semiconductor devices, which have low electrical resistance and can provide high power, low noise, and high speed.
DESCRIPTION OF THE RELATED ARTAmong the ongoing trends in integrated circuit (IC) technology are the drives towards higher integration, shrinking component feature sizes, and higher speed. In addition, there is the relentless pressure to keep the cost/performance ratio under control, which translates often into the drive for lower cost solutions. Higher levels of integration include the need for higher numbers of signal lines and power lines, yet smaller feature sizes make it more and more difficult to preserve clean signals without mutual interference.
These trends and requirements do not only dominate the semiconductor chips, which incorporate the ICs, but also the packages, which house and protect the IC chips.
Compared to the traditional wire bonding assembly, the growing popularity of flip-chip assembly in the fabrication process flow of silicon integrated circuit (IC) devices is driven by several facts. First, the electrical performance of the semiconductor devices can commonly be improved when the parasitic inductances correlated with conventional wire bonding interconnection techniques are reduced. Second, flip-chip assembly often provides higher interconnection densities between chip and package than wire bonding. Third, in many designs flip-chip assembly consumes less silicon “real estate” than wire bonding, and thus helps to conserve silicon area and reduce device cost. And fourth, the fabrication cost can often be reduced, when concurrent gang-bonding techniques are employed rather than consecutive individual bonding steps.
The standard method of ball bonding in the fabrication process uses solder balls and their reflow technique. These interconnection approaches are more expensive than wire bonding. In addition, there are severe reliability problems in some stress and life tests of solder ball attached devices. Product managers demand the higher performance of flip-chip assembled products, but they also demand the lower cost and higher reliability of wire bonded devices. Furthermore, the higher performance of flip-chip assembled products should be continued even in miniaturized devices, which at present run into severe technical difficulties by using conventional solder ball technologies.
SUMMARY OF THE INVENTIONApplicants recognize a need to develop a technical approach which considers the complete system consisting of semiconductor chip—device package—external board, in order to provide superior product characteristics, including low electrical resistance and inductance, high reliability, and low cost. Minimum inductance and noise is the prerequisite of high speed, and reduced resistance is the prerequisite of high power. The system-wide method of assembling should also provide mechanical stability and high product reliability, especially in accelerated stress tests (temperature cycling, drop test, etc.). The fabrication method should be flexible enough to be applied for semiconductor product families with shrinking geometries, including substrates and boards, and a wide spectrum of design and process variations.
One embodiment of the invention is a method for fabricating a low resistance, low inductance interconnection structure for high current semiconductor flip-chip products. A semiconductor wafer is provided, which has metallization traces, the wafer surface protected by an overcoat, and windows in the overcoat to expose portions of the metallization traces. Copper lines are formed on the overcoat, preferably by electroplating; the lines are in contact with the traces by filling the windows with metal. Next a layer of photo-imageable insulation material is deposited over the lines and the remaining wafer surface. Windows are opened in the insulation material to expose portions of the lines, the locations of the windows selected in an orderly and repetitive arrangement on each line so that the windows of one line are positioned about midway between the corresponding windows of the neighboring lines. Copper bumps are formed, preferably by electroplating, in the windows, and are in contact with the lines.
Certain device features serve multiple purposes in the process flow. The photo-imageable insulation layer doubles as protection against running solder in the assembly process. The photoresist layers needed to enable the electroplating steps double as thickness controls for the copper elements being electroplated.
Another embodiment of the invention is a method for fabricating a low resistance, low inductance device for high current semiconductor flip-chip products. A structure is provided, which comprises a semiconductor chip with metallization traces, copper lines in contact with the traces, and copper bumps located in an orderly and repetitive arrangement on each line so that the bumps of one line are positioned about midway between the corresponding bumps of the neighboring lines. Further, a substrate is provided which has elongated copper leads with first and second surfaces, the leads oriented at right angles to the lines. The first surface of each lead is connected to the corresponding bumps of alternating lines using solder elements. Finally, the assembly is encapsulated in molding compound so that the second lead surfaces remain un-encapsulated.
Another embodiment of the invention is a method for fabricating a low resistance, low inductance interconnection system for high current semiconductor flip-chip devices. An encapsulated device as described above is provided, with lead surfaces un-encapsulated. Further a circuit board is provided, which has copper contact pads parallel to the leads. The device lead surfaces are attached to the board pads using solder layers.
The technical advantages represented by certain embodiments of the invention will become apparent from the following description of the preferred embodiments of the invention, when considered in conjunction with the accompanying drawings and the novel features set forth in the appended claims.
The present invention is related to U.S. patent application Ser. No. 11/210,066, filed on Aug. 22, 2005. (Coyle et al., “High Current Semiconductor Device System having Low Resistance and Inductance”; TI-60885).
A window of width 104 is opened in overcoat 103 to expose a portion of metallization trace 102. The top view of
As
In
In the next process steps shown in
In
The locations of the windows 702a are selected in an orderly and repetitive arrangement on each line 501 so that the windows 702a of one line 501 are positioned about midway between the corresponding windows of the neighboring lines.
As
In
In the next process steps shown in
The next process step is a singulation step, preferably involving a rotating diamond saw, by which the wafer is separated into individual chips. Each chip can then be further processed by assembling the chip onto a substrate or a leadframe.
In the next process step, a substrate is provided, which has elongated copper leads with first and second surfaces. A preferred example is a metallic leadframe with individual leads; preferred leadframe metals are copper or copper alloys, but in specific devices, iron/nickel alloys or aluminum may be used. Other examples include insulating substrates with elongated copper leads. The leads are oriented at right angles to the copper lines 501 shown in
In
Flipping the assembly of
The assembly of
From lead surface 1410b to the chip circuitry, there is a continuous electrical path through copper connectors (with the exception of solder element 1420). Consequently, the electrical resistance and the electrical inductance of the device displayed in
While this invention has been described in reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. As an example, the substrate may be an insulating tape with copper leads of first and second surfaces. As another example, the copper bumps may be considerably shorter than illustrated in the figures; there still will be no risk of electrical shorts by creeping solder elements. It is therefore intended that the appended claims encompass any such modifications.
Claims
1. A method for fabricating a low resistance, low inductance interconnection structure for high current semiconductor flip-chip products, comprising the steps of:
- providing a semiconductor wafer having metallization traces, the wafer surface protected by an overcoat, and windows in the overcoat, to expose portions of the metallization traces;
- forming copper lines on the overcoat,;
- contacting the metallization traces by filling the windows with metal;
- depositing a layer of photo-imageable insulation material over the copper lines and the remaining wafer surface;
- opening windows in the photo-imageable insulation material to expose portions of the copper lines, the locations of the windows selected in an orderly and repetitive arrangement on each copper line so that the windows of one line are positioned about midway between the corresponding windows of the neighboring lines; and
- forming copper bumps in the windows, in contact with the lines.
2. The method according to claim 1 further comprising the step of depositing a cap of solderable metal layers on each bump.
3. The method according to claim 1 wherein the number and locations of the windows in the overcoat are selected as needed for the devices employing the metallization traces.
4. The method according to claim 1 wherein the copper lines are oriented parallel to the metallization traces.
5. The method according to claim 1 wherein the copper lines are oriented at right angles to the metallization traces.
6. The method according to claim 1 wherein the step of forming copper lines comprises the steps of:
- depositing a barrier metal layer over the wafer surface;
- depositing a seed metal layer over the barrier metal layer;
- depositing a first photoresist layer over the seed metal layer in a height commensurate with the height of intended copper lines;
- opening windows in the first photoresist layer so that the windows are shaped as the intended lines;
- depositing copper to fill the photoresist windows and form copper lines;
- removing the first photoresist layer; and
- removing the portions of the adhesion and barrier layers, which are exposed after removing the first photoresist layer.
7. The method according to claim 6, wherein the step of depositing copper comprises an electroplating technique.
8. The method according to claim 1 wherein the step of forming copper bumps comprises the steps of:
- depositing a barrier metal layer over the wafer surface;
- depositing a seed metal layer over the barrier metal layer;
- depositing a second photoresist layer over the seed metal layer in a height commensurate with the height of the intended copper bumps;
- opening windows in the second photoresist layer in locations intended for copper bumps, and of a width commensurate with the width of the intended copper bumps;
- filling the photoresist windows by depositing copper to form copper bumps;
- removing the second photoresist layer; and
- removing the portions of the adhesion and barrier layers, which are exposed after removing the second photoresist layer.
9. The method according the step to claim 8, wherein the step of depositing copper comprises an electroplating technique.
10. The method according to claim 8 further comprising the step of:
- depositing one or more solderable metal layers on the surface of the copper bump bumps, before removing the second photoresist layer.
11. The method according to claim 10 wherein said solderable metal layers include a layer of nickel on the copper surface, followed by a layer of palladium on the nickel layer.
12. A method for fabricating a low resistance, low inductance interconnection device for high current semiconductor flip-chip products, comprising the steps of:
- providing a structure comprising a semiconductor chip having metallization traces, copper lines in contact with the traces, and copper bumps located in an orderly and repetitive arrangement on each copper line so that the copper bumps of one copper line are positioned about midway between the corresponding copper bumps of the neighboring copper lines;
- providing a substrate having elongated copper leads with first and second surfaces, the leads oriented at right angles to the copper lines;
- connecting the first surface of each copper lead to the corresponding copper bumps of alternating copper lines using solder elements; and
- at least partially encapsulating the assembly in molding compound so that the second lead surfaces remain un-encapsulated.
13. The method according to claim 12 wherein the substrate is a leadframe including copper.
14. A method for fabricating a low resistance, low inductance interconnection system for high current semiconductor flip-chip devices, comprising the steps of:
- providing a low resistance, low inductance interconnection device comprising: a semiconductor chip structure including copper lines in contact with chip metallization traces, and copper bumps located in an orderly and repetitive arrangement on each copper line, the copper bumps of one copper line positioned about midway between the corresponding copper bumps of the neighboring copper lines; a substrate having elongated copper leads with first and second surfaces, the copper leads at right angles to the copper lines, the first lead surfaces connected to the corresponding copper bumps of alternating copper lines by solder elements; and the chip structure and substrate at least partially encapsulated so that the second lead surfaces remain un-encapsulated;
- providing a circuit board having copper contact pads parallel to the copper leads; and
- attaching the second surface of the device leads to the board pads using solder layers.
15. A method comprising:
- providing a structure having: a semiconductor chip having metallization traces; copper lines in electrical contact with the traces; and copper bumps located in an orderly and repetitive arrangement on each line so that the bumps of one line are positioned about midway between the corresponding bumps of the neighboring lines;
- providing a substrate having elongated copper leads with first and second surfaces, each lead oriented at an angle to the lines;
- connecting the first surface of each lead to the corresponding bumps of alternating lines using solder elements; and
- encapsulating portions of the structure and the substrate using an encapsulation process that encapsulates a plurality of assembled structure and substrate units.
16. A packaged integrated circuit (IC) product comprising:
- a plurality of metallization traces formed on a first substrate, wherein the metallization traces are generally in parallel to one another;
- a plurality of conductive lines formed on the first substrate, wherein each conductive lines is in contact with and is at least partially coextensive with at least one of the metallization traces;
- a plurality of conductive bumps formed on each of the conductive lines, wherein the conductive bumps for each line are arranged in an orderly and repetitive pattern such that each conductive bump is positioned about midway between the corresponding conductive bumps of each of its neighboring conductive lines;
- a plurality of leads formed on a second substrate, wherein each lead is electrically connected to corresponding conductive bumps from alternating conductive lines on the first substrate, wherein each lead is oriented at an angle to each conductive line, and wherein each lead includes a second surface that is opposite the first surface; and
- an encapsulation layer covering portions of the first substrate and second substrate.
17. The packaged IC product according to claim 16 wherein the conductive lines, the conductive bumps, and the leads further comprise copper.
18. The packaged IC product according to claim 17, wherein the angle is a right angle.
19. The packaged IC product according to claim 18 further comprising a solderable metal layer formed on the surface of the copper bump.
20. The packaged IC product according to claim 19 wherein the solderable metal layer includes a layer of nickel on the copper surface, followed by a layer of palladium on the nickel layer.
21. The packaged IC product according to claim 20 wherein the first substrate is a semiconductor wafer.
22. The packaged IC product according to claim 21 wherein the second substrate is a leadframe.
23. The packaged IC product according to claim 16, wherein the second surface of each of the leads is exposed following the formation of the encapsulation layer.
24. The method according to claim 12 wherein the copper lines further comprise top and bottom surfaces, and wherein the bottom surfaces are in contact with the traces, and wherein the step of providing the structure further comprises the step of providing an insulating layer that overlies the semiconductor chip between the copper lines and at least extends between the top and bottom surfaces of the copper lines.
25. The method according to claim 24 wherein the insulating layer has a thickness between approximately 10 and 20 μm.
26. The method according to claim 24 wherein the insulating layer further comprises a first insulating layer, and wherein the step of providing the structure further comprises providing a second insulating layer formed over at least a portion of the top surfaces of the copper lines.
27. The method according to claim 26 wherein the first insulating layer has a thickness between approximately 10 and 20 μm.
28. A method for fabricating a semiconductor flip-chip product, comprising the steps of:
- providing a semiconductor chip having metallization traces, copper lines connected to the traces, and plated copper bump structures located in an orderly and repetitive arrangement on each copper line;
- providing an insulating layer that overlies the semiconductor chip and extends between the top and bottom surfaces of the copper lines and over at least a portion of the top surface of the copper lines;
- providing a substrate having elongated copper leads with first and second surfaces;
- electrically coupling the first surface of each copper lead to corresponding ones of the plated copper bump structures using solder elements;
- at least partially encapsulating the semiconductor chip and the substrate; and
- providing un-encapsulated portions of the second lead surfaces for further electrical attachment.
29. The method of claim 28 wherein the substrate comprises a metallic leadframe.
30. The method of claim 28 wherein the insulating layer is at least 10 μm thick.
5083187 | January 21, 1992 | Lamson et al. |
5087590 | February 11, 1992 | Fujimoto |
6169329 | January 2, 2001 | Farnsworth et al. |
6297460 | October 2, 2001 | Schaper |
6303997 | October 16, 2001 | Lee |
6388200 | May 14, 2002 | Schaper |
6407462 | June 18, 2002 | Banouvong et al. |
6489688 | December 3, 2002 | Baumann et al. |
6510976 | January 28, 2003 | Hwee et al. |
6550666 | April 22, 2003 | Chew |
6650012 | November 18, 2003 | Takahashi |
6686666 | February 3, 2004 | Bodas |
6759738 | July 6, 2004 | Fallon et al. |
6762507 | July 13, 2004 | Cheng et al. |
6768210 | July 27, 2004 | Zuniga-Ortiz et al. |
6790758 | September 14, 2004 | Hsieh |
6798075 | September 28, 2004 | Liaw et al. |
6977435 | December 20, 2005 | Kim et al. |
7049642 | May 23, 2006 | Shinjo |
7101781 | September 5, 2006 | Ho |
7122897 | October 17, 2006 | Aiba et al. |
7127807 | October 31, 2006 | Yamaguchi |
7385286 | June 10, 2008 | Iwaki |
7465654 | December 16, 2008 | Chou |
7763977 | July 27, 2010 | Yamano |
8039956 | October 18, 2011 | Coyle et al. |
20020084534 | July 4, 2002 | Paek |
20040089946 | May 13, 2004 | Wen |
20070040237 | February 22, 2007 | Coyle et al. |
20070130554 | June 7, 2007 | Caruba |
20080023819 | January 31, 2008 | Chia |
1189279 | March 2001 | EP |
EP 0061863 | October 1982 | JP |
WO2007024587 | March 2007 | WO |
WO2007027994 | March 2007 | WO |
- Detailed Structural Analysis I of the Intel Pentium 3.0E GHz Processor “Prescott,” Seminconductor Insights Inc.. Mar. 2004, pp, 1-26.
- “Intel Prescott Package, Die Connection Layer,” UBM TechInsights, Aug. 4, 2011, pp. 1-5.
- “Intel BX80545PG2800E Pentium® 4 Prescott Microprocessor Structural Analysis,” Inside Technology, Chipworks, Apr. 1, 2005, www.chipworks.com, pp. 1-8.
- 8039956 File History—11210066.pdf.
- EP1932173 File History—06814056.pdf.
- EP1938382 File History.pdf.
- PCT/US2006/031933 Search Report (WO2007024587).
- “Multichip Assembly With Flipped Integrated Circuits,” IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. 12, No. 4, December 1989 (Heinen, et al.).
Type: Grant
Filed: Feb 25, 2010
Date of Patent: Jul 4, 2017
Assignee: TEXAS INSTRUMENTS INCORPORATED (Dallas, TX)
Inventors: Bernhard P. Lange (Freising), Anthony L. Coyle (Allen, TX), Quang X. Mai (Sugarland, TX)
Primary Examiner: Anjan Deb
Application Number: 12/712,934
International Classification: H01L 21/82 (20060101); H01L 21/44 (20060101); H01L 23/532 (20060101); H01L 23/00 (20060101); H01L 23/528 (20060101); H01L 23/31 (20060101);