Data security method and device for computer modules
A security method for an attached computer module in a computer system. The security method reads a security identification number in an attached computer module and compares it to a security identification number in a console, which houses the attached computer module. Based upon a relationship between these numbers, a security status is selected. The security status determines the security level of operating the computer system.
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Notice: More than one reissue application has been filed for the reissue of U.S. Pat. No. 6,643,777. The reissue applications are U.S. application Ser. No. 11/056,604 (a parent reissue application), application Ser. No. 11/545,056 (which is a reissue continuation of the parent reissue application), application Ser. No. 12/561,138 (which is a reissue continuation of the parent reissue application), application Ser. No. 13/294,108 (which is a reissue continuation of U.S. application Ser. No. 12/561,138), application Ser. No. 13/562,210; (which is a reissue continuation of U.S. application Ser. No. 13/294,108); application Ser. No. 13/649,078 (which is a reissue continuation of U.S. application Ser. 13/562,210); application Ser. No. 13/899,484, which is a reissue continuation of U.S. application Ser. No. 13/562,210); application Ser. No. 14/087,640 (the present application, which is a reissue continuation of U.S. application Ser. No. 13/899,484); and application Ser. No. 14/109,749, which is a reissue continuation of the present application.
This application is a reissue continuation of U.S. application Ser. No. 13/899,484, which is a reissue continuation of U.S. application Ser. No. 13/562,210, which is a reissue continuation of U.S. application Ser. No. 13/294,108, which is a reissue continuation of U.S. application Ser. No. 12/561,138, which is a reissue continuation of U.S. application Ser. No. 11/545,056, which is a reissue continuation of U.S. application Ser. No. 11/056,604, which is a reissue of U.S. Pat. No. 6,643,777, which are incorporated herein by reference.
BACKGROUND OF THE INVENTIONThe present invention relates to computing devices. More particularly, the present invention provides a method and device for securing a personal computer or set-top box. Merely by way of example, the present invention is applied to a modular computing environment for desk top computers, but it will be recognized that the invention has a much wider range of applicability. It can be applied to other portable or modular computing applications.
Many desktop or personal computers, which are commonly termed PCs, have been around and used for over ten years. The PCs often come with state-of-art microprocessors such as the Intel Pentium™ microprocessor chips. They also include a hard or fixed disk drive including memory in the giga-byte range. Additionally, the PCs often include a random access memory integrated circuit device such as a dynamic random access memory device, which is commonly termed DRAM. The DRAM devices now provide up to millions of memory cells (i.e., mega-bit) on a single slice of silicon. PCs also include a high resolution display such as cathode ray tubes or CRTs. In most cases, the CRTs are at least 15 inches or 17 inches or 19 inches in diameter. High resolution flat panel displays are also used with PCs.
Many external or peripheral devices can be used with the PCs. Among others, these peripheral devices include mass storage devices such as a Zip™ Drive product sold by Iomega Corporation of Utah. Other storage devices include external hard drives, tape drives, and others. Additional devices include communication devices such as a modem, which can be used to link the PC to a wide area network of computers such as the Internet. Furthermore, the PC can include output devices such as a printer and other output means. Moreover, the PC can include special audio output devices such as speakers the like.
PCs also have easy to use keyboards, mouse input devices, and the like. The keyboard is generally configured similar to a typewriter format. The keyboard also has the length and width for easily inputting information by way of keys to the computer. The mouse also has a sufficient size and shape to easily move a cursor on the display from one location to another location.
Other types of computing devices include portable computing devices such as “laptop” computers and the like. Although somewhat successful, laptop computers have many limitations. These computing devices have expensive display technology. In fact, these devices often have a smaller flat panel display that has poor viewing characteristics. Additionally, these devices also have poor input devices such as smaller keyboards and the like. Furthermore, these devices have limited common platforms to transfer information to and from these devices and other devices such as PCs.
Up to now, there has been little common ground between these platforms including the PCs and laptops in terms of upgrading, ease-of-use, cost, performance, and the like. Many differences between these platforms, probably somewhat intentional, has benefited computer manufacturers at the cost of consumers. A drawback to having two separate computers is that the user must often purchase both the desktop and laptop to have “total” computing power, where the desktop serves as a “regular” computer and the laptop serves as a “portable” computer. Purchasing both computers is often costly and runs “thousands” of dollars. The user also wastes a significant amount of time transferring software and data between the two types of computers. For example, the user must often couple the portable computer to a local area network (i.e., LAN), to a serial port with a modem and then manually transfer over files and data between the desktop and the portable computer. Alternatively, the user often must use floppy disks to “zip” up files and programs that exceed the storage capacity of conventional floppy disks, and transfer the floppy disk data manually.
Another drawback with the current model of separate portable and desktop computer is that the user has to spend money to buy components and peripherals the are duplicated in at least one of these computers. For example, both the desktop and portable computers typically include hard disk drives, floppy drives, CD-ROMs, computer memory, host processors, graphics accelerators, and the like. Because program software and supporting programs generally must be installed upon both hard drives in order for the user to operate programs on the road and in the office, hard disk space is often wasted.
One approach to reduce some of these drawbacks has been the use of a docking station with a portable computer. Here, the user has the portable computer for “on the road” use and a docking station that houses the portable computer for office use. The docking station typically includes a separate monitor, keyboard, mouse, and the like and is generally incompatible with other desktop PCs. The docking station is also generally not compatible with portable computers of other vendors. Another drawback to this approach is that the portable computer typically has lower performance and functionality than a conventional desktop PC. For example, the processor of the portable is typically much slower than processors in dedicated desktop computers, because of power consumption and heat dissipation concerns. As an example, it is noted that at the time of drafting of the present application, some top-of-the-line desktops include 400 MHz processors, whereas top-of-the-line notebook computers include 266 MHz processors.
Another drawback to the docking station approach is that the typical cost of portable computers with docking stations can approach the cost of having a separate portable computer and a separate desktop computer. Further, as noted above, because different vendors of portable computers have proprietary docking stations, computer users are held captive by their investments and must rely upon the particular computer vendor for future upgrades, support, and the like.
To date, most personal computers provide data file security through software only. A wide variety of removable storage media are available for a personal computer. These removable media do not provide any access security protection in hardware. Data encryption program often must be used for protection. Such program is cumbersome to handle for the user requiring extra cost and time. Data encryption is more commonly used for communication over an unprotected network or the Internet. Having a large number of frequently used files managed by encryption software is not practical. Without software security program, any file can be read and copied illegally from a hard disk drive on a PC or any removable media.
PC architecture generally allows freedom of data flow between memory and peripheral devices within the allowed memory and I/O address spaces. In conventional PC architecture, a peripheral bus, i.e. PCI bus, is used to control all data transactions among peripheral devices. PCI bus allows any device to be a bus master and perform data transaction with another device. Also when a software program is in control, it can move data between any two devices. There is no hardware or protocol security mechanism on a standard peripheral bus such as PCI Bus to detect or block data transactions. Operating system may have individual files read or write protected. These types of special security feature require significant additional user interaction to control. This is too cumbersome for a typical user to manage. There is no mechanism in current PCs to allow access to the primary hard disk drive and yet prevent copying of its content. The conventional PC is a single machine that does not have a mechanism to perform security ID matching in hardware.
Thus, what is needed are computer systems that provide improved security features to prevent illegal or unauthorized access to information.
SUMMARY OF THE INVENTIONAccording to the present invention, a technique including a method and device for securing a computer module in a computer system is provided. In an exemplary embodiment, the present invention provides a security system for an attached computer module (“ACM”). In an embodiment, the ACM inserts into a computer module bay (CMB) within a peripheral console to form a functional computer. A security program reads an identification number in a security memory device to determine a security level of the ACM according to one embodiment.
In a specific embodiment, the present invention provides a system for secured information transactions. The system has a console (e.g., computer housing) comprising a peripheral controller housed in the console; and a security memory device (e.g., flash memory device) coupled to the peripheral controller. The system also has an attached computer module (i.e., a removable module with memory and microprocessor) coupled to the console. The attached computer module has a host interface controller housed within the attached computer module to interface to the security memory device through the peripheral controller.
In an alternative embodiment, the present invention provides a security protection method for a computer module. The method includes steps or acts of inserting the computer module into a console. Once the module has been inserted, the method initiates a security program in the module to read a security identification of the console and to read a security identification of the computer module. Based upon a relationship of the console identification and the computer module identification, a predetermined security status is determined from, for example, a look up table or the like. The method then selects the predetermined security status, which can be one of many. The method then operates the computer module based upon the security status.
In a further alternative embodiment, the present invention provides a method for identifying a user for a computer module. The method includes inserting a computer module into a console; and initiating a security program in memory of the computer module. The method prompts a plurality of input fields corresponding to respective input information on a user interface to be provided by a user of the computer module. Next, the method inputs the input information into the user interface of the computer module. The input information includes a user (e.g., owner) name, a user (e.g., owner) password, a business name, a business password, and a location.
Still further, the present invention provides a system for secured information transactions, e.g., data security, electronic commerce, private communications. The system includes a console comprising a peripheral controller housed in the console. A user identification input device (e.g., keyboard, retinal reader, finger print reader, voice recognition unit) is coupled to the peripheral controller. The user identification input device is provided for user identification data of the user. The system has an attached computer module coupled to the console. The attached computer module has a security memory device (e.g., flash memory device) stored with the user identification data.
Numerous benefits are achieved using the present invention over previously existing techniques. The present invention provides mechanical and electrical security systems to prevent theft or unauthorized use of the computer system in a specific embodiment. Additionally, the present invention substantially prevents accidental removal of the ACM from the console. In some embodiments, the present invention prevents illegal or unauthorized use during transit. The present invention is also implemented using conventional technologies that can be provided in the present computer system in an easy and efficient manner. Depending upon the embodiment, one or more of these benefits can be available. These and other advantages or benefits are described throughout the present specification and are described more particularly below.
These and other embodiments of the present invention, as well as its advantages and features, are described in more detail in conjunction with the text below and attached FIGS.
FIG. 9 depicts a peripheral console configuration.
FIG. 10 is a block diagram of one embodiment of a computer system employing the present invention.
FIG. 11 is a block diagram of an attached computing module (ACM).
FIG. 12 is a block diagram of a peripheral console (PCON).
FIG. 13 is a block diagram of one embodiment of a computer system using the interface of the present invention.
FIG. 14 is a detailed block diagram of one embodiment of the host interface controller of the present invention.
FIG. 15 is a detailed block diagram of one embodiment of the PIC of the present invention.
FIG. 16 is a schematic diagram of the signal lines PCK, PD0 to PD3, and PCN.
FIG. 17 is a partial block diagram of a computer system using the interface of the present invention as a bridge between the north and south bridges of the computer system.
FIG. 18 is a partial block diagram of a computer system in which the north and south bridges are integrated with the host and peripheral interface controllers, respectively.
FIG. 19 shows an attached computer module with Integrated CPU/NB/Graphics and Integrated HIC/SB.
FIG. 20 shows an attached computer module with single chip fully integrated: CPU, Cache, Core Logic, Graphics controller and Interface controller.
FIGS. 21 and 22 are tables including the pin number, symbol, signal, standard and description for the pins on the peripheral and video connectors, respectively.
FIG. 23 is a table showing the symbols, signals, data rate and description of signals in a first embodiment of the XPBus.
FIG. 24 is a table showing different types of first nibbles and their corresponding data packet types.
FIG. 25 is a table showing the information transmitted on the XPBus during two clock cycles of the XPBus in one embodiment of the present invention where 10 data bits transmitted in each clock cycle of the XPBus.
FIG. 26 is a block diagram of one embodiment of the host interface controller and the peripheral interface controller of the present invention.
In the present embodiment, ACM 10 includes computer components, as will be described below, including a central processing unit (“CPU”), IDE controller, hard disk drive, computer memory, and the like. The computer module bay (i.e., CMB) 40 is an opening or slot in the desktop console. The CMB houses the ACM and provides communication to and from the ACM. The CMB also provides mechanical protection and support to ACM 10. The CMB has a mechanical alignment mechanism for mating a portion of the ACM to the console. The CMB further has thermal heat dissipation sinks, electrical connection mechanisms, and the like. Some details of the ACM can be found in co-pending U.S. patent application Ser. Nos. 09/149,882 and 09/149,548 filed Sep. 8, 1998 commonly assigned, and hereby incorporated by reference for all purposes.
In a preferred embodiment, the present system has a security system, which includes a mechanical locking system, an electrical locking system, and others. The mechanical locking system includes at least a key 11. The key 11 mates with key hole 13 in a lock, which provides a mechanical latch 15 in a closed position. The mechanical latch, in the closed position, mates and interlocks the ACM to the computer module bay. The mechanical latch, which also has an open position, allows the ACM to be removed from the computer module bay. Further details of the mechanical locking system are shown in the FIG. below.
The CPU module can use a suitable microprocessing unit, microcontroller, digital signal processor, and the like. In a specific embodiment, the CPU module uses, for example, a 400 MHz Pentium II microprocessor module from Intel Corporation and like microprocessors from AMD Corporation, Cyrix Corporation (now National Semiconductor Corporation), and others. In other aspects, the microprocessor can be one such as the Compaq Computer Corporation Alpha Chip, Apple Computer Corporation PowerPC G3 processor, and the like. Further, higher speed processors are contemplated in other embodiments as technology increases in the future.
In the CPU module, host interface controller 401 is coupled to BIOS/flash memory 405. Additionally, the host interface controller is coupled to a clock control logic, a configuration signal, and a peripheral bus. The present invention has a host interface controller that has lock control 403 to provide security features to the present ACM. Furthermore, the present invention uses a flash memory that includes codes to provide password protection or other electronic security methods.
The second portion of the attached computer module has the hard drive module 420. Among other elements, the hard drive module includes north bridge 421, graphics accelerator 423, graphics memory 425, a power controller 427, an IDE controller 429, and other components. Adjacent to and in parallel alignment with the hard drive module is a personal computer interface (“PCI”) bus 431, 432. A power regulator 435 is disposed near the PCI bus.
In a specific embodiment, north bridge unit 421 often couples to a computer memory, to the graphics accelerator 423, to the IDE controller, and to the host interface controller via the PCI bus. Graphics accelerator 423 typically couples to a graphics memory 423, and other elements. IDE controller 429 generally supports and provides timing signals necessary for the IDE bus. In the present embodiment, the IDE controller is embodied as a 643U2 PCI-to IDE chip from CMD Technology, for example. Other types of buses than IDE are contemplated, for example EIDE, SCSI, USB, and the like in alternative embodiments of the present invention.
The hard drive module or mass storage unit 420 typically includes a computer operating system, application software program files, data files, and the like. In a specific embodiment, the computer operating system may be the Windows98 operating system from Microsoft Corporation of Redmond Washington. Other operating systems, such as WindowsNT, MacOS8, Unix, and the like are also contemplated in alternative embodiments of the present invention. Further, some typical application software programs can include Office98 by Microsoft Corporation, Corel Perfect Suite by Corel, and others. Hard disk module 420 includes a hard disk drive. The hard disk drive, however, can also be replaced by removable hard disk drives, read/write CD ROMs, flash memory, floppy disk drives, and the like. A small form factor, for example 2.5″, is currently contemplated, however, other form factors, such as PC card, and the like are also contemplated. Mass storage unit 240 may also support other interfaces than IDE.
In a specific embodiment, the present invention provides a file and data protection security system and method for a removable computer module or ACM. ACM contains the primary hard disk drive (HDD) where the operating system, application programs, and data files reside. The security system is used to prevent illegal access and copying of any file residing on the HDD inside ACM. An ACM is a self-contained computing device that can be armed with security software and hardware to protect its owner's private files and data. ACM docks with a computer bay in a wide variety of peripheral consoles. The combined ACM and peripheral console function as a personal computer. A computer module interface bus connects ACM and peripheral device. In some embodiments, all ACM data passes through computer module interface (CMI) bus to reach any device in the peripheral console, i.e. floppy drive, removable media, secondary hard disk drive, modem, and others. CMI bus data transfer is controlled by a pair of interface controllers on either side of the bus. This partitioning of a personal computer offer a way of protecting against illegal access of data residing within ACM by guarding data transaction through the computer module interface bus.
In a specific embodiment, a secured ACM has an enclosure that includes the following components:
-
- 1) ACPU,
- 2) Main memory,
- 3) A primary Hard Disk Drive (HDD),
- 4) Operating System, application software, data files on primary HDD,
- 5) Interface circuitry and connectors to peripheral console,
- 6) Flash memory used for storing security code and ID,
- 7) Data detection and control circuitry to manage data flow to peripheral console,
- 8) Circuit board connecting the above components, and others.
A peripheral console includes some of the following elements:
-
- 1) Input means, e.g. keyboard and mouse,
- 2) Display means, e.g. CRT monitor, or integrated LCD display,
- 3) Removable storage media subsystem, e.g. Floppy drive, CDROM drive,
- 4) Communication device, e.g. LAN or modem,
- 5) Computer Module Bay, interface device and connectors to ACM,
- 6) Flash memory with security ID,
- 7) Power supply or battery system, and other devices.
The Computer Module Bay (CMB) is an opening in a peripheral console that receives ACM. CMB provides mechanical protection and electrical connection to ACM. The Computer Module Interface bus is made up of 3 bus components: video bus, peripheral data bus, and power bus. Video Bus consists of video output of graphics devices, i.e. analog RGB and control signals for monitor, or digital video signals to drive flat panel displays. Power bus supplies the power for ACM. Peripheral data bus is a high speed, compressed, peripheral bridge bus managed by a Host Interface Controller in ACM and a peripheral Interface Controller in peripheral console. In some embodiments, all peripheral data transaction passes through the interface controllers.
The implementation of the secured ACM generally includes the following elements:
-
- 1) A programmable Flash memory controlled by the Peripheral Interface Controller containing the security ID for the peripheral console,
- 2) A programmable Flash memory controlled by the Host Interface Controller containing hardware specific security code and ID for the computer module,
- 3) A data detection and control circuitry within Host Interface Controller to detect and manage data going out of ACM, and
- 4) A low level hardware dependent security code to perform security ID matching, hardware programming to manage data flow,
- 5) A high-level security program to manage user interface, program security ID, program security level, and other functions.
The hardware and software implementation allow more flexibility in the level of security protection offered to an ACM owner. Some examples of security levels are:
-
- 1) No access—Security IDs do not match according to owner's requirement. The Host Interface Controller blocks all peripheral data traffic between ACM and peripheral console except for keyboard and mouse,
- 2) Peripheral Read-only—No files can be written to any peripheral devices. All peripheral devices in peripheral console are managed as Read-only devices. The primary hard disk drive in ACM can be accessed freely,
- 3) Limited access—Certain peripheral devices are allowed read/write access, i.e. modem, and other devices are Read-only, i.e. removable media devices,
- 4) Full access—No restriction, and others.
Upon power up, the low level security code is executed to compare security ID between the respective flash memory between ACM and peripheral console. Typical security ID can include:
-
- 1) User ID
- 2) User password
- 3) User Access privilege
- 4) Business ID
- 5) Business password
- 6) Equipment ID
- 7) Equipment access privilege, and any other security IDs.
The user through the security program can activate different levels of password protection, which can be stored in a look up table. The company through the security program can control different levels of access privilege of a user, a business group, or equipment. The security code then program the security level allowed by the access privilege determined by the security ID matching result. For example, if an unidentified peripheral console is detected upon power up by the low level security code, e.g. a home unit, the access privilege can set to Peripheral Read-only. With Read-only access privilege for all peripheral devices in peripheral console, the data detection and control circuitry is programmed to monitor all data traffic going to the peripheral console. Any memory block transfer to peripheral console will be detected and blocked. Under this mode, a user can use the computer with free access to the primary HDD in ACM. Any files can be read from other storage media in the peripheral console. But no files from the primary HDD can be copied to another media.
The data detection circuitry separately monitors peripheral bus operation type and memory address range being accessed. A specific address range for memory accesses and for I/O accesses can be programmed for the data detection circuitry to flag a match. A data blocking circuitry is triggered by the detection circuitry when a match occurs, and blank out the data that is being sent to the peripheral console. For the security system to be effective, a temper tamper resistant enclosure must be used to prevent removal of the hard disk drive and the flash memory inside ACM. Further details are shown throughout the present specification and more particularly below.
Other types of access can be granted depending upon the consoles. For example, various consoles include, among others, a console at a user's home, e.g., “John Doe's,” a console in the user's office 329, a console in a co-worker's office 331, which the user can access. The access from John Doe's home console uses security identification 317 and provides restricted access 305. The user's use of the module 307 can be from a variety of consoles and is accessed using security identification 319. Here, access privilege is private, which allows the user to access private personal information or private company information that the user has created. The user's access from his office relies upon security identification 321, which grants access to private information and general company information. The co-worker's console can also be used with security identification 323, which allows the user to access general company information but not private information of John Doe, for example. Depending upon the console used by the user, the security system can provide partial or full access to information on servers via network as well as an attached computer module. Information can also be limited to read only for certain information sources such as a server, a hard drive, a floppy drive, and others.
In a specific embodiment, the present invention also provides a security feature for the ACM 307. Here, the user of the ACM can be granted access to information in the ACM if the correct security identification information 319 is provided to the combination of ACM and console. Once the correct information is provided, the user can access the information on the hard drive of the ACM, which can be for private use. Other levels of access and security can also be provided depending upon the application.
The block diagram 500 illustrates attached computer module 501. The module 501 has a central processing unit 502, which communicates to a north bridge 541, by way of a CPU bus 527. The north bridge couples to main memory 523 via memory bus 529. The main memory can be any suitable high speed memory device or devices such as dynamic random access memory (“DRAM”) integrated circuits and others. The DRAM includes at least 32 Meg. or 64 Meg. and greater of memory, but can also be less depending upon the application. Alternatively, the main memory can be coupled directly with the CPU in some embodiments. The north bridge also couples to a graphics subsystem 515 via bus 542. The graphics subsystem can include a graphics accelerator, graphics memory, and other devices. Graphics subsystem transmits a video signal to an interface connector, which couples to a display, for example.
The attached computer module also includes a primary hard disk drive 509 that serves as a main memory unit for programs and the like. The hard disk can be any suitable drive that has at least 2 GB and greater. As merely an example, the hard disk is a Marathon 2250 (2.25 GB, 2 ½ inch drive) product made by Seagate Corporation of Scotts Valley, but can be others. The hard disk communicates to the north bridge by way of a hard disk drive controller and bus lines 502 and 531. The hard disk drive controller couples to the north bridge by way of the host PCI bus 531, which connects bus 537 to the north bridge. The hard disk includes computer codes that implement a security program according to the present invention. Details of the security program are provided below.
The attached computer module also has a flash memory device 505 with a BIOS. The flash memory device 505 also has codes for a user password that can be stored in the device. The flash memory device generally permits the storage of such password without a substantial use of power, even when disconnected. As merely an example, the flash memory device has at least 512 kilobits or greater of memory, or 1 megabits or greater of memory. The flash memory device can store a security identification number or the like. The flash memory device is generally non-volatile and can preserve information even when the power is turned off, for example. The flash memory generally has at least 128 kilobits storage cells or more. The flash memory can be any product such as a W29C020 product made by a company called Winbond of Taiwan, but can also be others. The flash memory cell and user identification will be more fully described below in reference to the FIGS. A host interface controller 507 communications to the north bridge via bus 535 and host PCI bus. The host interface controller also has a data control 511. Host interface controller 507 communicates to the console using bus 513, which couples to connection 515.
Peripheral console 503 includes a variety of elements to interface to the module 501, display 551, and network 553. The console forms around south bridge 571, which couples to bus 563, which couples to bus 561. Bus 561 is in communication with network card 555, which is a local area network for Ethernet, for example. South bridge also couples through control 569 to peripheral interface controller 567, which also communicates to bus 561. Peripheral interface controller also couples to host interface controller through connection 515 and bus 513. The peripheral console has a primary removable drive 559 connected to south bridge through bus 575. South bridge also couples to secondary hard disk through bus 577.
In a specific embodiment, the peripheral console also has a serial EEPROM memory device 575, which is coupled to the peripheral interface controller. The memory device can store a security identification number or the like. The memory device is generally non-volatile and can preserve information even when the power is turned off, for example. The memory generally has at least 16 kilobits of storage cells or more. Preferably, the memory device is a 16 kilobit device or 64 megabit device or greater, depending upon the application. The memory can be any product such as a X24320 product made by a company called Xicor, but can also be others. The memory cell and user identification will be more fully described below in reference to the FIGS.
The software 601 includes an operating system 609, application programs 607, and a data security and initialization program 605. Other programs can also exist. Additionally, some of these programs may not exist. Preferably, the data security and initialization program exists. This data security and initialization program is initiated once the attached computer module is inserted into the console. The program interface and oversees a variety of hardware features, which will be used to control access to the external devices, for example. Of course, the particular configuration of the software will depend upon the application.
Hardware features can be implemented using a primary hard disk 611 coupled to a CPU/cache combination, which includes a main memory. The main memory is often a volatile memory such as dynamic random access memory. Data from any one of the external devices can enter the CPU/cache combination. For example, the secondary hard disk memory and I/O address range data is transferred 624 to the CPU/cache combination. The removable drive memory and I/O address range data can also transfer 625 to the CPU/cache combination. The LAN memory and 1/0 address range data can also transfer 626 to the CPU/cache combination. Keyboard data can also transfer 627 to the CPU/cache combination. To write data from the module into any one of these external elements, the data security program interfaces with the data detection and control circuit to determine of such data should be transferred to any one of the external elements. As noted, the external elements include, among others, secondary hard disk, and removable drive. Here, the data security program checks the security identification number with other numbers to determine the security access level. There are many other ways that the present invention can be implemented. These methods are described more fully below.
The present method reads (step 703) the security code, which has been entered. Next, the security code is compared with a stored code, which is in flash memory or the like (step 705). If the compared code matches with the stored code, the method resumes to step 708. Alternatively, the method goes to step 707 via branch 706 where no access is granted. When no access is granted, all data are blocked out from the user that attempts to log onto the system. Alternatively, the method determines if a certain level of access is granted, step 708. Depending upon the embodiment, the present method can grant full access, step 710, via branch 716. The present method allows full access based upon information stored in the flash memory device. Alternatively, the method can allow the user to access a limited amount of information.
Here, the present method allows for at least one or more than two levels of access. In a specific embodiment, the present method allows for the user of the module to access peripheral storage (step 711). The access privilege is read-only. The user can read information on the peripheral storage including hard disks and the like. Once the user accesses the storage, the method data control , step 719, takes over, where the hardware prevents the user from accessing other information, step 721. In a specific embodiment, the method can allow information to be removed from the peripheral storage. If the method allows for data to be removed, step 723, the method goes through branch 731 to let data out, which can occur through the module. Alternatively, the method goes to block data (step 725) via branch 733. Depending upon the embodiment, the method returns to the decision block, step 723. Alternatively, the method traverses branch 714 to a peripheral read-only process, step 712. The read-only process programs data control, step 713. Next, the hardware takes over (step 715). The method blocks all data from being accessed by the user, step 717.
As shown, the attached computer module has elements such as a memory region 807, which stores BIOS information, a security code, and a security identification number on a flash memory device or the like. The memory region couples to a central processing region 809, which can include CPU, chipset, cache memory, graphics, and a hard disk drive, as well as other features. The central processing region couples to a host interface controller, which interfaces the attached computer module to one of the peripheral consoles. Any of the above information can also be included in the attached computer module.
Each peripheral console also has a variety of elements. These elements include a region 813, 821, which has a flash memory device with a security identification number, a password, access information, access privileges, internet service provider access information, as well as other features, which were previously noted. The peripheral console also has an interface controller 815, 823, which couples region 813, 821, respectively to a networking device 817, 825. The networking device can be an Ethernet card 817, which allows communication to the local area network 819. Alternatively, the networking device can be a DSL modem 825, which allows communication to a DSL (or ADSL) phone line. Other types of networking device can also be used, depending upon the application.
Each console provides a selected connection based upon set of predefined factors. These factors include communication hardware information so that software in attached computer module can read and allow a connection to a network. Here, access information can be provided to the user. Information about connection information will also be included. This connection information includes telephone numbers, account numbers, passwords (local), or a company password. The console and module combination will take care of charges, etc. based upon time bases. Module will have credit card information, but will have security. In a specific embodiment, the module inserts into the console. The module then asks the console which hardware will be used. If the hardware is an Ethernet connect, the module configures connection information to access the Ethernet connection. Alternatively, if the hardware requires a DSL connection, the module configures connection information to access the DSL connection. Other configuration information such as company server information, password, can also be provided.
A personal computer system that comprises two physically separate units and the interconnection between them is disclosed. The first unit, an attached computing module (ACM), contains the core computing power and environment for a computer user. The second unit, a peripheral console (PCON), contains the power supply and primary input and output devices for the computer system. An ACM and a PCON are coupled with one another to form a fully functional personal computer system.
FIG. 9 depicts a notebook computer PCON configuration. The opening of the computer bay 992 is visible at the side of the PCON unit 900. The PCON 900 provides an integrated LCD display panel 910 as the user's primary display device. The PCON 900 provides an integrated keyboard 922 as the user's primary input device.
FIG. 10 is a block diagram of the components in one computer system. The computer system comprises an attached computer module (ACM) 1000, a peripheral console (PCON) 1001, and the interconnection apparatus 1003 between them. The ACM 1000 includes the central processing unit (CPU) 1010, system memory 1020, high performance devices 1050, primary mass storage 1030, and related interface and support circuitry 1040. The PCON 1001 includes primary display 1011, primary input 1021, secondary mass storage 1051, other devices 1061, expansion slots 1071, the primary power supply 1031, and related interface and support circuitry 1041. The interconnection apparatus 1003 includes circuitry to convey power and operational signals between the ACM 1000 and PCON 1001.
Within the ACM 1000, the CPU 1010 executes instructions and manipulates data stored in the system memory 1020. The CPU 1010 and system memory 1020 represent the user's core computing power. The core computing power may also include high performance devices 1050 such as advanced graphics processor chips that greatly increase overall system performance and which, because of their speed, need to be located close to the CPU 1010. The primary mass storage 1030 contains persistent copies of the operating system software, application software, configuration data, and user data. The software and data stored in the primary mass storage device 1030 represent the user's computing environment. Interface and support circuitry 1040 primarily includes interface chips and signal busses that interconnect the CPU 1010, system memory 1020, high performance devices 1050, and primary mass storage 1030. The interface and support circuitry 1040 also connects ACM-resident components with the ACM-to-PCON interconnection apparatus 1003 as needed.
Within the PCON 1001, the primary display component 1011 may include an integrated display device or connection circuitry for an external display device. This primary display device 1011 may be, for example, an LCD, plasma, or CRT display screen used to display text and graphics to the user for interaction with the operating system and application software. The primary display component 1011 is the primary output of the computer system, i.e., the paramount vehicle by which programs executing on the CPU 1010 can communicate toward the user.
The primary input component 1021 of the PCON 1001 may include an integrated input device or connection circuitry for attachment to an external input device. The primary input 1021 may be, for example, a keyboard, touch screen, keypad, mouse, trackball, digitizing pad, or some combination thereof to enable the user to interact with the operating system and application software. The primary input component 1021 is the paramount vehicle by which programs executing on the CPU 1010 receive signals from the user.
The PCON 1001 may contain secondary mass storage 1051 to provide additional high capacity storage for data and software. Secondary mass storage 1051 may have fixed or removable media and may include, for example, devices such as diskette drives, hard disks, CD-ROM drives, DVD drives, and tape drives.
The PCON 1001 may be enhanced with additional capability through the use of integrated “Other Devices” 1061 or add-on cards inserted into the PCON's expansion slots 1071. Examples of additional capability include sound generators, LAN connections, and modems. Interface and support circuitry 1041 primarily includes interface chips, driver chips, and signal busses that interconnect the other components within the PCON 1001. The interface and support circuitry 1041 also connects PCON-resident components with the ACM-to-PCON interconnection apparatus 1003 as needed.
Importantly, the PCON 1001 houses the primary power supply 1031. The primary power supply 1031 has sufficient capacity to power both the PCON 1001 and the ACM 1000 for normal operation. Note that the ACM 1000 may include a secondary “power supply” in the form, for example, of a small battery. Such a power supply would be included in the ACM 1000 to maintain, for example, a time-of-day clock, configuration settings when the ACM 1000 is not attached to a PCON, or machine state when moving an active ACM immediately from one PCON to another. The total energy stored in such a battery would, however, be insufficient to sustain operation of the CPU 1010 at its rated speed, along with the memory 1020 and primary mass storage 1030, for more than a fraction of an hour, if the battery were able to deliver the required level of electrical current at all.
FIG. 11 is a block diagram of an attached computing module (ACM) 1100. The physical ACM package 1100 contains the ACM functional components 1101 and the ACM side of the ACM-to-PCON Interconnection 1700. The ACM 1101 comprises a CPU component 1110, a system memory component 1120, a primary mass storage component 1130, a high performance devices components 1150, and an interface and support component 1140.
The ACM side of the ACM-to-PCON Interconnection 1700 comprises a Host Interface Controller (HIC) component 1720 and an ACM connector component 1730. The HIC 1720 and connector 1730 components couple the ACM functional components 1100 with the signals of an ACM-to-PCON interface bus 1710 used to operatively connect an ACM with a PCON. The ACM-to-PCON interface bus 1710 comprises conveyance for electrical power 1714 and signals for a peripheral bus 1712, video 1716, video port 1717, and console type 1718. The preferred ACM-to-PCON Interconnection 1700 is described in detail in a companion U.S. patent application Ser. No. 09/149,882, entitled “A Communication Channel and Interface Devices for Bridging Computer Interface Buses,” by the same inventor, filed on Sep. 8, 1998, and hereby incorporated by reference. The preferred ACM-to-PCON interconnection 1700 includes circuitry to transmit and receive parallel bus information from multiple signal paths as a serial bit stream on a single signal path. This reduces the number of physical signal paths required to traverse the interconnection 1700. Further, employing low-voltage differential signaling (LVDS) on the bit stream data paths provides very reliable, high-speed transmission across cables. This represents a further advantage of the present invention.
Clocking circuitry 1144 generates clock signals for distribution to other components within the ACM 1100 that require a timing and synchronization clock source. The CPU 1110 is one such component. Often, the total power dissipated by a CPU is directly proportional to the frequency of its main clock signal. The presently described embodiment of the ACM 1100 includes circuitry that can vary the frequency of the main CPU clock signal conveyed to the CPU 1110 via signal path 1162, in response to a signal received from the host interface controller (HIC) 1720 via signal path 1161. The generation and variable frequency control of clocking signals is well understood in the art. By varying the frequency, the power consumption of the CPU 1110 (and thus the entire ACM 1100) can be varied.
The variable clock rate generation may be exploited to match the CPU power consumption to the available electrical power. Circuitry in the host interface controller (HIC) 1720 of the presently described embodiment adjusts the frequency control signal sent via signal path 1161 to the clocking circuitry 1144, based on the “console type” information signal 1718 conveyed from the peripheral console (PCON) by the CPU-to-PCON interconnection 1700.
FIG. 12 is a block diagram of a peripheral console (PCON). A peripheral console couples with an ACM to form an operating personal computer system. The peripheral console (PCON) supplies an ACM with primary input, display, and power supply; the ACM supplies the core computing power and environment of the user. In the presently described embodiment the physical PCON package 1200 contains the PCON functional components 1201 and the PCON side of the ACM-to-PCON Interconnection 1800. The PCON functional components 1201 comprise primary display 1210, a primary input 1220, a primary power supply 1230, interface and support 1240, secondary mass storage 1250, other devices 1260, and expansion slots 1270.
The PCON side of the ACM-to-PCON Interconnection 1800 comprises a Peripheral Interface Controller (PIC) component 1840, a PCON connector component 1850, console-type component 1842, and flash memory device 1848. The PIC 1840 and connector 1850 components couple the PCON functional components 1201 with the signals of an ACM-to-PCON interface bus 1810 used to operatively connect an ACM with a PCON. The ACM-to-PCON interface bus 1810 comprises conveyance for electrical power 1814 and signals for a peripheral bus 1812, video 1816, video port 1817, and console-type 1818. The preferred ACM-to-PCON Interconnection 1800 is described in detail in the U.S. patent application entitled “A Communication Channel and Interface Devices for Bridging Computer Interface Buses,” already incorporated herein by reference.
Connector component 1850 may be selected to mate directly with the connector component 1730 of an ACM (shown in FIG. 11). Alternatively, connector component 1850 may be selected to mate with, for example, the connector on one end of a cable intervening between the PCON and an ACM in a particular embodiment. The ACM-to-PCON interconnection described in the aforementioned companion patent application has the advantage of providing reliable signal conveyance across low cost cables.
Flash memory device 1848 provides non-volatile storage. This storage may be accessible to devices in both the ACM and the PCON, including the host interface controller and the peripheral interface controller 1840 to which it is connected. As such, flash memory 1848 may be used to store configuration and security data to facilitate an intelligent mating between an ACM and a PCON that needs no participation of the CPU.
The secondary mass storage component 1250 of the PCON functional circuitry 1201 of the presently described embodiment comprises diskette drive 1254, hard disk drive 1252, and CD-ROM drive 1256. Secondary mass storage 1250 generally provides low-cost, non-volatile storage for data files which may include software program files. Data files stored on secondary mass storage 1250 are not part of a computer user's core computing power and environment. Secondary mass storage 1250 may be used to store, for example, seldom used software programs, software programs that are used only with companion hardware devices installed in the same peripheral console 1200, or archival copies of data files that are maintained in primary mass storage 1130 of an ACM (shown in FIG. 11). Storage capacities for secondary mass storage 1250 devices may vary from the 1.44 megabytes of the 3.5-inch high density diskette drive 1254, to more than 10 gigabytes for a large format (5-inch) hard disk drive 1252. Hard disk drive 1252 employs fixed recording media, while diskette drive 1254 and CD-ROM drive 1256 employ removable media. Diskette drive 1254 and hard disk drive 1252 support both read and write operations (i.e., data stored on their recording media may be both recalled and modified) while CD-ROM drive 1256 supports only read operations.
Two PCI or PCI-like buses are interfaced using a non-PCI or non-PCI-like channel. PCI control signals are encoded into control bits, and the control bits, rather than the control signals that they represent, and are transmitted on the interface channel. At the receiving end, the control bits representing control signals are decoded back into PCI control signals prior to being transmitted to the intended PCI bus.
The fact that control bits rather than control signals are transmitted on the interface channel allows using a smaller number of signal channels and a correspondingly small number of conductive lines in the interface channel than would otherwise be possible. This is because the control bits can be more easily multiplexed at one end of the interface channel and recovered at the other end than control signals. This relatively small number of signal channels used in the interface channel allows using LVDS channels for the interface. As mentioned above, an LVDS channel is more cable friendly, faster, consumes less power, and generates less noise than a PCI bus channel. Therefore, an LVDS channel is advantageously used for the hereto unused purpose of interfacing PCI or PCI-like buses. The relatively smaller number of signal channels in the interface also allows using connectors having smaller pins counts. As mentioned above an interface having a smaller number of signal channels and, therefore, a smaller number of conductive lines is less bulky and less expensive than one having a larger number of signal channels. Similarly, connectors having a smaller number of pins are also less expensive and less bulky than connectors having a larger number of pins.
In one embodiment, the present invention encompasses an apparatus for bridging a first computer interface bus and a second computer interface bus, in a microprocessor based computer system where each of the first and second computer interface buses have a number of parallel multiplexed address/data bus lines and operate at a clock speed in a predetermined clock speed range having a minimum clock speed and a maximum clock speed. The apparatus comprises an interface channel having a clock channel and a plurality of bit channels for transmitting bits; a first interface controller coupled to the first computer interface bus and to the interface channel to encode first control signals from the first computer interface bus into first control bits to be transmitted on the interface channel and to decode second control bits received from the interface channel into second control signals to be transmitted to the first computer interface bus; and a second interface controller coupled to the interface channel and the second computer interface bus to decode the first control bits from the interface channel into third control signals to be transmitted on the second computer interface bus and to encode fourth control signals from the second computer interface bus into the second control bits to be transmitted on the interface channel.
In one embodiment, the first and second interface controllers comprise a host interface controller (HIC) and a peripheral interface controller (PIC), respectively, the first and second computer interface buses comprise a primary PCI and a secondary PCI bus, respectively, and the interface channel comprises an LVDS channel.
In a preferred embodiment, the interface channel has a plurality of serial bit channels numbering fewer than the number of parallel bus lines in each of the PCI buses and operates at a clock speed higher than the clock speed at which any of the bus lines operates. More specifically, the interface channel includes two sets of unidirectional serial bit channels which transmit data in opposite directions such that one set of bit channels transmits serial bits from the HIC to the PIC while the other set transmits serial bits from the PIC to the HIC. For each cycle of the PCI clock, each bit channel of the interface channel transmits a packet of serial bits.
The HIC and PIC each include a bus controller to interface with the first and second computer interface buses, respectively, and to manage transactions that occur therewith. The HIC and PIC also include a translator coupled to the bus controller to encode control signals from the first and second computer interface buses, respectively, into control bits and to decode control bits from the interface channel into control signals. Additionally, the HIC and PIC each include a transmitter and a receiver coupled to the translator. The transmitter converts parallel bits into serial bits and transmits the serial bits to the interface channel. The receiver receives serial bits from the interface channel and converts them into parallel bits.
FIG. 13 is a block diagram of one embodiment of a computer system 1300 using the interface of the present invention. Computer system 1300 includes an attached computer module (ACM) 1305 and a peripheral console 1310, which are described in greater detail in the application of William W. Y. Chu, Ser. No. 09/149,548, for “Personal Computer Peripheral Console With Attached Computer Module” filed on Sep. 8, 1998 and incorporated herein by reference. The ACM 1305 and the peripheral console 1310 are interfaced through an exchange interface system (XIS) bus 1315. The XIS bus 1315 includes power bus 1316, video bus 1317 and peripheral bus (XPBus) 1318, which is also herein referred to as an interface channel. The power bus 1316 transmits power between ACM 1305 and peripheral console 1310. In a preferred embodiment power bus 1316 transmits power at voltage levels of 3.3 volts, 5 volts and 12 volts. Video bus 1317 transmits video signals between the ACM 1305 and the peripheral console 1310. In a preferred embodiment, the video bus 1317 transmits analog Red Green Blue (RGB) video signals for color monitors, digital video signals (such as Video Electronics Standards Association (VESA) Plug and Display's Transition Minimized Differential Signaling (TMDS) signals for flat panel displays), and television (TV) and/or super video (S-video) signals. The XPBus 1318 is coupled to host interface controller (HIC) 1319 and to peripheral interface controller (PIC) 1320, which is also sometimes referred to as a bay interface controller.
In the embodiment shown in FIG. 13, HIC 1319 is coupled to an integrated unit 1321 that includes a CPU, a cache and a north bridge. In another embodiment, such as that shown in FIG. 17, the CPU 1705 and north bridge 1710 are separate rather than integrated units. In yet another embodiment, such as that shown in FIG. 18, the HIC and PIC are integrated with the north and south bridges, respectively, such that integrated HIC and north bridge unit 1805 includes an HIC and a north bridge, while integrated PIC and south bridge unit 1810 includes a PIC and a south bridge. FIG. 19 shows an attached computer module with integrated CPU/NB/Graphics 1915 and Integrated HIC/SB 1920. FIG. 20 shows an attached computer module with single chip 2025 fully integrated: CPU, Cache, Core Logic, Graphics controller and Interface controller.
FIG. 14 is a detailed block diagram of one embodiment of the HIC of the present invention. As shown in FIG. 14, HIC 1600 comprises bus controller 1610, translator 1620, transmitter 1630, receiver 1640, a PLL 1650, an address/data multiplexer (A/D MUX) 1660, a read/write controller (RD/WR Cntl) 1670, a video serial to parallel converter 1680 and a CPU control & general purpose input/output latch/driver (CPU CNTL & GPIO latch/driver) 1690.
HIC 1600 is coupled to an optional flash memory BIOS configuration unit 1601. Flash memory unit 1601 stores basic input output system (BIOS) and PCI configuration information and supplies the BIOS and PCI configuration information to A/D MUX 1660 and RD/WR Control 1670, which control the programming, read, and write of flash memory unit 1601.
Bus controller 1610 is coupled to the host PCI bus, which is also referred to herein as the primary PCI bus, and manages PCI bus transactions on the host PCI bus. Bus controller 1610 includes a slave (target) unit 1611 and a master unit 1616. Both slave unit 1611 and master unit 1616 each include two first in first out (FIFO) buffers, which are preferably asynchronous with respect to each other since the input and output of the two FIFOs in the master unit 1616 as well as the two FIFOs in the slave unit 1611 are clocked by different clocks, namely the PCI clock and the PCK. Additionally, slave unit 1611 includes encoder 1622 and decoder 1623, while master unit 1616 includes encoder 1627 and decoder 1628. The FIFOs 1612, 1613, 1617 and 1618 manage data transfers between the host PCI bus and the XPBus, which in the embodiment shown in FIG. 14 operate at 33 MHz and 66 MHz, respectively. PCI address/data (AD) from the host PCI bus is entered into FIFOs 1612 and 1617 before they are encoded by encoders 1622 and 1627. Encoders 1622 and 1627 format the PCI address/data bits to a form more suitable for parallel to serial conversion prior to transmittal on the XPBus. Similarly, address and data information from the receivers is decoded by decoders 1623 and 1628 to a form more suitable for transmission on the host PCI bus.
The multiplexed parallel A/D bits and some control bits input to transmitter 1630 are serialized by parallel to serial converters 1632 of transmitter 1630 into 10 bit packets. These bit packets are then output on data lines PD0 to PD3 of the XPBus. Other control bits are serialized by parallel to serial converter 1633 into 10 bit packets and sent out on control line PCN of the XPBus.
FIG. 15 is a detailed block diagram of one embodiment of the PIC of the present invention. PIC 11100 is nearly identical to HIC 1600 in its function, except that HIC 1600 interfaces the host PCI bus to the XPBus while PIC 11100 interfaces the secondary PCI bus to the XPBus. Similarly, the components in PIC 11100 serve the same function as their corresponding components in HIC 1600. Reference numbers for components in PIC 11100 have been selected such that a component in PIC 11100 and its corresponding component in HIC 1600 have reference numbers having the same two least significant digits. Thus for example, the bus controller in PIC 11100 is referenced as bus controller 11110 while the bus controller in HIC 1600 is referenced as bus controller 1610. As many of the elements in PIC 11100 serve the same functions as those served by their corresponding elements in HIC 1600 and as the functions of the corresponding elements in HIC 1600 have been described in detail above, the function of elements of PIC 11100 having corresponding elements in HIC 1600 will not be further described herein. Reference may be made to the above description of FIG. 14 for an understanding of the functions of the elements of PIC 11100 having corresponding elements in HIC 1600.
FIG. 16 is a schematic diagram of lines PCK, PD0 to PD3, and PCN. These lines are unidirectional LVDS lines for transmitting clock signals and bits from the HIC to the PIC. The bits on the PD0 to PD3 and the PCN lines are sent synchronously within every clock cycle of the PCK. Another set of lines, namely PCKR, PDR0 to PDR3, and PCNR, are used to transmit clock signals and bits from the PIC to HIC. The lines used for transmitting information from the PIC to the HIC have the same structure as those shown in FIG. 16, except that they transmit data in a direction opposite to that in which the lines shown in FIG. 16 transmit data. In other words they transmit information from the PIC to the HIC. The bits on the PDR0 to PDR3 and the PCNR lines are sent synchronously within every clock cycle of the PCKR. Some of the examples of control information that may be sent in the reverse direction, i.e., on PCNR line, include a request to switch data bus direction because of a pending operation (such as read data available), a control signal change in the target requiring communication in the reverse direction, target busy, and transmission error detected.
The XPBus which includes lines PCK, PD0 to PD3, PCN, PCKR, PDR0 to PDR3, and PCNR, has two sets of unidirectional lines transmitting clock signals and bits in opposite directions. The first set of unidirectional lines includes PCK, PD0 to PD3, and PCN. The second set of unidirectional lines includes PCKR, PDR0 to PDR3, and PCNR. Each of these unidirectional set of lines is a point-to-point bus with a fixed transmitter and receiver, or in other words a fixed master and slave bus. For the first set of unidirectional lines, the HIC is a fixed transmitter/master whereas the PIC is a fixed receiver/slave. For the second set of unidirectional lines, the PIC is a fixed transmitter/master whereas the HIC is a fixed receiver/slave. The LVDS lines of XPBus, a cable friendly and remote system I/O bus, transmit fixed length data packets within a clock cycle.
The XPBus lines, PD0 to PD3, PCN, PDR0 to PDR3 and PCNR, and the video data and clock lines, VPD and VPCK, are not limited to being LVDS lines, as they may be other forms of bit based lines. For example, in another embodiment, the XPBus lines may be IEEE 1394 lines.
It is to be noted that although each of the lines PCK, PD0 to PD3, PCN, PCKR, PDR0 to PDR3, PCNR, VPCK, and VPD is referred to as a line, in the singular rather than plural, each such line may contain more than one physical line. For example, in the embodiment shown in FIG. 16, each of lines PCK, PD0 to PD3 and PCN includes two physical lines between each driver and its corresponding receiver. The term line, when not directly preceded by the terms physical or conductive, is herein used interchangeably with a signal or bit channel of one or more physical lines for transmitting a signal. In the case of non-differential signal lines, generally only one physical line is used to transmit one signal. However, in the case of differential signal lines, a pair of physical lines is used to transmit one signal. For example, a pair of physical lines together transmit a signal in a bit line or bit channel in an LVDS or IEEE 1394 interface.
A bit based line (i.e., a bit line) is a line for transmitting serial bits. Bit based lines typically transmit bit packets and use a serial data packet protocol. Examples of bit lines include an LVDS line, an IEEE 1394 line, and a Universal Serial Bus (USB) line.
FIGS. 21 and 22 are tables including the pin number, symbol, signal, standard and description for the pins on the peripheral and video connectors, respectively. FIG. 23 is a table showing the symbols, signals, data rate and description of signals on the XPBus, where RTN indicates a ground (GND) reference. In the above tables, P&D stands for plug and display and is a trademark of the Video Electronics Standards Association (VESA) for the Plug and Display standard, DDC2:SCL and DDC2:SDA stand for the VESA display data channel (DDC) standard 2 clock and data signals, respectively, SV stands for super video, V33 is 3.3 volts, and V5 is 5.0 volts. TMDS stands for Transition Minimized Differential Signaling and is a trademark of Silicon Images and refers to their Panel Link technology, which is in turn a trademark for their LVDS technology. TMDS is used herein to refer to the Panel Link technology or technologies compatible therewith.
The reserved data packet types can be used to support non-PCI bus transactions, e.g., USB transactions. The bits sent in the first nibble of each data packet indicate the type of the data packet. FIG. 24 is a table showing different types of first nibbles and their corresponding data packet types.
Although the functionality above has been generally described in terms of a specific sequence of steps, other steps can also be used. Here, the steps can be implemented in a combination of hardware, firmware, and software. Either of these can be further combined or even separated. Depending upon the embodiment, the functionality can be implemented in a number of different ways without departing from the spirit and scope of the claims herein. One of ordinary skill in the art would recognize other variations, modifications, and alternatives.
FIG. 25 is a table showing the information transmitted on the XPBus during two clock cycles of the XPBus in one embodiment of the present invention where 10 data bits are transmitted in each clock cycle of the XPBus. In FIG. 25, A00 to A31 represent 32 bits of PCI address A[31::0], D00 to D31 represent 32 bits of PCI data D[31::0], BS0 to BS3 represent 4 bits of bus status data indicating the status of the XPBus, CM0# to CM3# represent 4 bits of PCI command information, BE0# to BE3# represent 4 bits of PCI byte enable information, and CN0 to CN9 represent 10 bits of control information sent in each clock cycle. As shown in FIG. 25, for each of lines PD0 to PD3, the 10 bit data packets contain one BS bit, one CM/BE bit, and eight A/D bits. For the PCN line, the 10 bit data packet contains 10 CN bits. The first clock cycle shown in FIG. 25 comprises an address cycle in which 4 BS bits, 4 CM bits, 32 A bits and 10 CN bits are sent. The second clock cycle comprises a data cycle in which 4 BS bits, 4 BE bits, 32 D bits and 10 CN bits are sent. The bits transmitted on lines PD0 to PD3 represent 32 PCI AD[31::0] signals, 4 PCI C/BE# [3::0] signals, and part of the function of PCI control signals, such as FRAME#, IRDY#, and TRDY#.
In the embodiment shown in FIG. 25, BS0 to BS3 are sent at the beginning of each clock cycle. The bus status bits indicate the following bus cycle transactions: idle, address transfer, write data transfer, read data transfer, switch XPBus direction, last data transfer, wait, and other cycles.
FIG. 26 is a more detailed block diagram of one embodiment of an HIC 26505 and PIC 26555 of the present invention. HIC 26505 includes a peripheral component interconnect (PCI) bus controller 510, an XPBus controller 26515. a phase lock loop (PLL) clock 520 and an input/output (IO) control 525. Similarly, PIC 26555 includes a PCI bus controller 560, an XPBus controller 26565, a PLL clock 570 and an IO control 575. PCI bus controllers 510 and 560 are coupled to the primary and secondary PCI buses 530 and 580, respectively, and manage PCI transactions on the primary and secondary PCI buses 530 and 580, respectively. Similarly, XPBus Controllers 26515 and 26565 are coupled to XPBus 590. XPBus controller 26515 drives the PCK line 591 and PD[0::3] and PCN lines 592 while XPBus controller 26565 drives the PCKR lines 593, the PDR[0::3] and PCNR lines 594 and the RESET# line 595.
PCI bus controller 510 receives PCI clock signals from the primary PCI bus 530 and is synchronized to the PCI clock. However, as indicated in FIG. 26, the XPBus controller 26515 is asynchronous with the PCI bus controller 510. Instead, the XPBus controller receives a clock signal from the PLL clock 520 and is synchronized therewith. PLL clock 520 generates a clock signal independent of the PCI clock. The asynchronous operation of the PCI bus and the XPBus allows the PCI Bus to change in frequency, for example as in a power down situation, without directly affecting the XPBus clocking. In the embodiment shown in FIG. 26, the PLL clock 520 generates a clock signal having a frequency of 66 MHz, which is twice as large as the 33 MHz frequency of the PCI clock. (The clock signal generated by the PLL clock may have a clock speed different from, including lower than, 66 MHz. For example, in another embodiment, which is discussed in greater detail below, the PLL clock 520 generates a clock signal having a frequency of 132 MHz.)
While the above is a full description of the specific embodiments, various modifications, alternative constructions and equivalents may be used. Therefore, the above description and illustrations should not be taken as limiting the scope of the present invention which is defined by the appended claims.
Claims
1. A security protection method for a computer module, said method comprising:
- inserting the computer module into a console;
- initiating a security program in said module to read a security identification of said console and to read a security identification of said computer module;
- determining of a predetermined security status based upon a relationship of said console identification and said computer module identification;
- selecting said predetermined security status; and
- operating said computer module based upon said security status.
2. The method of claim 1 wherein said predetermined security status disables a network access to the computer module.
3. The method of claim 1 wherein said predetermined security status disables a secondary storage of information from said computer module to substantially prevent information to be transferred from a memory of the computer module to said secondary storage.
4. The method of claim 1 wherein said security program is provided in a system BIOS.
5. The method of claim 1 wherein said step of initiating reads said security identification of said computer module from a flash memory device.
6. The method of claim 1 wherein said step of initiating reads said security identification of said console from a flash memory device.
7. The method of claim 1 wherein said console is selected from a desktop home computing device, an office desktop computing device, a mobile computing device, a television sot-top computing device, and a co-worker's computing device.
8. A system for secured information transactions, the system comprising:
- a console comprising a peripheral controller housed in the console;
- a user identification input device coupled to the peripheral controller, the user identification input device being provided for user identification data; and
- an attached computer module coupled to the console, the attached computer module comprising a security memory device stored with the user identification data.
9. The system of claim 8 wherein the user identification input device is a finger print reader.
10. The system of claim 8 wherein the user identification input device is a voice processing device.
11. A method for operating a module computer into one of a plurality of network systems, the method comprising:
- providing a computer module, the module comprising a connection program;
- inserting the computer module into a computer console, the computer console having access to a network;
- receiving connection information from the computer console;
- configuring the connection program to adapt to the connection information; and
- establish a connection between the computer module and a server coupled to the network.
12. The method of claim 11 wherein the connection information comprises a connection protocol for providing the connection.
13. The method of claim 12 wherein the connection protocol is selected from TCP/IP, or mobile IP.
14. A computer system, comprising:
- a central processing unit (CPU);
- a low voltage differential signal (LVDS) channel directly extending from the CPU, the LVDS channel comprising two unidirectional, serial bit channels to convey data in opposite directions; and
- a mass storage device directly coupled to the CPU;
- wherein the CPU is configured to output a serial bit stream of Universal Serial Bus (USB) protocol information that is conveyed over the LVDS channel.
15. The computer system of claim 14 wherein the mass storage device comprises flash memory.
16. The computer system of claim 14 further comprising a second LVDS channel extending directly from the CPU, comprising two unidirectional, serial bit channels to convey data in opposite directions.
17. The computer system of claim 16 wherein the serial bit channels conveys address and data bits of a Peripheral Component Interface (PCI) bus transaction.
18. The computer system of claim 17 wherein the second LVDS channel couples to the mass storage device.
19. A computer system, comprising:
- a central processing unit (CPU);
- a mass storage device directly coupled to the CPU; and
- a low voltage differential signal (LVDS) channel directly extending from the CPU, the LVDS channel comprising two unidirectional, serial bit channels to convey data in opposite directions;
- wherein the LVDS channel is configured to output a serial bit stream of address bits, data bits, and byte enable information bits of a Peripheral Component Interface (PCI) bus transaction.
20. The computer system of claim 19, wherein the mass storage device comprises flash memory.
21. The computer system of claim 19, wherein the LVDS channel couples to the mass storage device.
22. The computer system of claim 19 wherein the CPU comprises an interface controller coupled to Phase-Locked Loop (PLL) clock circuitry, and wherein the interface controller is directly coupled to the LVDS channel to convey the serial bit stream of address and data bits of the PCI bus transaction.
23. The computer system of claim 22 wherein the interface controller generates different data transfer rates to convey serial bit streams of address and data bits of PCI bus transactions through the LVDS channel based on different clock frequencies generated by the PLL clock circuitry.
24. The computer system of claim 19 wherein the central processing unit (CPU) comprises an interface controller coupled to Phase-Locked Loop (PLL) clock circuitry, and wherein the interface controller is directly coupled to the LVDS channel to convey said PCI bus transaction.
25. The computer system of claim 24 wherein the interface controller generates different data transfer rates to convey the PCI bus transaction through the LVDS channel based on different clock frequencies generated by the PLL clock circuitry.
26. A computer system, comprising:
- an integrated central processing unit and graphics subsystem in a single chip directly connected to a Low Voltage Differential Signal (LVDS) channel to convey encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in serial form, wherein the LVDS channel comprises a first unidirectional, differential signal pair to convey data in a first direction and a second unidirectional, differential signal pair to convey data in a second, opposite direction; and
- a mass storage device directly coupled to the integrated central processing unit and graphics subsystem, comprising flash memory;
- wherein the integrated central processing unit and graphics subsystem directly outputs a differential signal channel to convey digital video display signals.
27. The computer system of claim 26 wherein the differential signal channel conveys Transition Minimized Differential Signaling (TMDS) signals.
28. The computer system of claim 26 wherein the LVDS channel couples to the mass storage device.
29. A computer system, comprising:
- a printed circuit board coupled to a connector;
- a central processing unit (CPU);
- a first low voltage differential signal (LVDS) channel directly extending from the CPU, the LVDS channel comprising two sets of unidirectional, serial bit channels to convey an encoded serial bit stream of address bits, data bits, and byte enable information bits of a Peripheral Component Interconnect (PCI) bus transaction in opposite directions;
- a mass storage device coupled to the CPU; and
- a second LVDS channel coupled to the connector, comprising two sets of unidirectional, serial bit channels to convey serial bit data in opposite directions.
30. The computer system of claim 29 wherein the second LVDS channel communicates Ethernet protocol signals.
31. The computer system of claim 29 further comprising a graphics subsystem integrated with the CPU as a single chip, and wherein the integrated central processing unit and graphics subsystem directly outputs a differential signal channel to convey digital video display signals.
32. A computer system, comprising:
- an integrated central processing unit and graphics subsystem in a single chip directly outputting digital video display signals to a differential signal channel; and
- a Low Voltage Differential Signal (LVDS) channel to convey Universal Serial Bus (USB) protocol signals, wherein the LVDS channel comprises a first unidirectional, differential signal pair to convey data in a first direction and a second unidirectional, differential signal pair to convey data in a second, opposite direction;
- wherein the differential signal channel conveys Transition Minimized Differential Signaling (TMDS) signals.
33. The computer system of claim 32 further comprising a mass storage device directly coupled to the integrated central processing unit and graphics subsystem.
34. The computer system of claim 33, wherein the mass storage device comprises flash memory.
35. A computer system, comprising:
- a printed circuit board coupled to a connector;
- a central processing unit;
- a mass storage unit coupled to the central processing unit;
- a first Low Voltage Differential Signal (LVDS) channel comprising two sets of unidirectional, serial bit channels to transmit data in opposite directions; and
- a peripheral bridge directly coupled to the central processing unit without any intervening Peripheral Component Interconnect (PCI) bus, wherein the peripheral bridge directly conveys an encoded serial bit stream of address bits, data bits, and byte enable information bits of a PCI bus transaction over the first LVDS channel; and
- a second LVDS channel coupled to the connector, comprising two sets of unidirectional, serial bit channels to convey serial bit data in opposite directions.
36. The computer system of claim 35 wherein the second LVDS channel communicates Ethernet protocol signals.
37. The computer system of claim 35 wherein the mass storage device comprises flash memory, directly coupled to the central processing unit through a third LVDS channel comprising two sets of unidirectional, serial bit channels to convey data in opposite directions.
38. The computer system of claim 35 wherein the peripheral bridge comprises an interface controller coupled to Phase-Locked Loop (PLL) clock circuitry, and wherein the interface controller is directly coupled to the first LVDS channel to convey encoded serial bit streams of address and data bits of PCI bus transactions.
39. The computer system of claim 38 wherein the interface controller generates different data transfer rates to convey the encoded serial bit streams of address and data bits of the PCI bus transactions through the first LVDS channel based on different clock frequencies generated by the PLL clock circuitry.
40. The computer system of claim 35 wherein the peripheral bridge comprises an interface controller coupled to Phase-Locked Loop (PLL) clock circuitry, and wherein the interface controller is directly coupled to the first LVDS channel to convey said PCI bus transaction.
41. The computer system of claim 40 wherein the interface controller generates different data transfer rates to convey the PCI bus transaction through the LVDS channel based on different clock frequencies generated by the PLL clock circuitry.
42. A computer, comprising:
- a central processing unit directly coupled to a first Low Voltage Differential Signal (LVDS) channel comprising at least two sets of unidirectional, serial bit channels to convey encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in serial bit streams in opposite directions;
- a graphics subsystem directly coupled to a differential signal channel to convey digital video display signals;
- a connector coupled to the central processing unit through a second Low Voltage Differential Signal (LVDS) channel comprising two unidirectional, differential signal pairs to convey serial bit data in opposite directions.
43. The computer of claim 42 wherein the CPU and graphics subsystem are integrated on a single chip.
44. The computer of claim 43 wherein the second LVDS channel conveys an encoded serial bit stream of address and data bits of a PCI bus transaction.
45. The computer of claim 42 wherein the second LVDS channel conveys an encoded serial bit stream of address and data bits of a PCI bus transaction.
46. The computer of claim 45 wherein the connector further conveys digital video display signals through a differential signal channel, and the connector is configured for coupling to a console through a cable.
47. The computer of claim 42 further comprising a mass storage device directly coupled to the central processing unit, wherein the mass storage device comprises flash memory.
48. A computer system comprising:
- a central processing unit (CPU) comprising an interface controller;
- a first low voltage differential signal (LVDS) channel directly extending from the interface controller, the first LVDS channel comprising two unidirectional, serial bit channels to convey data in opposite directions, wherein each serial bit channel comprises four or more differential signal pairs; and
- a second LVDS channel coupled to a connector, comprising two sets of unidirectional, serial bit channels to convey data in opposite directions;
- wherein the first LVDS channel conveys encoded serial bit streams of address bits, data bits, and byte enable information bits of Peripheral Component Interconnect (“PCI”) bus transactions.
49. The computer system of claim 48 wherein the interface controller is coupled to Phase-Locked Loop (PLL) clock circuitry, and wherein the interface controller generates different data transfer rates to convey PCI bus transactions through the first LVDS channel based on different clock frequencies generated by the PLL clock circuitry.
50. The computer system of claim 49 wherein the second LVDS channel communicates Ethernet protocol traffic.
51. A computer system comprising:
- a central processing unit (CPU);
- a peripheral bridge directly coupled to the CPU without any intervening Peripheral Component Interconnect (PCI) bus;
- a first low voltage differential signal (LVDS) channel directly coupled to the peripheral bridge, comprising two unidirectional, serial bit channels to convey data in opposite directions, wherein each serial bit channels comprises four or more differential signal pairs; and
- a second LVDS channel extending directly from the CPU, comprising two sets of unidirectional, serial bit channels to convey data in opposite directions;
- wherein the first LVDS channel conveys encoded serial bit streams of address bits, data bits, and byte enable information bits of PCI bus transactions.
52. The computer system of claim 51 wherein the peripheral bridge comprises an interface controller coupled to Phase-Locked Loop (PLL) clock circuitry, and wherein the interface controller directly couples to the first LVDS channel to convey said PCI bus transactions.
53. The computer system of claim 52 wherein the interface controller generates different data transfer rates to convey said PCI bus transactions through the first LVDS channel based on different clock frequencies generated by the PLL clock circuitry.
54. A computer system comprising:
- a central processing unit (CPU) comprising an interface controller;
- a first low voltage differential signal (LVDS) channel directly extending from the interface controller, the first LVDS channel comprising two unidirectional, serial bit channels to convey data in opposite directions, wherein each serial bit channel comprises four or more differential signal pairs; and
- a second LVDS channel coupled to a connector, comprising two sets of unidirectional, serial bit channels to convey data in opposite directions; and
- wherein the first LVDS channel conveys an encoded serial bit stream of address and data bits of a Peripheral Component Interconnect (“PCI”) bus transaction.
55. The computer system of claim 54 wherein the interface controller is coupled to Phase-Locked Loop (PLL) clock circuitry, and wherein the interface controller generates different data transfer rates to convey the PCI bus transaction through the first LVDS channel based on different clock frequencies generated by the PLL clock circuitry.
56. The computer system of claim 55 wherein the second LVDS channel communicates Ethernet protocol.
57. A computer system comprising:
- a central processing unit (CPU);
- a peripheral bridge directly coupled to the CPU without any intervening Peripheral Component Interconnect (PCI) bus;
- a first low voltage differential signal (LVDS) channel directly coupled to the peripheral bridge, comprising two unidirectional, serial bit channels to convey data in opposite directions, wherein each serial bit channel comprises four or more differential signal pairs; and
- a second LVDS channel extending directly from the CPU, comprising two sets of unidirectional, serial bit channels to convey data in opposite directions;
- wherein the first LVDS channel conveys an encoded serial bit stream of address and data bits of a PCI bus transaction.
58. The computer system of claim 57 wherein the peripheral bridge comprises an interface controller coupled to Phase-Locked Loop (PLL) clock circuitry, and wherein the interface controller is directly coupled to the first LVDS channel to convey said PCI bus transaction.
59. The computer system of claim 58 wherein the interface controller generates different data transfer rates to convey the PCI bus transaction through the LVDS channel based on different clock frequencies generated by the PLL clock circuitry.
60. A computer comprising:
- a connector for external peripheral data communication;
- a central processing unit (CPU);
- a first Low Voltage Differential Signal (LVDS) channel directly connected to the CPU comprising two unidirectional, serial bit channels that transmit data in opposite directions; and
- a second LVDS channel to convey Universal Serial Bus (USB) protocol traffic through the connector, the second LVDS channel including two unidirectional, serial bit channels that transmit data in opposite direction; and
- wherein the connector further conveys digital video data through a third differential signal channel.
61. The computer of claim 60 wherein the first LVDS channel conveys address and data bits, and byte enable information bits of a Peripheral Component Interconnect (PCI) bus transaction in serial form.
62. A computer comprising:
- a connector for external peripheral data communication;
- an integrated central processing unit and graphics subsystem in a single chip; and
- a first Low Voltage Differential Signal (LVDS) channel comprising two unidirectional, serial bit channels that transmit data in opposite directions;
- wherein the integrated graphics subsystem directly outputs digital video display data to a unidirectional differential signal channel;
- wherein the first LVDS channel conveys Universal Serial Bus (USB) protocol traffic through the connector and wherein the digital video display data couples to the connector.
63. The computer of claim 62 wherein the digital video display data is transmitted through Transition Minimized Differential Signaling (TMDS).
| 3996585 | December 7, 1976 | Hogan et al. |
| 4141068 | February 20, 1979 | Mager et al. |
| 4228496 | October 14, 1980 | Katzman et al. |
| 4453215 | June 5, 1984 | Reid |
| 4570220 | February 11, 1986 | Tetrick et al. |
| 4615039 | September 30, 1986 | Li |
| 4623964 | November 18, 1986 | Getz et al. |
| 4670837 | June 2, 1987 | Sheets |
| 4680674 | July 14, 1987 | Moore |
| 4700362 | October 13, 1987 | Todd et al. |
| 4760276 | July 26, 1988 | Lethellier |
| 4769764 | September 6, 1988 | Levanon |
| 4791524 | December 13, 1988 | Teigen et al. |
| 4799258 | January 17, 1989 | Davies |
| 4872091 | October 3, 1989 | Maniwa et al. |
| 4890282 | December 26, 1989 | Lambert et al. |
| 4918572 | April 17, 1990 | Tarver et al. |
| 4939735 | July 3, 1990 | Fredericks et al. |
| 5056141 | October 8, 1991 | Dyke |
| 5086499 | February 4, 1992 | Mutone |
| 5103446 | April 7, 1992 | Fischer |
| 5187645 | February 16, 1993 | Spalding et al. |
| 5191581 | March 2, 1993 | Woodbury et al. |
| 5198806 | March 30, 1993 | Lord |
| 5227957 | July 13, 1993 | Deters |
| 5251097 | October 5, 1993 | Simmons et al. |
| 5278509 | January 11, 1994 | Haynes et al. |
| 5278730 | January 11, 1994 | Kikinis |
| 5282247 | January 25, 1994 | McLean et al. |
| 5293497 | March 8, 1994 | Free |
| 5311397 | May 10, 1994 | Harshberger et al. |
| 5317441 | May 31, 1994 | Sidman |
| 5317477 | May 31, 1994 | Gillett |
| 5319771 | June 7, 1994 | Takeda |
| 5325517 | June 28, 1994 | Baker et al. |
| 5331509 | July 19, 1994 | Kikinis |
| 5339408 | August 16, 1994 | Bruckert et al. |
| 5355391 | October 11, 1994 | Horowitz et al. |
| 5428806 | June 27, 1995 | Pocrass |
| 5430607 | July 4, 1995 | Smith |
| 5432939 | July 11, 1995 | Blackledge, Jr. et al. |
| 5436857 | July 25, 1995 | Nelson et al. |
| 5436902 | July 25, 1995 | McNamara et al. |
| 5463742 | October 31, 1995 | Kobayashi |
| 5485488 | January 16, 1996 | Van Brunt |
| 5519843 | May 21, 1996 | Moran et al. |
| 5533125 | July 2, 1996 | Bensimon et al. |
| 5537544 | July 16, 1996 | Morsawa et al. |
| 5539616 | July 23, 1996 | Kikinis |
| 5546403 | August 13, 1996 | Caputo et al. |
| 5546463 | August 13, 1996 | Caputo et al. |
| 5550710 | August 27, 1996 | Rahamim et al. |
| 5550861 | August 27, 1996 | Chan et al. |
| 5552776 | September 3, 1996 | Wade et al. |
| 5572441 | November 5, 1996 | Boie |
| 5577205 | November 19, 1996 | Hwang et al. |
| 5578940 | November 26, 1996 | Dillon et al. |
| 5584053 | December 10, 1996 | Kommrusch et al. |
| 5588850 | December 31, 1996 | Pan et al. |
| 5590377 | December 31, 1996 | Smith |
| 5600800 | February 4, 1997 | Kikinis et al. |
| 5603044 | February 11, 1997 | Annapareddy et al. |
| 5606717 | February 25, 1997 | Farmwald et al. |
| 5608608 | March 4, 1997 | Flint et al. |
| 5623637 | April 22, 1997 | Jones et al. |
| 5630057 | May 13, 1997 | Hait |
| 5638521 | June 10, 1997 | Buchala et al. |
| 5640302 | June 17, 1997 | Kikinis |
| 5648762 | July 15, 1997 | Ichimura et al. |
| 5659773 | August 19, 1997 | Huynh et al. |
| 5663661 | September 2, 1997 | Dillon et al. |
| 5673172 | September 30, 1997 | Hastings et al. |
| 5673174 | September 30, 1997 | Hamirani |
| 5680126 | October 21, 1997 | Kikinis |
| 5680536 | October 21, 1997 | Tyuluman |
| 5689654 | November 18, 1997 | Kikinis et al. |
| 5708840 | January 13, 1998 | Kikinis et al. |
| 5721837 | February 24, 1998 | Kikinis et al. |
| 5721842 | February 24, 1998 | Beasley et al. |
| 5724591 | March 3, 1998 | Hara et al. |
| 5737194 | April 7, 1998 | Hopkins et al. |
| 5737524 | April 7, 1998 | Cohen et al. |
| 5742840 | April 21, 1998 | Hansen et al. |
| 5745733 | April 28, 1998 | Robinson |
| 5751711 | May 12, 1998 | Sakaue |
| 5751950 | May 12, 1998 | Crisan |
| 5752080 | May 12, 1998 | Ryan |
| 5764924 | June 9, 1998 | Hong |
| 5774703 | June 30, 1998 | Weiss et al. |
| 5774704 | June 30, 1998 | Williams |
| 5787259 | July 28, 1998 | Haroun |
| 5795228 | August 18, 1998 | Trumbull et al. |
| 5802391 | September 1, 1998 | Hwang |
| 5805903 | September 8, 1998 | Elkhoury |
| 5809262 | September 15, 1998 | Potter |
| 5809538 | September 15, 1998 | Pollmann et al. |
| 5815681 | September 29, 1998 | Kikinis |
| 5819050 | October 6, 1998 | Boehling et al. |
| 5819053 | October 6, 1998 | Goodrum et al. |
| 5822571 | October 13, 1998 | Goodrum et al. |
| 5826048 | October 20, 1998 | Dempsey et al. |
| 5838932 | November 17, 1998 | Alzien |
| 5848249 | December 8, 1998 | Garbus et al. |
| 5857085 | January 5, 1999 | Zhang et al. |
| 5859669 | January 12, 1999 | Prentice |
| 5862350 | January 19, 1999 | Coulson |
| 5862381 | January 19, 1999 | Advani et al. |
| 5878211 | March 2, 1999 | Delagrange et al. |
| 5884049 | March 16, 1999 | Atkinson |
| 5884053 | March 16, 1999 | Clouser et al. |
| 5907566 | May 25, 1999 | Benson et al. |
| 5909559 | June 1, 1999 | So |
| 5930110 | July 27, 1999 | Nishigaki et al. |
| 5933609 | August 3, 1999 | Walker et al. |
| 5935226 | August 10, 1999 | Klein |
| 5941965 | August 24, 1999 | Moroz et al. |
| 5941968 | August 24, 1999 | Mergard |
| 5948047 | September 7, 1999 | Jenkins et al. |
| 5960213 | September 28, 1999 | Wilson |
| 5961623 | October 5, 1999 | James et al. |
| 5965957 | October 12, 1999 | Bourgeois |
| 5968144 | October 19, 1999 | Walker et al. |
| 5971804 | October 26, 1999 | Gallagher et al. |
| 5974486 | October 26, 1999 | Siddappa |
| 5977989 | November 2, 1999 | Lee et al. |
| 5978821 | November 2, 1999 | Freeny |
| 5978919 | November 2, 1999 | Doi et al. |
| 5982363 | November 9, 1999 | Naiff |
| 5982614 | November 9, 1999 | Reid |
| 5987543 | November 16, 1999 | Smith |
| 5991163 | November 23, 1999 | Marconi et al. |
| 5991833 | November 23, 1999 | Wandler et al. |
| 5991844 | November 23, 1999 | Khosrowpour |
| 5999476 | December 7, 1999 | Dutton et al. |
| 5999952 | December 7, 1999 | Jenkins et al. |
| 6002442 | December 14, 1999 | Li et al. |
| 6003105 | December 14, 1999 | Vicard et al. |
| 6006243 | December 21, 1999 | Karidis |
| 6009488 | December 28, 1999 | Kavipurapu |
| 6011546 | January 4, 2000 | Bertram |
| 6012145 | January 4, 2000 | Mathers et al. |
| 6016252 | January 18, 2000 | Pignolet et al. |
| 6025989 | February 15, 2000 | Ayd et al. |
| 6028643 | February 22, 2000 | Jordan et al. |
| 6029183 | February 22, 2000 | Jenkins et al. |
| 6038621 | March 14, 2000 | Gale et al. |
| 6040792 | March 21, 2000 | Watson et al. |
| 6046571 | April 4, 2000 | Bovio et al. |
| 6049823 | April 11, 2000 | Hwang |
| 6052513 | April 18, 2000 | MacLaren |
| 6069615 | May 30, 2000 | Abraham et al. |
| 6070211 | May 30, 2000 | Neal et al. |
| 6070214 | May 30, 2000 | Ahern |
| 6078503 | June 20, 2000 | Gallagher et al. |
| 6088224 | July 11, 2000 | Gallagher et al. |
| 6088620 | July 11, 2000 | Ninomiya et al. |
| 6088752 | July 11, 2000 | Ahern |
| 6091737 | July 18, 2000 | Hong et al. |
| 6104921 | August 15, 2000 | Cosley et al. |
| 6145085 | November 7, 2000 | Tran et al. |
| 6148357 | November 14, 2000 | Gulick |
| 6157534 | December 5, 2000 | Gallagher et al. |
| 6161157 | December 12, 2000 | Tripathi |
| 6161524 | December 19, 2000 | Akbarian et al. |
| 6163464 | December 19, 2000 | Ishibashi et al. |
| 6175490 | January 16, 2001 | Papa et al. |
| 6179489 | January 30, 2001 | So et al. |
| 6188602 | February 13, 2001 | Alexander et al. |
| 6199134 | March 6, 2001 | Deschepper et al. |
| 6202115 | March 13, 2001 | Khosrowpour |
| 6202169 | March 13, 2001 | Razzagne-Ashrafi et al. |
| 6208522 | March 27, 2001 | Manweller et al. |
| 6216185 | April 10, 2001 | Chu |
| 6226700 | May 1, 2001 | Wandler et al. |
| 6256689 | July 3, 2001 | Khosrowpour |
| 6256691 | July 3, 2001 | Moroz et al. |
| 6266539 | July 24, 2001 | Pardo |
| 6289376 | September 11, 2001 | Taylor et al. |
| 6297955 | October 2, 2001 | Frank, Jr. et al. |
| 6301637 | October 9, 2001 | Krull et al. |
| 6304895 | October 16, 2001 | Schneider et al. |
| 6311268 | October 30, 2001 | Chu |
| 6311287 | October 30, 2001 | Dischier et al. |
| 6314522 | November 6, 2001 | Chu et al. |
| 6317329 | November 13, 2001 | Dowdy et al. |
| 6321277 | November 20, 2001 | Andresen et al. |
| 6321335 | November 20, 2001 | Chu |
| 6324605 | November 27, 2001 | Rafferty |
| 6325636 | December 4, 2001 | Hipp et al. |
| 6332180 | December 18, 2001 | Kauffman et al. |
| 6345330 | February 5, 2002 | Chu |
| 6356968 | March 12, 2002 | Kishon |
| 6366951 | April 2, 2002 | Schmidt |
| 6378009 | April 23, 2002 | Pinkston, II et al. |
| 6381602 | April 30, 2002 | Shoroff et al. |
| 6393561 | May 21, 2002 | Hagiwara et al. |
| 6401124 | June 4, 2002 | Yang et al. |
| 6411506 | June 25, 2002 | Hipp et al. |
| 6425033 | July 23, 2002 | Conway et al. |
| 6430000 | August 6, 2002 | Rent |
| 6452789 | September 17, 2002 | Pallotti et al. |
| 6452790 | September 17, 2002 | Chu et al. |
| 6453344 | September 17, 2002 | Ellsworth et al. |
| 6460106 | October 1, 2002 | Stufflebeam |
| 6477593 | November 5, 2002 | Khosrowpour et al. |
| 6487614 | November 26, 2002 | Nobutani et al. |
| 6496361 | December 17, 2002 | Kim et al. |
| 6498361 | December 24, 2002 | Osann, Jr. |
| 6549966 | April 15, 2003 | Dickens et al. |
| 6564274 | May 13, 2003 | Heath et al. |
| 6567877 | May 20, 2003 | Lewis et al. |
| 6570561 | May 27, 2003 | Boesch |
| 6578103 | June 10, 2003 | Hill et al. |
| 6581125 | June 17, 2003 | Lange et al. |
| 6606253 | August 12, 2003 | Jackson et al. |
| 6643777 | November 4, 2003 | Chu |
| 6664377 | December 16, 2003 | Xu |
| 6715100 | March 30, 2004 | Hwang |
| 6718415 | April 6, 2004 | Chu |
| 6725317 | April 20, 2004 | Bouchier et al. |
| 6742068 | May 25, 2004 | Gallagher et al. |
| 6747878 | June 8, 2004 | Hipp et al. |
| 6757748 | June 29, 2004 | Hipp |
| 6900847 | May 31, 2005 | Agneta et al. |
| 6948047 | September 20, 2005 | Maruska et al. |
| 6985967 | January 10, 2006 | Hipp |
| 7017001 | March 21, 2006 | Hill et al. |
| 7020735 | March 28, 2006 | Kikinis |
| 7099981 | August 29, 2006 | Chu |
| 7123660 | October 17, 2006 | Haq et al. |
| 7146446 | December 5, 2006 | Chu |
| 7243173 | July 10, 2007 | Campbell |
| 7266661 | September 4, 2007 | Walmsley |
| 7328297 | February 5, 2008 | Chu |
| 7339786 | March 4, 2008 | Bottom et al. |
| 7363415 | April 22, 2008 | Chu |
| 7363416 | April 22, 2008 | Chu |
| 7376779 | May 20, 2008 | Chu |
| 7480303 | January 20, 2009 | Ngai |
| RE41076 | January 12, 2010 | Chu |
| RE41092 | January 26, 2010 | Chu |
| 7676624 | March 9, 2010 | Chu |
| RE41294 | April 27, 2010 | Chu |
| 7783818 | August 24, 2010 | Sardella et al. |
| 7818487 | October 19, 2010 | Chu |
| 7822895 | October 26, 2010 | Sardella et al. |
| RE41961 | November 23, 2010 | Chu |
| RE42814 | October 4, 2011 | Chu |
| 8041873 | October 18, 2011 | Chu |
| RE42984 | November 29, 2011 | Chu |
| RE43119 | January 17, 2012 | Chu |
| 8090971 | January 3, 2012 | Sarmento |
| RE43171 | February 7, 2012 | Chu |
| 8230145 | July 24, 2012 | Bresniker |
| 8234436 | July 31, 2012 | Chu |
| RE43602 | August 21, 2012 | Chu |
| RE44468 | August 27, 2013 | Chu |
| RE44739 | January 28, 2014 | Chu |
| 8626977 | January 7, 2014 | Chu |
| 8671153 | March 11, 2014 | Chu |
| 8739179 | May 27, 2014 | Tripathi |
| RE44933 | June 3, 2014 | Chu |
| 8756359 | June 17, 2014 | Chu |
| 8977797 | March 10, 2015 | Chu |
| 20010011312 | August 2, 2001 | Chu |
| 20040177200 | September 9, 2004 | Chu |
| 20040268015 | December 30, 2004 | Pettey et al. |
| 20050174729 | August 11, 2005 | Chu |
| 20050182882 | August 18, 2005 | Chu |
| 20050195575 | September 8, 2005 | Chu |
| 20050204083 | September 15, 2005 | Chu |
| 20050246469 | November 3, 2005 | Chu |
| 20060265361 | November 23, 2006 | Chu |
| 20080244149 | October 2, 2008 | Chu |
| 20090083813 | March 26, 2009 | Dolce et al. |
| 20090157858 | June 18, 2009 | Bolan et al. |
| 20090157939 | June 18, 2009 | Chu |
| 20090164684 | June 25, 2009 | Atherton et al. |
| 20090268390 | October 29, 2009 | King et al. |
| 20090292854 | November 26, 2009 | Khoo |
| 20100082874 | April 1, 2010 | Baba et al. |
| 20100167557 | July 1, 2010 | Hoang |
| 20100174844 | July 8, 2010 | Chu |
| 20110007473 | January 13, 2011 | Franz et al. |
| 20110145618 | June 16, 2011 | Andresen et al. |
| 20110208893 | August 25, 2011 | Chu |
| 20120072633 | March 22, 2012 | Elboim |
| 20130013957 | January 10, 2013 | Armstrong et al. |
| 20130024596 | January 24, 2013 | Chu |
| 20130097352 | April 18, 2013 | Chu |
| 20130198430 | August 1, 2013 | Chu |
| 20130346665 | December 26, 2013 | Freking et al. |
| 20140059266 | February 27, 2014 | Ben-Michael et al. |
| 20140195713 | July 10, 2014 | Chu |
| 20150039871 | February 5, 2015 | Shetty et al. |
| 0722138 | July 1996 | EP |
| 6-289953 | October 1994 | JP |
| 6-289956 | October 1994 | JP |
| 7-64672 | March 1995 | JP |
| 7-84675 | March 1995 | JP |
| WO 92/018924 | October 1992 | WO |
| WO 92/18924 | October 1992 | WO |
| WO 94/00970 | January 1994 | WO |
| WO 95/13640 | May 1995 | WO |
| WO 97/00481 | January 1997 | WO |
| WO 97/005618 | February 1997 | WO |
- Boosten, “Transmission Overhead and Optimal Packet Size”, Mar. 11, 1998, printed on: Jan. 28, 2011, 2 pgs.
- 8260 ATM Product Architecture, IBM International Technical Support Organization, Raleigh Center, Sep. 1997, First Edition, International Business Machines Corporation, 220 pages.
- 8265 Nways ATM Switch, Product Description, Sep. 1998, Fifth Edition, International Business Machines Corporation, 141 pages.
- Origin2000 Rackmount Owner's Guide, Document No. 007-3456-003, 1997, Silicon Graphics, Inc., 146 pages.
- QuantumNet, Inc., QuantumNet Product Overview [online], 1996 [retrieved on Nov. 16, 2009], Retrieved from the Internet: <URL: http://web.archive.org/web/19971011194003/www.quantumnet.com/products.htm<, 1 page.
- QuantumNet, Inc., QuantumNet: The Next Generation Computing and Networking Environment [online], 1996 [retrieved on Nov. 16, 2009], Retrieved from the Internet: <URL: http://web.archive.org/web/19971011194123/www.quantumnet.com/qnetovw.htm>, 7 pages.
- QuantumNet, Inc., QuantumNet 6500 Processor Modules [online], 1996 [retrieved on Nov. 16, 2009], Retrieved from the Internet: <URL: http://web.archive.org/web/19971011194317/www.quantum net.com/ds6500.htm>, 4 pages.
- QuantumNet, Inc., QuantumServer Chassis [online], 1996 [retrieved on Nov. 16, 2009], Retrieved from the Internet: <URL: http://web.archive.org/web/19971011194309/www.quantumnet.com/dsq6000.htm>, 3 pages.
- Cubix Corporation, White Paper: Benefits of High-Density Servers [online], 1997 [retrieved on Jul. 31, 2009], Retrieved from the Internet: <URL: http://web.archive.org/web/19970716204215/www.cubix.com/corporate/whitep/densit.htm>, 6 pages.
- Cubix Corporation, Datasheet: Single-Board Computers with Pentium Processors [online], 1997 [retrieved on Jul. 31, 2009], Retrieved from the Internet: <URL: http://web.archive.org.web/19970716204717/www.cubix.com/corporate/data/bcp5t.htm>, 5 pages.
- Cubix Corporation, Datasheet: ERS/FT II Server Chassis [online], 1997 [retrieved on Jul. 31, 2009], Retrieved from the Internet: <URL: http://web.archive.org/web/19970716204623/www.cubix.com/corporate/data/ersft2.htm>, 3 pages.
- Cubix Corporation, Cubix ERS/FT II Systems [online], 1997 [retrieved on Jul. 31, 2009], Retrieved from the Internet: <URL: http://web.archive.org/web/19980124213320/www.cubix.com/support/steps/ers-ft2/intro.htm>, 5 pages.
- Cubix Corporation, Cubix Product Catalog, Summer 1995, 56 pages.
- Cubix Corporation, BC Series, Processor Boards Installation Guide, DOC 800A, Aug. 1994, 149 pages.
- Cubix Corporation, ERS/FT II—Enhanced Resource Subsystem/Fault Tolerant II, Nov. 1994, 4 pages.
- Cubix Corporation, Density Series Plug-In Servers, Plug-In Computers for Managed Server Farms, Sep. 15, 1998, 2 pages.
- Cubix Corporation, Cubix Pentium II Plug-In Computers for Density Series Systems, Sep. 15, 1998, 1 page.
- Cubix Corporation, Density Series Multi-Server Systems, Sep. 10, 1999, 4 pages.
- Compaq Computer Corporation, White Paper, “Order and Configuration Guide for Compaq ProLiant Cluster Series F Model 100,” Sep. 1998, pp. 1-8.
- Compaq Computer Corporation, QuickSpecs, Compaq ProLiant Cluster Series F Model 100, (undated), pp. 8-36 to 8-37.
- Compaq Computer Corporation, Compaq Performance Brief, ProLiant 1600 ServerBench Performance Summary, Aug. 1998, pp. 1-7.
- Compaq Computer Corporation, Compaq ActiveAnswers Installation Guide, Installation and Configuration Guide for Linux and Apache Web Server on Compaq Prosignia and ProLiant Servers, May 1999, pp. 1-40.
- Compaq Computer Corporation, Compaq White Paper, “Microsoft Internet Information Server 4.0 on the Compaq ProLiant 6500,” Aug. 1998, pp. 1-14.
- Compaq Computer Corporation, Compaq White Paper, “Accelerating Financial Spreadsheet Simulations with Workstation Clusters,” Oct. 1998, pp. 1-14.
- Compaq Computer Corporation, ProLiant 6500-PDC/O1000 C/S with 4 ProLiant 1850R, TPC-C Rev. 3.4, Report Date: Dec. 22, 1998, pp. 1-3.
- Black Box Corporation, Black Box Network Services, Black Box ServSwitch Duo, Jul. 1998, 52 pages.
- Compaq Computer Corporation, Compaq White Paper, “ServerNet—A High Bandwith, Low Latency Cluster Interconnection,” Sep. 1998, pp. 1-9.
- JL ChatCom, Inc.—Web Site, JL ChatCom, Inc., ChatterBox Communications and Server Solutions [online], 1996 [retrieved on Dec. 2, 2009], Retrieved from the Internet: <URL: http://web.archive.org/web/19970104221841/http://www.jlchatcom.com/>, 1 page.
- JL ChatCom, Inc.—Scaleable Application and Communication Servers, “ChatCom, Inc. Announces Complete Line of Scaleable Application and Communication Servers,” Aug. 30, 1996 [retrieved on Dec. 2, 2009], JL ChatCom, Inc., ChatterBox Communications and Server Solutions [online], Retrieved from the Internet: <URL: http://web.archive.org/web/19970104221932/www.jlchatcom.com/cpofrel.htm>, 4 pages.
- JL ChatCom, Inc.—Highly Adaptable Intranet and Web Servers, “ChatCom, Inc. Announces Highly Adaptable Intranet and Web Servers,” Sep. 3, 1996 [Retrieved on Dec. 2, 2009], JL ChatCom, Inc., ChatterBox Communications and Server Solutions [online], Retrieved from the Internet: <URL: http://web.archive.org/web/19970104221941/www.jlchatcom.com/chat4int.htm>, 2 pages.
- JL ChatCom, Inc., “ChatPower Plus,” 1996 [retrieved on Dec. 2, 2009], JL ChatCom, Inc., ChatterBox Communications and Server Solutions [online], Retrieved from the Internet: <URL: http://web.archive.org/web/19970104222122/www.jlchatcom.com/chatplus.htm>, 3 pages.
- JL ChatCom, Inc., “ChatterBox ChatPower Plus,” (undated) [retrieved on Dec. 2, 2009], JL ChatCom, Inc., ChatterBox Communications and Server Solutions [online], Retrieved from the Internet: <URL: http://web.archive.org/web/19970104222558/www.jlchatcom.com/cpp1.gif>, 1 page.
- JL ChatCom, Inc., “ChatExpress PB5 Series P166 Pentium PIC/ISA CPU Card,” 1996 [retrieved on Dec. 2, 2009], JL ChatCom, Inc., ChatterBox Communications and Server Solutions [online], Retrieved from the Internet: <URL: http://web.archive.org/web/19970104222157/www.jlchatcom.com/chatp599.htm>, 2 pages.
- JL ChatCom, Inc., “ChatExpress—2 Slot,” [retrieved on Dec. 2, 2009], JL ChatCom, Inc., ChatterBox Communications and Server Solutions [online], Retrieved from the Internet: <URL: http://web.archive.org/web/19970104222644/www.jlchatcom.com/exp2ill.gif>, 1 page.
- Ziatech Corporation, Ketris 9000, Aug. 1, 2000, 4 pages.
- Ziatech Corporation, Ketris 9000 System Hardware Manual, 2000, 46 pages.
- Ziatech Corporation, Ketris Server Blade Hardware Manual, 2000, pp. 1-60.
- Ziatech Corporation, Ketris Media Blade Hardware Manual, 2000, pp. 1-17.
- Ziatech Corporation, Ketris Manager Software Manual, 2000, pp. 1-28.
- Ziatech Corporation, Ketris System Management Overview, Jun. 22, 2000, 4 pages.
- Intel Corporation, Intel 82559 Fast Ethernet Multifunction PCI/Cardbus Controller, Networking Silicon, Preview Datasheet, Jan. 1999, 56 pages.
- Ziatech Corporation, STD 32 Star System Multiprocessing Computer System, 1998, 6 pages.
- Ziatech Corporation, ZT 8907 Single Board Computer with IntelDX4 Microprocessor, 1998, 4 pages.
- Ziatech Corporation, ZT 8908 Single Board Computer with Pentium Processor or AMD-K6, 1998, 6 pages.
- Ziatech Corporation, System Designer's Guide, Expanding STD Bus Performance Through Multiprocessing, Apr. 1996, 6 pages.
- Ziatech Corporation, System Designer's Guide, Hot Swap Capability on STD 32 Computers, Jan. 1996, 6 pages.
- Ziatech Corporation, STD 32 zVID2 Local Bus Super VGA/FPD Adapter, Apr. 1996, 2 pages.
- Wolfpack or Microsoft Cluster Services on Star System, (undated), 3 pages.
- Ziatech Corporation, Ziatech Industrial BIOS for CompactPCI and STD 32 Systems, Software Manual for Industrial BIOS Version 4.7, Jul. 27, 1998, 134 pages.
- Ziatech Corporation, “New STD 32 Fault Tolerant Computer Provides Modular Platform for ‘Non-Stop’ Applications,” Feb. 5, 1996. 2 pages.
- Network Engines, Inc., P6000EXP Fault-tolerant Load-Balanced Cluster Server, Sep. 1997, 3 pages.
- Network Engines, Inc., Network Engines ClusterDirector User's Manual, Jun. 1998, 32 pages.
- Eversys Corporation, System 8000 Consolidated Network Server Product Brief, (undated), 2 pages.
- Eversys Corporation, System 8000 Consolidated Server, (undated), [retrieved on Nov. 9, 2009], Retrieved from C: drive <path: file://C:\Documents and Settings\Daniel\M Documents\Eversys\Eversys Web Site Master . . . >, 6 pages.
- Eversys Corporation, System 8000 Consolidated Server Presentation, (undated), 23 pages.
- Eversys Corporation, System 8000 Consolidated Network Server, Pentium II Processor Module User's Guide for Module version P2D-BXT, Jan. 1998, 49 pages.
- Eversys Corporation, Eversys System 8000 Peripheral Sharing Switch (PSS) User's Guide, 1st Edition-Jun. 1997, 2nd Edition-Jan. 1998, 17 pages.
- Eversys Corporation, WebView 8000 version 1.1 User's Guide, Web-Based Management Software to the Eversys System 8000 Consolidated Server, Revision A-Nov. 1998, Revision B-Dec. 1998, 56 pages.
- Eversys Corporation, S8000 Single Module Body Assemby, Oct. 9, 1998, 9 pages.
- Eversys CAPserver Product Brief [online], (undated), [retrieved on Nov. 16, 2009], Retrieved from the Internet: <URL: http://web.archive.org/web/19961104093115/www.eversys.com/CAPbrief.htm>, 10 pages.
- Eversys CAPcard 9500/sa Product Brief [online], (undated), [retrieved on Nov. 16, 2009], Retrieved from the Internet: <URL:http://web.archive.org/web/19961104093144/www.eversys.com/cc95sa_Brief.htm>, 3 pages.
- Evergreen Systems, Inc., “CAPserver, The Communication/Application server for local area networks,” Product Guide, (undated), 18 pages.
- Phillips, J., “9800 Disk Card Design Specification,” May 26, 1998, White Cross Systems Limited, pp. 1-44.
- Phillips, J., “9800 Disk Card Layout Specification,” Apr. 6, 1998, White Cross Systems Limited, pp. 1-22.
- Feakes, L., “Disk Connector Card Functional Requirement Specification,” Jan. 14, 1998, White Cross Systems Limited, pp. 1-4.
- Feakes, L., “Disk Connector Card Layout Specification” Jan. 14, 1998, White Cross Systems Limited, pp. 1-6.
- White Cross Systems Limited, WhiteCross Data Exploration Configuration and Maintenance Manual, Jul. 2000, 354 pages.
- White Cross Systems Limited, WhiteCross Data Exploration, White Paper: R&D 99Q3-01, “WXDES-Technical Information,” Sep. 3, 1999, pp. 1-38.
- White Cross Systems Limited, WhiteCross Configuration & Maintenance Manual, Nov. 2002, Version 5.2, 305 pages.
- Burrow, M., WhiteCross Data Exploration, “A Technical Overview of the WXDES/9800,” Mar. 2, 1999, Revision 2.00, White Cross Systems Limited, pp. 1-90.
- White Cross Systems Limited, WhiteCross WX/DES Hardware Maintenance, 2000, pp. 1-72.
- White Cross Systems Limited, WhiteCross WX/DES Technical Overview, 2000, pp. 1-221.
- Burrow, M., WhiteCross Data Exploration, “A Technical Overview of the WXDES/9800,” Apr. 22, 1999, White Cross Systems Limited, 222 pages.
- Khan, M. F., “Ethernet Switch Card Design Specification,” Mar. 8, 2001, White Cross Systems Limited, pp. 1-32.
- Khan, M. F., “Ethernet Switch Card Layout Specifications,” Mar. 8, 2001, pp. 1-31.
- Smith, B., Processor Backplane Functional Requirement Specification, Jul. 31, 1997, White Cross Systems Limited, pp. 1-11.
- Smith, B., “Processor Backplane Design Specification,” Feb. 3, 1998, White Cross Systems Limited, pp. 1-16.
- Smith, B., “Processor Backplane Layout Specification,” Nov. 12, 1997, White Cross Systems Limited, pp. 1-7.
- Phillips, J., “9800 Processor Card Design Specification,” Feb. 25, 1998, White Cross Systems Limited, pp. 1-41.
- Phillips, J., “9800 Processor Card Layout Specification,” Sep. 29, 1997, White Cross Systems Limited, pp. 1-13.
- Miastkowski, S. (Editor), “A Whale of a System,” Byte, Aug. 1991, 4 pages, vol. 16, No. 8.
- Advanced Micro Devices, Inc., “AMD-K6-III Processor Data Sheet,” 21918B/0, Oct. 1999; 326 pages.
- Black Box Corporation, “Black Box Serve Switch Duo,” Black Box Network Services Manual, Jul. 1998, 52 pages.
- Cisco Systems, Inc., “Cisco AS5800 Universal Access Server Dial Shelf Controller Card Installation and Replacement,” 1997, 28 pages.
- Digital Equipment Corporation, “Digtal AlphaServer 4000 and 4100 systems,” [Brochure], 1998, 4 pages.
- Engineering Department Electronic Industries Association (EIA), “Electrical Characteristics of Balanced Voltage Digital Interface Circuits,” EIA Standard, EIA-422-A, Dec. 1978, 20 pages.
- EIA-485—Not uploaded—Get from Defendants.
- Telecommunications Industries Association, “Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits,” TIA/EIA Standard, TIA/EIA-644, Mar. 1996, 42 pages.
- Huq, S. et al., “An Overview of LVDs Technology,” Application Note 971, Jul. 1998, 6 pages.
- Eversys, “CAPserver Product Brief” [online], [retrieved on Nov. 16, 2009], Retrieved from the Internet: <URL: http://web.archieve.org/web/19961104093115/www.eversys.com/CAPbrief.htm>, 10 pages.
- Eversys, “CAPcard 9500/sa Product Brief,” [online], [retrieved on Nov. 16, 2009], Retrieved from the Internet: <URL: http://web.archieve.org/web/19961104093144/www.eversys.com/cc95sa_Brief.htm>, 3 pages.
- Accton Technology Corporation, “Gigabit Ethernet PCI Adapter,” Cheetah Gigabit Adapter (EN1407-SX), [Brochure], 1999, 2 pages.
- Hewlett Packard Gigabit Ethernet Transceiver Chip, Preliminary Technical Data, [online], May 1997 HDMP-1636 Transceiver and HDMP-1646 Transceiver, Retrieved from the Internet: <URL: www.datasheetcatalog.com>, pp. 711-725.
- Grow, R. et al., “Gigabit Media Independent Interface Proposal,” Nov. 11, 1996, IEEE 802.3Z, Vancouver, 22 pages.
- Part 3: Carrier sense multiple access with collision detection (CSMA/CD) access method and physical layer specifications, IEEE Standard 802.3z, The Institute of Electrical and Electronics Engineers, Inc., Jul. 1998.
- KTI Networks, Inc, “Installation Guide 10/100 Dual-speed Fast Ethernet PCI Adapters,” Doc. No. 990420-KF230TX/2-K, P/N: 750-0124-001, 1999, 24 pages.
- Intel, “21143 PCI/CardBus 10/100 Mb/s Ethernet LAN Controller, Brief Datasheet,” Order No. 278072-001, Oct. 1998, 8 pages.
- Intel, “82559 Fast Ethernet* Multifunction PCI/Cardbus Controller, Networking Silicon, Preview Datasheet,” Document No. 738259-001, Revision 1.0, Jan. 1999, 56 pages.
- Intel, “Pentium® II Processor at 350 MHz, 400 MHz, and 450 MHz, Datasheet,” Order No. 243657-003, Aug. 1998, 83 pages.
- Ellis, S., “IRIS FailSafe™ Administrator's Guide,” Document No. 007-3109-003, Apr. 6, 1997, 212 pages.
- Microsoft Cluster Service Center, “MSCS Basics,” [online], [retrieved on Feb. 7, 2005]. Retrieved from the Internet at <URL: http://www.nwnetworks.com/mscsbasics.htm>, 6 pages.
- NEC, “Server HX4500 User's Guide,” PN: 456-00005-000, Dec. 1998, 160 pages.
- Novell, Inc., “Novell's NetWare 4.1 Momentum Continues—NetWare 4 Now World's Best-Selling Network Operating System,” [online], Mar. 21, 1996, [retrieved on Nov. 16, 2009]. Retrieved from the Internet: <URL: http://www.novell.com/news/press/archive/1996/03/pr96056.html>, 2 pages.
- Chapter 7: Maintaining the NetWare Server, “Supervising the Network,” (undated), pp. 514-517.
- Chapter 7: Designing a Data Protection Plan, (undated), pp. 170-171.
- Concepts, Disk Driver and Disk Duplexing, (undated), pp. 82-83.
- Network Engines, “P6000EXP Fault-tolerant Load-balanced Clustered Server,” 1997, 3 pages.
- PCI Local Bus, “PCI Local Bus Specification,” Dec. 18, 1998, Revision 2.2, 322 pages.
- Micronet, “SP2500R Series EtherFast 10/100 MBPS Adapter User's Guide,” 1999, Document Version 2.0,10 pages.
- Sun Microsystems Computer Company, “Sun™ Enterprise™ 250 Server Owner's Guide,” Jun. 1998, Part No. 805-5160-10, Revision A, 324 pages.
- Sun Microsystems, Inc., “UltraSPARC™-II CPU Module, Datasheet 400 MHz CPU, 2.0 MP E-Cache,” Jul. 1999, 28 pages.
- Sun Microsystems, Inc., White Paper, “Netra™ ft 1800,” Apr. 1999, Revision 09, 50 pages.
- Compaq Computer Corporation, et al., “Universal Serial Bus Specification,” Sep. 23, 1998, Revision 1.1, 327 pages.
- Compaq Computer Corporation, et al., “Universal Serial Bus Specification,” Apr. 27, 2000, Revision 2.0, 650 pages.
- Silicon Graphics International, “Additional Information for: IRIS FailSafe Administrator's Guide (IRIX 6.4),” [online], Document No. 007-3109-003, Published Apr. 6, 1997, [retrieved on Nov. 5, 2009], Retrieved from the Internet: <URL: http://techpubs.sgi.com/library/tpl/cgi-bin/summary.cgi?coll=0640&db=bks&docnumber=. . . >, 2 pages.
- Origin and Onyx Theory of Operations Manual, Document No. 007-3439-002, 1997 Silicon Graphics, Inc., 124 pages.
- QuantumNet, Inc., QuantumNet 6000 Sharing Modules [online], 1996 [retrieved on Nov. 16, 2009], Retrieved from the Internet: <URL: http://web.archive.org/web/19971011194326/www.quantumnet.com/dsq60xx.htm>, 3 pages.
- JL ChatCom, Inc., “ChatTwin,” [retrieved on Dec. 2, 2009], JL ChatCom, Inc,, ChatterBox Communications and Server Solutions [online], Retrieved from the Internet: <URL: http://web.archive,org/web/19970104222209/www.jlchatcom.com/chattwin.htm>, 2 pages.
- Eversys, “Welcome to EverSys” [online], [retrieved on Nov. 16, 2009], Retrieved from the Internet: <URL: http://web.archieve.org/web/19961104092834/www.eversys.com/index2.htm>, 1 page.
- Eversys, “Products” [online], [retrieved on Nov. 16, 2009], Retrieved from the Internet: <URL: http://web.archieve.org/web/19961104093103/www.eversys.com/prodinfo.htm>, 2 pages.
- “Microsoft Press Computer Dictionary, Third Edition,” Microsoft Press, 1997, pp. 199 and 332, Kim Fryer ed.
- Excerpt from “Microsoft Computer Dictionary, 5th Edition”, Microsoft Press, 2002, pp. 96 and 547.
- Excerpt from IEEE 100: The Authoritative Dictionary of IEEE Standards Terms (7th Ed., 2000), pp. 78, 79 and 128.
- Anderson, C.R. et al., “IEEE 1355 HS-Links: Present Status and Future Prospects,” [online], 1998, [retrieved on Aug. 11, 2010], Retrieved from the Internet: <URL: http://www94.web.cern.ch/HIS/dshs/publications/wotug21/hslink/pdf/hslinkpaper.pdf>, 14 pages.
- Mamakos, L. et al., “Request for Comments 2516—A Method for Transmitting PPP Over Ethernet (PPPoE),” [online], 1999, [retrieved on Aug. 18, 2010], Retrieved from the Internet: <URL: http://ttols.ietf.org/html/rfc2516>, 35 pages.
- Haas, S., “The IEEE 1355 Standard: Developments, Performance and Application in High Energy Physics,” Thesis for degree of Doctor of Philosophy, University of Liverpool, Dec. 1998, 138 pages.
- “IEEE Std 1355-1995 Standard for Heterogeneous InterConnect (HIC),” Open Microprocessor systems Initiative (OMI), [online], Oct. 30, 1998, [retrieved on Aug. 6, 2010], Retrieved from the Internet: <URL: http://grouper.ieee.org/groups/1355/index.html>, 6 pages.
- Galles, M., “Spider: A High-Speed Network Interconnect,” IEEE Micro, 1997, pp. 34-39. (6 pages).
- Excerpt from “Microsoft Computer Dictionary, 4th Edition,” Microsoft Press, 1999, pp. 184-185, 241, 432 (7 pages).
- Excerpt from “Microsoft Computer Dictionary, 4th Edition,” Microsoft Press, 1999, pp. 40, 241, 432 (6 pages).
- Excerpt from IEEE 100: The Authoritative Dictionary of IEEE Standards Terms (7th Ed., 2000), pp. 181,304 and 771.
- “Family of VME Technology Specifications,” [online], date unknown, [retrieved on Dec. 29, 2010], Retrieved from the Internet: <URL: http://www.vita.com/specifications.html>, 1 page.
- Excerpt from “Microsoft Computer Dictionary, 5th Edition”, Microsoft Press, 2002, pp. 96, 329, 624 and 625.
- Hill, Golf (editor), “The Cable and Telecommunications Professional's Reference: vol. 1,” Third Edition, Focal Press, 2007, pp. 227-229, 5 pages.
- Intel Corporation, Intel 82559 Fast Ethernet Controller, [retrieved on Mar. 14, 2011], Retrieved from the Internet: <URL: http://www.intel.com/design/network/products/lan/controllers/82559.htm>, 1 page.
- Gruener, J., “Vendors Pack in More Servers,” PC Week, vol. 14, No. 11, Mar. 17, 1997, 2 pages.
- Grigonis, R., “Fault Resilient PC's,” Flatiron Publishing, 1996, 314 pages.
- Microsoft Press Computer User's Dictionary, pp. 82 and 232, Kim Flyer ed., Microsoft Press, 1998, 5 pages.
- IBM Thinkpad Product Information Guide, IBM PC Company, Apr. 28, 1998, 26 pages.
- The American Heritage Dictionary, pp. 536, 607 and 770, Dell Publishing, 1994, 5 pages.
- The New IEEE Standard Dictionary of Electrical and Electronics Terms, Fifth Ed., p. 1236, The Institute of Electrical and Electronics Engineers, Inc., 1993, 3 pages.
- Microsoft Press Computer Dictionary, Third Ed., pp. 96, 313, and 355, Kim Fryer ed., Microsoft Press, 1997, 5 pages.
- IBM Dictionary of Computing, Tenth Ed., pp. 139, 439, 480 and 629, George McDaniel ed., McGraw-Hill, Inc., Aug. 1993, 16 pages.
- IEEE 100: The Authoritative Dictionary of IEEE Standards Terms, Seventh Ed., pp. 703, 704, 856 and 1064, The Institute of Electrical and Electronics Engineers, Inc., 2000, 13 pages.
- Microsoft Press Computer Dictionary, Second Edition, pp. 82, 92, 93 and 260, Alice Smith ed., Microsoft Press, 1994, 13 pages.
- Microsoft Press Computer User's Dictionary, pp. 232, 262, and 275, Kim Fryer ed., Microsoft Press, 1998, 12 pages.
- Feibel, W., Encyclopedia of Networking, Third Edition, p. 265, The Network Press, 2000, 4 pages.
- System 8000, Consolidated Network Server, Product Brief, Eversys Corporation, undated, 2 pages.
- System 8000, Consolidated Server, Presentation, Eversys Corporation, undated, 23 pages.
- IEEE Standard for a High Performance Serial Bus, IEEE Std 1394-1995, The Institute of Electrical and Electronics Engineers, Inc., 1996, 392 pages.
- RLX System 324 Hardware Installation Guide, RLX Technologies, Inc., 2001, 80 pages.
- RLX System 324 Platform Guide: RLX Linux Web Server, RLX Technologies, Inc., 2001, 73 pages.
- RLX System 324 Platform Guide—Windows Powered Web Server—Online, undated, 39 pages.
- RLX System 324 Technical Guide: RLX Control Tower SNMP Implementation, RLX Techologies, 2001, 32 pages.
- RLX System 324 Technical Guide: RLX Control Tower SNMP Implementation, Supplementary Document, Draft, RLX Techologies, May 26, 2001, 48 pages.
- RLX System 324 Technical Guide: RLX Control Tower Backup/Restore, Draft, RLX Techologies, May 18, 2001, 8 pages.
- “RLX Control Tower™ Take Control,” RLX Technologies, undated, 4 pages.
- “RocketLogix Passive I/O Board Topology,” RocketLogix, Inc., Revision 6, May 24, 2000, 1 page.
- “RocketLogix Switched I/O Board Topology,” RocketLogix, Inc., Revision 6, May 24, 2000, 1 page.
- HotDock and Orbiter 3360—Technical Specifications, Product Overview, and Configurations, RocketLogix, Inc., 2000, 4 pages.
- “Redefining Server Economics—Take Control,” RLX Technologies, 2001, 2 pages.
- RLX Technologies Presentation, RLX Technologies, Inc., Apr. 27, 2001, 44 pages.
- “Engineering Design Proposal for RocketLogix, Inc.,” Anigma, Inc., Apr. 19, 2000, 35 pages.
- RLX Blade, RLX Technologies, 2001, 2 pages.
- “RLX System 324 Technical Guide: RLX Red Hat Installation,” RLX Technologies, Inc, 2001, 22 pages.
- “Firmware interface Specification,Orbiter 1680, Orbiter 3360,” Anigma, Inc., Aug. 17, 2000, 16 pages.
- Board Specifications for DataModule Board, DataStation Backplane, DataStation Front Bezel, and BaseStation Backplane, Rev. E, Anigma, Inc., Mar. 2, 2000, 5 pages.
- “Logical Management Process,” RocketLogix, Rev. 5, Apr. 5, 2000, 1 page.
- Eversys Corporation Business Pan, Eversys Corporation, Mar. 21, 1997, 53 pages.
- Gruener, J., “Vendors pack in more servers,” [retrieved on Oct. 22, 2009], Retrieved from the Internet: <URL: http://www.galenet.galegroup.com.ezproxy.sfpl.org.servlet/BCR . . . >, 2 pages.
- System 8000 Web Product Brief, Eversys Corporation, [retrieved on Oct. 22, 2009], Retrieved from the Internet: <URL: http://www.web.archive.org/web/1997052509465/www.eversys.com/Products/S8000/Brief/Index/htm, 6 pages.
- “Eversys Corporation System 8000 Consolidated Server Peripheral Sharing Switch,” Eversys Corporation, undated, 1 page.
- Nicholls, T., “9800 First level design,” White Cross Systems Limited, Mar. 26, 1997, 26 pages.
- Nicholls, T., “9800 System Architecture,” White Cross Systems Limited, Mar. 27, 1997, 28 pages.
- Feakes. L., “Fast Ethernet Switch Card Design Specification,” Revision 4.00, White Cross Systems Limited, Jul. 27, 2010, 23 pages.
- Phillips, J., “9800 Power System Backplane Design Specification,” Revision 1.00, White Cross Systems Limited, Oct. 22, 1997, 11 pages.
- Phillips, J., “9800 Auxiliary PSU Design Specification,” Revision 1.00, White Cross Systems Limited, Oct. 27, 1997, 13 pages.
- Burrow, M., “A Technical Overview of the WXDES/9800,” Whitecross Data Exploration, White Cross Systems Limited, Apr. 21, 1999, 90 pages.
- Burrow, M., “A Technical Overview of the WXDES/9800,” Whitecross Data Exploration, Apr. 21, 1999, Software, 102 pages.
- “Narus and Whitecross Join Forces to Deliver Comprehensive Usage Pattern Analysis Applications for IP Service Providers,” Press Release, Palo Alto, CA, Mar. 27, 2000, 4 pages.
- “Enterprise Application Sewers,” Powerstation Technologies, Inc, undated, 4 pages.
- “P6000 Fault-Tolerant Multiprocessor Application Server,” Powerstation Technologies, Inc., 1996, 3 pages.
- “P6000 IP Application Server,” Network Engines, undated, 1 page.
- “Best of Show 97,” LAN Times, undated, 1 page.
- “GMAC/EDS Case Study,” Network Engines, Inc., undated, 1 page.
- Network Engines P6000 System Guide, Revision C, Network Engines, Inc., Jul. 1998, 89 pages.
- Network Engines P6000EXP System Guide, Revision A, Network Engines, Inc., Jan. 1998, 106 pages.
- Powerstation Technologies P6000 System Guide, Powerstation Technologies, Inc., 1996, 65 pages.
- Network Engines™ SBC2000ST Reference Guide, Rev. A, Network Engines, Inc., Oct. 1998, 178 pages.
- Network Engines™ SBC2000S Reference Guide, Rev. 1.0, Network Engines, Inc., Sep. 1998, 156 pages.
- Network Engines™ SBC2000 User's Manual, Rev. 1.0, Network Engines, Inc., Jul. 1998, 140 pages.
- Network Engines™ SBC1000 User's Manual, Rev. E Draft, Network Engines, Inc., Jun. 1998, 78 pages.
- Pentium Processor™ Network Engines™ P586 Guide, Issue 0.0.20 Preliminary, Network Engines, Inc., Nov. 10, 1997, 58 pages.
- Pentium Processor™ Network Engine™ Manual, Network Engines, Inc., undated, 56 pages.
- “PTI Fault Tolerant System Working Document Specification,” Rev 0, Feb. 26, 1996, 2 pages.
- High Bandwidth Synchronization Bus Arbiter FPGA Implementation, Network Engines, Inc., undated, 49 pages.
- Network Engines Network, Network Engines, Inc. Jun. 22, 1999, 20 pages.
- “HMU—586 Card Guide (Mustang) Pentium PCI,” Issue 0.0.14 Preliminary, HM Systems, Inc., Nov. 18, 1996, 57 pages.
- “TLD Queries Complete Call Detail Record Database with WhiteCross Data Exploration Server,” Data Mining Product Reviews, Feb. 2000, 1 page.
- “WhiteCross Data Exploration Announces ExplorationSTUDIO™,” Press Release, New York, NY, Sep. 2, 1999, 2 pages.
- “WhiteCross Introduces ‘World's Most Powerful Exploration Warehouse System,’” Press Release, New York, NY, Sep. 2, 1999, 2 pages.
- Charlesworth, I., “Technology Audit, Data Exploration Server,” Butler Group, Sep. 1999, 8 pages.
- Groom, P., “WhiteCross 9800 pre-release configuration details and USA Pricing Information,” WhiteCross Systems Limited, Nov. 3, 1998, 4 pages.
- Letter to Barac from Pacotti, Jr. with attachments on WhiteCross Data Exploration undated, 12 pages.
- “Kognitio—Infrastructure Partners,” Retrieved from the Internet on Sep. 8, 2010, Retrieved at URL: www.kognito.com/partners/infrastructure.php, 2 pages.
- RocketLogix Presentation, RocketLogix, Inc., Apr. 6, 2000, 84 pages.
- “Expanding the Reach of the Internet with a New Breed of Web Server Appliances,” RocketLogix, Inc., May 2000, 10 pages.
- Radigan, J., “A Solution to the Power Shortage?” CFO.com, Jan. 17, 2001, [online] Retrieved from the Internet on Dec. 14, 2007, Retrieved at URL: www.cfo.com/article.cfm/2991376?f=singlepage, 3 pages.
- RLX Technologies Presentation, RLX Technologies, Inc., Apr. 27, 2001, 53 pages.
- Goldman, A, “ISP Profiles: RLX Technologies,” ISP-Planet, May 17, 2001, retrieved from the Internet on Jul. 26, 2001, Retrieved at URL: www.isp-planet.com/profiles/2001/rlx.html, 3 pages.
- Rosencrance, L., “IBM agrees to resell RLX high-density servers,” Computerworld, May 8, 2001, retrieved from the Internet on Jul. 25, 2001, Retrieved at URL: www.itworld.com/Comp/1362/CWD010508STO60353/pfindex.html, 3 pages.
- “ChatCom, Inc. Announces Results for the Dec. 31, 1996 Quarter,” ChatCom, Inc., Press Release, Feb. 12, 1997, 2 pages.
- “ChatCom Defines Specification for Future Consolidated Server Products, Rains™ Concept to Accelerate the Adoption of Consolidated Servers,” ChatCom, Inc., Press Release, Mar. 31, 1997, 2 pages.
- “ChatCom, Inc. Announces PentiumPro/200 MHz Server Module, Serve Module Offers Scalability and High Availability for File Server Environments,” ChatCom, Inc., Press Release, Mar. 24, 1997, 3 pages.
- “ChatCom Strengthens Sales Management Team, Three New Sales Directors to Address Growing Demand for ChatCom's ChatterBox™,” ChatCom, Inc., Press Release, Mar. 18, 1997, 2 pages.
- “ChatCom Announces Major Push into International Markets, Significant International Sales Opportunities for ChatCom's Consolidated Server Technology,” ChatCom, Inc., Press Release, Mar. 18, 1997, 2 pages.
- “ChatCom Receives Product Award From LAN Times Magazine, Consolidated Server Product Comparison Puts ChatCom on Top,” ChatCom, Inc., Press Release, Feb. 20, 1997, 2 pages.
- “Astro Sciences Corporation Shareholders Elect Two New Directors, and Vote to Change Corporate Name to ChatCom, Inc.,” Astro Sciences Corporation, Press Release, Feb. 12, 1996, 2 pages.
- “ChatCom, Inc., (Formerly Astro Sciences Corporation) Trades Under New Symbol—NASDAQ/NMS: Chat,” ChatCom, Inc., News Release, Feb. 22, 1996, 1 page.
- “ChatCom Names James B. Mariner President/CEO,” ChatCom, Inc., Press Release, Mar. 7, 1996, 2 pages.
- “ChatCom Selected as Partner in Anixter Race '96 Program and Completes First Part of Financing,” ChatCom, Inc., Press Release, Mar. 26, 1996, 2 pages.
- “Astro Sciences Corporation Announces Results for The Third Quarter,” Astro Sciences Corporation, Press Release, Feb. 8, 1996, 2 pages.
- “Telecom Australia to Receive Astro Sciences/J&L 486 Services,” Astro Sciences Corporatoin, Press Release, Jan. 4, 1996, 1 page.
- “Astro Sciences Receives Microsoft Certification and Announces New Director,” Astro Sciences Corporation, Press Release, Nov. 21, 1995, 2 pages.
- “Astro Sciences Corp. Announces Results for Second Quarter,” Astro Sciences Corporation, Press Release, Nov. 17, 1995, 2 pages.
- “Astro Sciences Corp. Signs Agreement With Storage Computer Corp.,” Astro Sciences Corporation, Press Release, Nov. 7, 1995, 2 pages.
- “Astro Sciences Corporation Appoints Interim President/CEO Board Expanded by Two Seats,” Astro Sciences Corporation, Press Release, Aug. 17, 1995, 1 page.
- “Astro Sciences Corporation Announces Results for the First Quarter of the Fiscal Year,” Astro Sciences Corporation, Press Release, Aug. 3, 1995, 1 page.
- “Astro Sciences Corporation Retains Technology Strategies and Alliance Partners,” Astro Sciences Corporation, News Release, Jun. 29, 1995, 1 page.
- “Astro Sciences Corporation Receives Patent for Network Security and Management,” Astro Sciences Corporation, News Release, Jun. 26, 1995, 1 page.
- “Astro Sciences Corporation Introduces New Generation of Products at PC Expo Show,” Astro Sciences Corporation, Press Release, Jun. 23, 1995, 1 page.
- “Astro Sciences Corporation Announces Results for the Fourth Quarter and the Fiscal Year,” Astro Sciences Corporation, News Release, Jun. 6, 1995, 2 pages.
- “Astro Sciences Corporation Announces Signing of $4 Million Credit Facility With Deutsche Financial Services,” Astro Sciences Corporation, News Release, May 19, 1995, 1 page.
- “Astro Sciences Corporation to Strengthen Management Team Board,” Astro Sciences Corporation, News Release, Apr. 21, 1995, 1 page.
- “J&L Announces their ChatExpress-P75Applications Server at Networks Expo,” J&L Information Systems, Press Release, Feb. 13, 1994, 3 pages.
- “J&L Information Systems Announces two DX4 for their ChatterBox Family of Remote Access Servers,” J&L Information Systems, Press Release, Feb. 13, 1994, 2 pages.
- “J&L Announces the NRS-T10RS™ a Fault Tolerant Applications Server Platform at FOSE,” J&L Information Systems, Press Release, Mar. 20, 1994, 2 pages.
- “J&L Announces their ChatAccess™ Family of Remote LAN Node Servers at Networld+Intertop Las Vegas,” J&L Information Systems, Press Release, Mar. 27, 1994, 2 pages.
- “J&L Announces ChatExpress-P120 Rackmounted Applications Server at PC Expo, New York,” J&L Information Systems, Press Release, Jun. 19, 1994, 2 pages.
- “ChatCom Books Additional Orders with Major Facilities-Based Carrier Companies, ChatCom Products Provide Internet Platforms for Carrier's Customers Worldwide,” ChatCom Inc., Press Release, Mar. 12, 1997, 2 pages.
- “ChatCom Announces Comprehensive VAR Program, Commitment to VARs is Key to Corporate Strategy,” ChatCom, Inc., Press Release, Jan. 13, 1997, 1 page.
- “ChatCom, Inc, Reports Completion of $2.5 Million Private Placement,” ChatCom, Inc., Press Release, Jan. 9, 1997, 2 pages.
- “ChatCom Receives Product Award From LAN Times Magazine, Consolidated Server Product Comparison Puts ChatCom on Top,” ChatCom, Inc, Press Release, Feb. 17, 1997, 2 pages.
- “ChatCom Announces Mass Storage Subsystem, ChatRAID to Address Application Server Market,” ChatCom, Inc., Press Release, Aug. 12, 1996, 1 page.
- “ChatCom, Inc. Announces Commitment to ISO 9001 Quality Certification, ISO 9001 Quality Control Programs are High Priority Company Imperative,” ChatCom, Inc., Press Release, Aug. 1, 1996, 1 page.
- “ChatCom Adds New Senior Management Team Members,” ChatCom, Inc., Press Release, Jul. 2, 1996, 1 page.
- “ChatCom, Inc., Announces Commitment to ISO 9001 Quality Certification, ISO 9001 Quality Control Programs are High Priority Company Imperative,” ChatCom, Inc., Press Release, Aug. 1, 1996, 1 page.
- “ChatCom Announces Mass Storage Subsystem, ChatRAID to Address Application Server Market,” ChatCom, Inc., Press Release, Aug. 14 1996, 2 pages.
- “ChatCom Announces Complete Line of Scaleable Application and Communication Servers,” ChatCom, Inc., Press Release, Aug. 30, 1996 4 pages.
- “ChatCom, Inc. Announces Highly Adaptable Intranet and Web Servers, Servers reduce costs associated with radical change,” Press Release, Sep. 3, 1996, 1 page.
- J&L Introduces Twin Pentium for ChatterBox Systems, J&L Information Systems, Press Release, Jan. 29, 1996, 1 page.
- “ChatterBox/SAS™—Scaleable Access Server™,” J&L Information Systems, Networks Expo—Boston '96, Dec. 22, 1995, 1 page.
- “J&L Information Systems Announces ChatPower-Plus™ a Revolutionary Redundant Power Supply System,” J&L Information Systems, Press Release, Jun. 19, 1995, 2 pages.
- “J&L Announces ChatAccess/PC™, a PCMCIA Based Remote LAN Node Server,” J&L Information Systems, Press Release, Jun. 19, 1995, 2 pages.
- “J&L Announces Two Patents,” J&L Information Systems, Press Release, Feb. 9, 1995, 1 page.
- “J&L Announces their ChatExpress-P100 Rackmounted Applications Server at Networks Expo. Boston,” J&L Information Systems, Press Release, Feb. 13, 1994, 3 pages.
- “J&L Doubles the Rack-Mounted Communications Server Density with ChatVantage/486™,” J&L Information Systems, Press Release, Sep. 11, 1995, 2 pages.
- “Astro Sciences Shareholders Elect Two New Directors, and Vote to Change Corporate Name to Chatcom, Inc.,” Astro Sciences Corporation, Press Release, Feb. 12, 1996, 2 pages.
- “ChatCom, Inc. Announces Results for the Jun. 30 Quarter,” ChatCom, Inc., News Release, Aug. 16, 1996, 2 pages.
- “Introducing the new ChatterBox™ Corporate and Office Series . . . the Power Behind Your Network,” ChatCom, Inc., May 31, 1996, 15 pages.
- “ChatterBox Communications and Server Solutions,” ChatCom, Inc., Mar. 7, 1996, 12 pages.
- “ChatterBox Communications and Server Solutions Products,” ChatCom, Inc., Apr. 24, 1996, 7 pages.
- Lazik, G., “Remote Access—a Historical Perspective,” Network News, vol. 3, No. 7, NPA The Network Professional Association, Jul. 1994, 6 pages.
- Lazik, G., “Remote Access—Part H, Cost Analysis,” Network News, vol. 3, No. 8, NPA The Network Professional Association, Sep. 1994, 5 pages.
- “QuantumNet 6000 Sharing Modifies,” QuantumNet, Inc., 1996, Retrieved from the Internet on Oct. 22, 2008, Retrieved at URL: www.web.archive.org/web/19971011194326/www.quantumnet.com/ds60xx.htm, 3 pages.
- “Plexnet™ Product Overview,” Plexcom, Inc., 1992, 8 pages.
- “Thin Client Servers High-Speed Data Switching Technical Summary,” QuantumNet, Inc., Aug. 29, 2010, 28 pages.
- Facsimile from Pocrass to Paunovich attaching “QuantumNet Network Computing Systems,” Aug. 30, 2010, 8 pages.
- “List of Representative Customers,” Network Engines, Inc., undated, 1 page.
- World Wide System Price Guide, Network Engines, Inc., Sep. 26, 1997, 10 pages.
- P6000 System Price Guide, Network Engines, Inc., Feb. 24, 1998, 9 pages.
- “Venture financing is fuel for Powerstation's Growth Plans,” Mass High Tech Communications, Inc., Jun. 2, 1997, 1 page.
- Grigonis, R., “Life-Saving Computers: Network Engines,” Computer Telephony, Sep. 1997, 1 page.
- Rodgers, A., “NT Clustering Hardware Readied, Vendor Racks up Windows NT Clustering Options at NetWorld+Interop,” Internetweek, Oct. 20, 1997, 1 page.
- “Network Engines Awarded Best of Show at Networld + Interop 97, New company debuts product and wins,” Network Engines, Inc., Press Release, Oct. 14, 1997, 2 pages.
- Network Engines Website, Network Engines, Inc., [retrieved on Feb. 27, 1998], Retrieved from the Internet: <URL: http://www.networkengines.com/>, 12 pages.
- Network Engines, Inc., Company Overview, Aug. 26, 2010, 21 pages.
- “Clustered Servers for Network Based Applications,” Network Engines, Inc., undated, 27 pages.
- Network Engines ClusterDirector Users' Manual, Revision B, Network Engines, Inc., Jun. 1998, 88 pages.
- Network Engines ClusterDirector Users' Manual, Network Engines, Inc., Jan. 1998, 52 pages.
- MP700 User Guide, Issue 0.0.89, Network Engines, Inc., Oct. 16, 1997, 29 pages.
- “ClusterDirector™ Product Description, Fault Tolerance for Industry Standard Processors, Operating Systems, and Applications,” Network Engines, Inc., 1998, 4 pages.
- Maintenance and Service Guide, Compaq Armada 4100 and 4200 Families of Personal Computers, 190 pages.
- “Network Engines Announces New Clustered Application Servers for Web, Thin-Client and Windows NT Enterprise Environments,” Network Engines, Inc., Press Release, Oct. 8, 1997, 3 pages.
- “Network Engines Announces Partnership With Telegration Associates, Inc.,” Network Engines, Inc., Press Release, Dec. 10, 1997, 2 pages.
- “Network Engines Debuts ClusterDirector in Internet/Intranet Load Balanced Environment,” Network Engines, Inc., Press Release, Jan. 27, 1998, 3 pages.
- Stallings, W., “Computer Organization and Architecture—Designing for Performance,” Sixth Edition, Pearson Education, Inc., 2003, pp. 69-89, 23 pages.
- Hill, G. (editor) “The Cable and Telecommunications Professional's Reference: vol. 1,” Third Edition, Focal Press, 2007, pp. 225-229, 7 pages.
- Dell, Inc., White Paper, “PCI Express Technology,” Feb. 2004, pp. 1-11.
- Athavale, A., “How to Lower the Cost of PCI Express Adoption by Using FPGAs,” EETimes Design [online] Apr. 26, 2006, [retrieved on May 3, 2011]. Retrieved from the Internet at <URL: http://www.eetimes.com/General/DisplayPrintViewContent?contentItemID=4014824>, 6 pages.
- Thoms, I., “IBM Hit with $9M Judgment in Server Patent Suit,” Law360 [online], [retrieved on May 3, 2011], Retrieved from the Internet at <URL: http://www.law360.com/articles/229575/print?section=ip>, 2 pages.
- McKenzie, L., “Fujitsu Reaches Deal in Acqis Blade Server IP Spat,” Law360 [online], [retrieved on Jun. 16, 2010], Retrieved from the Internet at <URL: http://ip.law360.com/print_article/175004>, 2 pages.
- PCI Local Bus Specification, PCI Special Interest Group, Production Version, Revision 2.1, Jun. 1, 1995, 298 pages.
- “National Semiconductor Design Guide,” LVDS Owner's Manual, Spring 1997, 65 pages.
- Intel Corporation, “PCI Express* to PCI-X* Bridge Architecture: Where Interface Standards Meet,” 2003, 8 pages.
- Desai, D. M. et al., “BladeCenter system overview,” IBM Journal of Research and Development, vol. 49, No. 6, Nov. 2005, pp. 809-821, 13 pages.
- Spring, T., “Top of the News—Broadband Users Still Sing the Blues,” PC World, Jun. 2001, pp. 42-54, 13 pages.
- San Jose Mercury News, “Business & Stocks—Top Stories from The Mercury News,” Jun. 28, 2001, [online], [retrieved on Jun. 30, 2001], Retrieved from the Internet at <URL: http://www0.mercurycenter.com/premium/business/docs technews28.htm>, 5 pages.
- “iMod Pad,” Wired Magazine, Mar. 2001, 1 page.
- Kunzman, A. J., et al., “1394 High Performance Serial Bus: The Digital Interface for ATV,” IEEE Transactions on Consumer Electronics, vol. 41, No. 3, Aug. 1995, pp. 893-900, 9 pages.
- Parkes, S. M., “High-Speed, Low-Power, Excellent EMC: LVDS for On-Board Data Handling,” Proceedings of 6th International Workshop on Digital Signal Processing Techniques for Space Applications, IEEE, Sep. 1998, 13 pages.
- Yen, C-S, et al., “G-Link: A Chipset for Gigabit-Rate Data Communication,” Hewlett-Packard Journal, Oct. 1992, 18 pages.
- “NX440LX Motherboard Technical Product Specification,” Intel, Aug. 1997, 76 pages.
- “Universal Serial Bus Specification,” Compaq, Digital Equipment Corporation, IBM, Intel, Microsoft, NEC, and Northern Telecom, Revision 10, Jan. 15, 1996, 268 pages.
- “SQL Server and NT Cluster Manager Availability Demo,” Microsoft WindowsNT Server, Microsoft Server Programmer Developers Conference, Nov. 4-6, 1996, 15 pages.
- Agerwala, T. et al., “SP2 System Architecture,” IBM Systems Journal, 1995, vol. 34, No. 2, pp. 152-184.
- CETIA Brochure, “CETIA PowerEngine CVME 603e,” CETIA Real-Time Intelligence [online], [retrieved on Feb. 15, 2006]. Retrieved from the Internet at <URL: http://www.cetia.com/ProductAddOns/wp-47-01.pdf>, 6 pages.
- MPL Brochure, “The First Rugged All-in-One Industrial 486FDX-133 MHz PC,” MPL [online], [retrieved on Feb. 16, 2006]. Retrieved from the Internet at <URL: http://www.mpl.ch/DOCs/ds48600.pdf>, 2 pages.
- MPL Brochure, “IPM 486/IPM5 User Manual,” MPL [online], [retrieved on Feb. 15, 2006]. Retrieved from the Internet at <URL: http://www.mpl.ch/DOCs/u48600xd.pdf>, 13 pages.
- Snyder, J., “Better Management Through Consolidation,” Aug. 18, 1997, Network World [online], [retrieved on Jun. 22, 2004]. Retrieved from the Internet at <URL: http://www.opus1.com/www.jms/nw-con-0818rev.html.>, pp. 1-6.
- Bernal, C., “PowerSMP Series 4000,” Mar. 1998, Windows & .NET Magazine [online], [retrieved on Jun. 22, 2004]. Retrieved from the Internet at <URL: http://www.winnetmag.com/Windows/Article/ArticleID/3095/3095.html>, 2 pages.
- Cragle, J., “Density System 1100,” May 1999, Windows & .NET Magazine [online], [retrieved Jun. 21, 2004]. Retrieved from the Internet at <URL: http://www.winnetmag.com/Windows/Article/ArticleID/5199/5199.html, 3 pages.
- Feldman, J., “Rack Steady: The Four Rack-Mounted Servers That Rocked Our Network,” Network Computing [online], [retrieved on Jun. 23, 2004]. Retrieved from the Internet at <URL: http://www.networkcomputing.com/shared/printArticle.jhtml?article=/910/910r3side1.htm>, 3 pages.
- Fetters, D., “Cubix High-Density Server Leads the Way With Standout Management Software,” Feb. 8, 1999, Network Computing [online], [retrieved on Jun. 23, 2004]. Retrieved from the Internet at <URL: http://www.nwc.com/shared/printArticle.jhtm?article=/1003/1003r3full.html&pub=nwc>, 5 pages.
- Gardner, M. et al, “A Server Condominium—Eversys System 8000 Shrinks Footprints and Performance,” LAN Times [online], [retrieved on Jun. 23, 2004]. Retrieved from the Internet at <URL: http://www.lantimes.com/testing/98jun/806a042a.html>, 3 pages.
- Harrison, D., “VME in the Military: The M1A2 Main Battle Tank Upgrade Relies on COTS VME,” Feb. 9, 1998, pp. 1-34.
- Williams, D., “Consolidated Servers—Redundancy, Convenience, and Protection Define Consolidated Servers,” Product Comparison: Feb. 17, 1997, LAN Times [online], [retrieved on Jun. 23, 2004]. Retrieved from the Internet at <URL: http://www.lantimes.com/testing/97/compare/pcconsol.html>, 2 pages.
- Williams, D., “Executive Summary: Consolidate Now,” Feb. 17, 1997, LAN Times [online], [retrieved on Jun. 23, 2004]. Retrieved from the Internet at <URL: http://www.lantimes.com/testing/97feb/702b064a.html>, 2 pages.
- Williams, D., “Top Scores for Useability and Openness—Ease of Use, Installation, and Administration Combine with Off-The-Shelf Components in Ideal Consolidated Server,” Feb. 17, 1997, LAN Times [online], [retrieved on Jun. 23, 2004], Retrieved from the Internet at <URL: http://www.lantimes.com/testing/97feb/702b070a.html>, 2 pages.
- Williams, D., “ChatCom, Inc. Chatterbox,” Feb. 17, 1997, LAN Times [online], [retrieved on Jun. 23, 2004]. Retrieved from the Internet at <URL: http://www.lantimes.com/testing/97feb/702b066a.html>, 3 pages.
- Williams, D., “Eversys Corp. System 8000,” Feb. 17, 1997, LAN Times [online], [retrieved on Jun. 22, 2004]. Retrieved from the Internet at <URL: http://www.lantimes.com/testing/97feb/702b070b.html>, 4 pages.
- Williams, D., “Cubix Corp. ERS/FT II,” Feb. 17, 1997, LAN Times [online], [retrieved on Jun. 23, 2004]. Retrieved from the Internet at <URL: http://www.lantimes.com/testing/97feb/702b068b.html>, 4 pages.
- Crystal Advertisement, “Rackmount Computers,” © 2000-2004, Crystal Group, Inc. [online], [retrieved on Jun. 17, 2004]. Retrieved from the Internet at <URL: http://www.crystalpc.com/products/roservers.asp>, 8 pages.
- Crystal Advertisement, “QuickConnect® Cable Management,” © 2000-2004, Crystal Group, Inc. [online], [retrieved on Jun. 17, 2004]. Retrieved from the Internet at <URL: http://www.crystalpc.com/products/quickconnect.asp>, 4 pages.
- Cubix Product Brochure, “Density System,” © 2000, Cubix [online], [retrieved on Jun. 22, 2004]. Retrieved from the Internet at <URL: http://64.173.211.7/support/techinfo/system/density/density10.htm>, 3 pages.
- Cubix Product Brochure, “Density System, Technical Specifications,” © 2000, Cubix [online], [retrieved on Jun. 22, 2004]. Retrieved from the Internet at <URL: http://64.173.211.7/support/techinfo/system/density/info/spec.htm>, 2 pages.
- Cubix Product Manual, “Density System,” Chapter 1—Introduction, © 2000, Cubix [online], [retrieved on Jun. 22, 2004]. Retrieved from the Internet at <URL: http://64.173,211.7/support/techinfo/manuals/density/Chap-1.htm>, 5 pages.
- Cubix Product Manual, “Density System,” Chapter 2—Installation, © 2000, Cubix [online], [retrieved on Jun. 22, 2004]. Retrieved from the Internet at <URL: http://64.173.211.7/Support/techinfo/manuals/density/Chap-2.htm>, 9 pages.
- Cubix Product Manual, “Density System,” Chapter 3—Operation, © 2000, Cubix [online], [retrieved on Jun. 22, 2004]. Retrieved from the Internet at <URL: http://64.173.211.7/support/techinfo/manuals/density/Chap-3.htm>, 4 pages.
- Cubix Product Manual, “Density System,” Chapter 4—Maintenance and Repair, © 2000, Cubix [offline], [retrieved on Jun. 22, 2004]. Retrieved from the Internet at <URL: http://64.173.211.7/support/techinfo/manuals/density/Chap-4.htm>, 5 pages.
- Cubix, “Click on the front panel that matches your system,” © , Cubix [online], [retrieved on Jun. 22, 2004]. Retrieved from the Internet at <URL: http://64.173.211.7/support/techinfo/system/density/density.htm>, 1 page.
- Cubix, “What are Groups?,” © 2000, Cubix [online], [retrieved on Jun. 22, 2004], Retrieved from the Internet at <URL: http://64.173.211.7/support/techinfo/system/density/info/groups.htm>, 3 pages.
- Cubix Product Brochure, “SP 5200XS Series Plug-in Computers,” © 2000, Cubix [online], [retrieved on Jun. 22, 2004]. Retrieved from the Internet at <URL: http://64.173.211.7/support/techinfo/bc/sp5200xs/intro.htm>, 2 pages.
- Cubix Product Brochure, “SP 5200XS Series Technical Specifications,” © 2000, Cubix [online], [retrieved on Jun. 22, 2004]. Retrieved from the Internet at <URL: http://64.173.211.7/support/techinfo/bc/sp5200xs/spec.htm>, 2 pages.
- Cubix Product Manual, “SP 5200 Series,” Chapter 1—Introduction, © 2000, Cubix [offline], [retrieved on Jun. 22, 2004]. Retrieved from the Internet at <URL: http://64.173.211.7/support/techinfo/manuals/sp5200/chap-1.htm>, 3 pages.
- Cubix Product Manual, “SP 5200 Series,” Chapter 2—Switches & Jumpers, © 2000, Cubix [online], [retrieved on Jun. 22, 2004]. Retrieved from the Internet at <URL: http://64.173.211.7/support/techinfo/manuals/sp5200/chap-2.htm>, 3 pages.
- Cubix Product Manual, “SP 5200 Series,” Chapter 3—Installation, © 2000, Cubix [online], [retrieved on Jun. 22, 2004], Retrieved from the Internet at <URL: http://64.173.211.7/support/techinfo/manuals/sp5200/chap-3.htm>, 4 pages.
- Cubix Product Manual, “SP 5200 Series,” Chapter 4—Technical Reference, © 2000, Cubix [online], [retrieved on Jun. 22, 2004]. Retrieved from the Internet at <URL: http://64.173.211.7/support/techinfo/manuals/sp5200/chap-4.htm>, 3 pages.
- Cubix product Brochure, “DP 6200 ‘D’ Series Plug-in Computers,” Cubix [online], [retrieved on Jun. 22, 2004]. Retrieved from the Internet at <URL: http://64.173.211.7/support/techinfo/bc/dp/6200d/intro/htm>, 2 pages.
- Cubix, “Installing DP or SP Series Boards,” © 2000, Cubix [online], [retrieved on Jun. 22, 2004]. Retrieved from the Internet at <URL: http://64.173.211.7/support/techinfo/system/density/info/pic-inst.htm>, 2 pages.
- Cubix, “Powering On/Off or Resetting Plug-in Computers in an Density System,” © 2000, Cubix [online], [retrieved on Jun. 22, 2004]. Retrieved from the Internet at <URL: http://64.173.211.7/support/techinfo/system/density/info/power.htm>, 2 pages.
- Cubix, “Multiplexing Video, Keyboard & Mouse with Multiple Density Systems,” © 2000, Cubix [online], [retrieved on Jun. 22, 2004]. Retrieved from the Internet at <URL: http://64.173.211.7/support/techinfo/system/density/info/vkm-mux.htm>, 2 pages.
- eBay Advertisement, Total IT Group, “Network Engines P6000 EXP Dual PII 400,” eBay [online], [retrieved on Jun. 25, 2004]. Retrieved from the Internet at <URL: http://cgi.ebay.com/we/eBayISAPI.dll?ViewItem&item=5706388046&sspagename=STRK%3AMEBI%3AIT&rd=1>, 1 page.
- “Features Chart,” Feb. 17, 1997, LAN Times [online], [retrieved on Jun. 23, 2004]. Retrieved from the Internet at <URL: http://www.lantimes.com/testing/97feb/702b072a.html>, 3 pages.
- Galitzine, G., “Industrial Computers,” Apr. 1999, Internet Telephone Roundup [online], [retrieved on Jun. 23, 2004], Retrieved from the Internet at <URL: http://www.tmcnet.com/articles/itmag/0499/0499roundup.htm>, 5 pages.
- Crystal Group Press Release, “Crystal Group Products Offer Industrial PCs With Built-In Flexibility,” Mar. 1, 1997, Crystal Group Inc. [online], [retrieved on May 14, 2004]. Retrieved from the Internet at <URL: http://www.crystalpc.com/news/pressreleases/prodpr.asp>, 2 pages.
- DY 4 Systems, Inc. Press Release, “Enhanced COTS SBC from DY 4 Systems Features 116MHz Pentium (TM) Processor,” Apr. 8, 1998, [online]. Retrieved from the Internet at <URL: http://www.realtime-info.be/VPR/layout/display/pr.asp?/PRID=363>, 2 pages.
- DY 4 Systems, Inc. Product Brochure, “SVME/DMV-192 Pentium® II Single Board Computer,” Revision D Jun. 1999, pp. 1-9.
- Eversys Corporation Web Product Brief, “System 8000,” Bomara Associates [online], [retrieved on Jun. 22, 2004]. Retrieved from the Internet at <URL: http://www.bomara.com/Eversys/brief/Default.htm>, 4 pages.
- Cubix Product Brochure, “ERS/FT II System (includes PowerSMP and RemoteServ/IS),” © 2000, Cubix [online], [retrieved on Jun. 22, 2004]. Retrieved from the Internet at <URL: http://64.173.211.7/support/techinfo/system/ersft2/ersft2.htm>, 4 pages.
- Cubix Product Manual, “ERS II and ERS/FT II,” Chapter 3, System Components, © 1997, Cubix [online], [retrieved on Jun. 22, 2004]. Retrieved from the Internet at <URL: http://64.173.211.7/support/techinfo/manuals/ers2/ers2-c3.htm>, 21 pages.
- Cubix Product Manual, “ERS II and ERS/FT II,” Chapter 6, Component Installation, © 1997, Cubix [online], [retrieved on Jun. 22, 2004]. Retrieved from the Internet at <URL: http://64.173.211.7/support/techinfo/manuals/ers2/ers2-c6.htm>, 18 pages.
- NT Enterprise, NT Product Pipeline—Hardware, “Cubix PowerSMP Series 4000,” Nov. 1997, Windows Magazine [online], [retrieved on Jun. 22, 2004]. Retrieved from the Internet at <URL: http://www.techweb.com/winmag/library/1997/1101/ntent008.htm>, p. NT07, 1 page.
- Eversys Corporation Slide Presentation, “Eversys System 8000 Consolidated Network Server, Market and Product Overview,” Product to be Released Mar. 1, 2007, [online]. Retrieved from the Internet at <URL: http://eversys.com>, 20 pages.
- Cubix Customer Service Support System, “Click on the Front Panel That Matches Your Systems,” © 2000, cubix [online], [retrieved on Jun. 22, 2004]. Retrieved from the Internet at <URL: http://64.173.211.7/support/techinfo/density/density.htm>, 1 page.
- International Search Report for International Patent Application No. PCT/US99/09369, dated Nov. 16, 1999, 7 pages.
- International Preliminary Examination Report for International Patent Application No. PCT/US99/09369, dated Jul. 5, 2000, 4 pages.
- IBM Corporation, “Grounding Spring for Peripheral Device and Bezel Bracket,” IBM Technical Disclosure Bulletin, Nov. 1, 1993, vol. 36, No. 11, 2 pages.
- Digital Semiconductor Product Brief, “21152 PCI-to-PCI Bridge,” Feb. 1996, 6 pages.
- Intel Corporation Architectural Overview, “Intel 430TX PCISET: 82439TX System Controller (MTXC),” Feb. 1997, 4 pages.
- Intel Corporation Architectural Overview, “Intel 82371AB PCI-to-ISA/IDE XCEL—ERATOR (PIIX4),” Apr. 1997, 3 pages.
- Intel Corporation Advance Information, “Intel 440LX AGPSET: 82443LX PCI A.G.P. Controller (PAC),” Aug. 1997, 4 pages.
- National Semiconductor, DS90CR215/DS90CR216 +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link-66 MHz, Jul. 1997, 2 pages.
- National Semiconductor Product Folder, “DS90CR215 Plus-3.3V Rising Edge Data Strobe LVDS 21-Bit Channel and Link—66 MHz,” National Semiconductor Corporation [online], [retrieved on Oct. 30, 1997]. Retrieved from the Internet at <URL: http://www.national.com/search/search.cgi/design?keywords=DS90CR215>, 2 pages.
- Video Electronics Standards Association (VESA), Plug and Display (P&D) Standard, P&D and Digital Transition Minimized Differential Signaling (TMDS) Video Transmission Overview, 1997, Version 1, Revision 0, pp. 13 & 31-34.
- Liquorman, M., “Convergent Technologies Had This Idea,” Dec. 5, 1997, Jesse Berst's Anchor Desk [online], [retrieved on Jul. 10, 1998]. Retrieved from the Internet at: <URL: http://www.zdnet.com/anchordesk/talkback/talkback_56555.html>, 1 page.
- Berst, J., “Hope For The Modular PCs We All Really Want,” Dec. 5, 1997, Jesse Berst's Anchor Desk [online], [retrieved on Jul. 10, 1998]. Retrieved from the Internet at: <URL: http://www.zdnet.com/anchordesk/story_1504.html>, 3 pages.
- Boyd-Merritt, R., “Upgradable-PC Effort Takes Divergent Paths,” EE Times—Headline News [online], [retrieved on Jul. 31, 1998]. Retrieved from the Internet at : <URL: http://techweb.cmp.com/eet/news/97/949news/effort.html>, 3 pages.
- Faegre, D. S. et al., “CTOS Revealed—Unisys' Best-Kept Secret is an Operating System Built for Distributed Business Applications,” Dec. 1994, Core Technologies, Byte [online], [retrieved on Jul. 10, 1998]. Retrieved from the Internet at: <URL: http://www.byte.com/art/9412/sec13/art2.htm>, 6 pages.
- Spang, K., “Component House: Design Technology for ‘PCs in a Snap’—NeoSystems Offers Building Blocks,” Computer Reseller News, Apr. 21, 1997, Issue: 732, Section: Channel Assembly, TechWeb [online], [retrieved on Jul. 31, 1998]. Retrieved from the Internet at: <URL: http://www.techweb.com/se/directlink.cgi?CRN19970421S0054>, 2 pages.
- “Think Modular,” Jun. 10, 1997, PC Magazine [online], [retrieved on Jul. 31, 1998]. Retrieved from the Internet at: <URL: wysiwyg://60/http://homezdnet.com/pcmag/issues/1611/pcmg0072.htm>, 1 page.
- Boosten, M., “Transmission Overhead and Optimal Packet Size,” [online], [retrieved on Jan. 28, 2011]. Retrieved from the Internet at <URL: http://hsi.web.cern.ch/HSI/dshs/publication/wotug21/dsnic/html/node9.html>, Mar. 11, 1998, 2 pages.
- Horst, Robert W., “Tnet: A Reliagble System Area Network,” IEEE Micro 15(1):37-45 (1995).
- P1394B (Gagabit 1394) Draft 1.33, Institute of Electrical and Electrical Electronics Engineers, Inc., Feb. 10, 1998, 4 pages.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft 0.03, Insfitute of Electrical and Electronics Engineers, Inc., pp. 1-54, Jun. 11, 1997.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft .011, Institute of Electrical and Electronics Engineers, Inc., pp. 1-174, Jul. 1, 1998.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft .012, Institute of Electrical and Electronics Engineers, Inc., pp. 1-205, Aug. 14, 1998.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft .013, Institute of Electrical and Electronics Engineers, Inc., pp. 1-204, Sep. 4, 1998.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft 016, Institute of Electrical and Electronics Engineers, Inc. pp. 1-200, Feb. 5, 1999.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft .87, Institute of Electrical and Electronics Engineers, Inc., pp. 1-346, Sep. 28, 1999.
- Gustavson and Li, “The Scalable Coherent Interface (SCIM),” IEEE Communications Magazine, pp. 52-63 (1996).
- White Paper, Compaq ServerNet II SAN Interconnect for Scalable Computing Clusters, pp. 1-9, Jun. 2000.
- ServerNet Technology Product Description, ServerNet Switch 1 Data Sheet, pp. 1-4, Feb. 1998.
- Yalamanchili and Duato (Eds.), “Parallel Computing Routing and Communication,” Second International Workshop, PCRCW97, Atlanta, GA, 120-135 pages, Jun. 26-27, 1997.
- RM600 E (Reliant UNIX) Operating Manual,Siemens AG, pp. 1-217 (1999).
- WhiteCross Data Exploration, Configuration and Maintenance Manual, 354 pages (1999).
- “Achieving High Availability with Microsoft Windows NT and AviiOn Servers,” A Technology Overview, retrieved online, Mar. 10, 2016, 8 pages.
- “Introduction: Data General Enterprise Systems,” Assessing AV 2000 Performance,retrieved online, Mar. 10, 2016, 4 pages.
- “AV 20000 and ccNUMA: Beyond the Application Bottleneck,” A Data General White Paper, retrieved online, Mar. 10, 2016, 2 pages.
- “Data General's NUMALiiNE Technology: The Foundation for the AV 25000 Server,” A Data General White Paper, retrieved online, Mar. 10, 2016, 8 pages.
- “Global Availability with Clustered AViiON systems brings new levels of service to open enterprise customers,” retrieved online, Mar. 10, 2016, 14 pages.
- “Lights-out Operations Keepingt the Enterprise Online All the Time,” retrieved online, Mar. 10, 2016, 9 pages.
- “Mainframe Migration,” A Data General White Paper, retrieved online, Mar. 10, 2016, 11 pages.
- Clark, R., “SCI Interconnect Chipset and Adapter: Budding Large Scale Enterprise Servers with Pentium II Xeon SHV Nodes,” retrieved online, Mar. 10, 2016, 9 pages.
- “The 64-bit Question: Very Large Memory Support—How Much is Enough?” A Data General White Paper, retrieved online, Mar. 10, 2016, 7 pages.
- “Transition to the Data General Intel Platform,” Technology Overview, retrieved online, Mar. 10, 2016, 7 pages.
- “DG/UX Clusters: Maximizing Availibility and Scalability; Simplifying Systems Management,” retrieved online, Mar. 10, 2016, 18 pages.
- CCNUMA: NUMALiiNE Systems online brochure, retrieved online, Mar. 10, 2016, 3 pages.
- “NUMA System Architectures will Extend Performance of ‘Commodity’ SMP,” © Data General Corporation, 1995, 4 pages.
- “Standard High-Volume Servers: The New Building Block,” © Data General Corporation, 1995, 7 pages.
- “DG/UX Release 4.1 Systems Software UNIX for the Enterprise,” retrieved online, Mar. 10, 2016, 22 pages,
- Gustad, P., et al., “The Dolphin D330 Cluster Adapter Card,” Dolphin Interconnect Solutions AS, Proceedings of the IEEE International Conference on Cluster Computing (Cluster'00), 2 pages.
- “Data General,” AViiON, AV2500, 6 pages.
- Brock, B., et al, “Windows NT in a ccNUMA System,” IBM Austin Research Laboratory, pp. 1-12.
- AViiON AV 20000 Enterprise Service, online brochure, retrieved online, Mar. 10, 2016, 9 pages.
- AViiON AV 20000 Quick Clusters, online brochure, retrieved online, Mar. 10, 2016, 3 pages.
- “AV 20000 Server,” Technical Overview, retrieved online, Mar. 10, 2016, 18 pages.
- Hellwagner, Hermann et al., “SCI: Scalable Coherent Interface,” 1998, part 1, pp. 1-200.
- Hellwagner, Hermann et al., “SCI: Scalable Coherent Interface,” 1998, part 1, pp. 200-496.
- Baker, William E. et al., “A Flexible ServerNet-based Fault-Tolerant Architecture,” Tandem Computers Incorporated, 1995 IEEE, 10 pages.
- “ServerNet Architecture,” Tandem, Part No. 12981, Tandem Computers Incorporated © 1996, 42 pages.
- “NonStop Himalaya S7000 and S70000 Servers,” NonStop Servers Configuation and Odering Information, Dec. 1997, 34 pages.
- Garcia, David et al., “ServerNet™ II,” PCRCW, Jun. 24, 1997, 14 pages.
- Fuller, Sam, “The Opportunity for Sub Microsecond Interconnects for Processor Connectivity,” Technology Comparisons, RapidIO®, retrieved online, May 7, 2015, 11 pages.
- Horst, Robert, “SAN and STAN Architectures for Cluster Communications,” Tandem Computers, a Compaq Company, Server I/O '98, Jan. 27-28, 1998, 20 pages.
- “IEEE Standard fpr Scalable Coherent Interface (SCI),” IEEE STD 1596-1992, © 1993 Institute of Electrical and Electronics Engineers, Inc., 253 pages.
- Horst, Robert W. et al., “ServerNet SAN I/O Architecture,” Hot Interconnects V, 1997, 8 pages.
- Horst, Robert W., TNet: A Reliable System Area Network, Tandem Computers Incorporated © 1995, 13 pages.
- Office Action for U.S. Pat. No. 6,718,415, dated Oct. 10, 2002, 7 pages.
- Office Action for U.S. Pat. No. 6,718,415, dated Jan. 29, 2003, 7 pages.
- Office Action for U.S. Pat. No. 6,718,415, dated Jun. 4, 2003, 8 pages.
- Office Action for U.S. Pat. No. 7,363,415, dated Apr. 12, 2007, 23 pages.
- Office Action for U.S. Pat. No. 7,328,297, dated Feb. 8, 2007, 5 pages.
- Office Action for U.S. Pat. No. 7,328,297, dated Jul. 12, 2007, 13 pages.
- Office Action for U.S. Pat. No. 7,363,416, dated Apr. 12, 2007, 23 pages.
- Office Action for U.S. Pat. No. 7,376,779, dated Sep. 28, 2007, 24 pages.
- Office Action for U.S. Pat. No. 7,676,624, dated Dec. 1, 2008, 8 pages.
- Office Action for U.S. Pat. No. 7,818,487, dated Sep. 29, 2009, 10 pages.
- Office Action for U.S Publication No. 2010/0174844, dated Oct. 28, 2010, 11 pages.
- Office Action for U.S. Appl. No. 13/087,912, dated Sep. 16, 2011, 11 pages.
- Office Action for U.S. Appl. No. 13/087,912, dated Mar. 13, 2012, 10 pages.
- Office Action for U.S. Appl. No. 13/560,924, dated Oct. 3, 2013, 10 pages.
- Office Action for U.S. Appl. No. 13/649,084, dated Sep. 11, 2014, 7 pages.
- Office Action for U.S. Appl. No. 13/744,287, dated Dec. 5, 2013, 20 pages.
- Office Action for U.S. Appl. No. 14/209,922, dated Jun. 3, 2016, 6 pages.
- Office Action for U.S. Appl. No. 14/511,093, dated May 20, 2016, 8 pages.
- Office Action for U.S. Pat. No. 6,216,185, dated Apr. 12, 2000, 9 pages.
- Office Action for U.S. Pat. No. 6,216,185, dated Aug. 25, 2000, 9 pages.
- Office Action for U.S. Pat. No. 6,345,330, dated Jun. 15, 2000, 7 pages.
- Office Action for U.S. Pat. No. 6,345,330, dated Mar. 23, 2001, 6 pages.
- Office Action for U.S. Appl. No. 10/963,825, dated Oct. 27, 2005, 25 pages.
- Office Action for U.S. Appl. No. 10/963,825, dated May 31, 2006, 29 pages.
- Office Action for U.S. Appl. No. 10/963,825, dated Oct. 20, 2006, 28 pages.
- Office Action for U.S. Appl. No. 10/963,825, dated May 14, 2009, 5 pages.
- Office Action for U.S. Appl. No. 10/963,825, dated Sep. 15, 2009, 14 pages.
- Office Action for Re. 41,294, dated Nov. 16, 2007, 10 pages.
- Office Action for Re. 41,294, dated Apr. 15, 2008, 10 pages.
- Office Action for Re. 41,294, dated Sep. 16, 2008, 11 pages.
- Office Action for Re. 41,076, dated Jul. 13, 2007, 38 pages.
- Office Action for Re. 41,076, dated Oct. 17, 2007, 55 pages.
- Office Action for Re. 41,076, dated Feb. 11, 2008, 62 pages.
- Office Action for Re. 41,076, dated Jun. 9, 2008, 25 pages.
- Office Action for Re. 41,076, dated Dec. 30, 2008, 8 pages.
- Office Action for U.S. Appl. No. 12/322,858, dated Mar. 4, 2010, 24 pages.
- Office Action for U.S. Appl. No. 12/322,858, dated Jun. 25, 2010, 22 pages.
- Office Action for U.S. Appl. No. 12/322,858, dated Feb. 3, 2011, 28 pages.
- Office Action for U.S. Appl. No. 12/577,074, dated Apr. 13, 2010, 7 pages.
- Office Action for U.S. Appl. No. 12/577,074, dated Nov. 10, 2010, 6 pages.
- Office Action for U.S. Appl. No. 12/577,074, dated May 6, 2011, 7 pages.
- Office Action for U.S. Appl. No. 09/312,199, dated Mar. 26, 2003, 5 pages.
- Office Action for Re. 41,092, dated Sep. 17, 2008, 8 pages.
- Office Action for U.S. Appl. No. 11/545,056, dated Mar. 12, 2010, 26 pages.
- Office Action for U.S. Appl. No. 12/561,138, dated Sep. 29, 2010, 4 pages.
- Office Action for U.S. Appl. No. 12/561,138, dated Mar. 17, 2011, 5 pages.
- Office Action for U.S. Appl. No. 13/294,108, dated Feb. 14, 2012, 5 pages.
- Office Action for U.S. Appl. No. 13/562,210, dated Nov. 19, 2012, 6 pages.
- Office Action for U.S. Appl. No. 13/562,210, dated Feb. 21, 2013, 4 pages.
- Office Action for U.S. Appl. No. 13/649,078, dated Feb. 12, 2013, 4 pages.
- Office Action for U.S. Appl. No. 13/899,484, dated Sep. 17, 2013, 5 pages.
- Office Action for U.S. Appl. No. 14/109,749, dated May 15, 2014, 6 pages.
- Office Action for U.S. Appl. No. 15/055,436, dated Jun. 3, 2016, 6 pages.
- Bogaerts, A., et al., “Application of the Scalable Coherent Interface to Data Acquisition at LHC: RD24 Status Report,” CERN-DRDC-94-23, CERN-RD-24-Status-Report-1994, 29 pages.
- P1394B (Gagabit 1394) Draft 1.33, Institute of Electrical and Electronics Engineers, Inc., Feb. 10, 1998, 4 pages.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft 0.02, Institute of Electrical and Electronics Engineers, Inc, pp. 1-56, Apr. 7, 1997.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft 0.03, Institute of Electrical and Electronics Engineers, Inc., pp. 1-54, Jun. 11, 1997.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft 0.04, Institute of Electrical and Electronics Engineers, Inc., Institute of Electrical and Electronics Engineers, Inc., pp. 1-68, Jul. 25, 1997.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft 0.05, Institute of Electrical and Electronics Engineers, Inc., pp. 1-82, Sep. 5, 1997.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft 0.06, Institute of Electrical and Electronics Engineers, Inc. pp. 1-104, Dec. 2, 1997.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft 0.07 Institute of Electrical and Electronics Engineers, Inc., pp. 1-86, Dec. 24, 1997.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft 0.71, Institute of Electrical and Electronics Engineers, Inc., pp. 1-120, Jan. 12, 1998.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft 0.08, Institute of Electrical and Electronics Engineers, Inc., pp. 1-131, Feb. 9, 1998.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft 0.09, Institute of Electrical and Electronics Engineers, Inc., pp. 1-146, Mar. 11, 1998.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft 0.10, Institute of Electrical and Electronics Engineers, Inc., pp. 1-148, Apr. 20, 1998.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft 0.011, Institute of Electrical and Electronics Engineers, Inc., pp. 1-174, Jul. 1, 1998.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft 0.012, Institute of Electrical and Electronics Engineers, Inc., pp. 1-205, Aug. 14, 1998.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft 0.013, Institute of Electrical and Electronics Engineers, Inc., pp. 1-204, Sep. 4, 1998.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft 0.14, Institute of Electrical and Electronics Engineers, Inc., pp. 1-208, Oct. 8, 1998.
- Horst, Robert W., “TNet: A Reliable System Area Network,” IEEE Micro 15(1): 37-45 (1995).
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft 0.15, Institute of Electrical and Electronics Engineers, Inc., pp. 1-228, Dec. 7, 1998.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft 016, Institute of Electrical and Electronics Engineers, Inc., pp. 1-200, Feb. 5, 1999.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft 0.17, Institute of Electrical and Electronics Engineers, Inc., pp. 1-238, Apr. 23, 1999.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft 0.6, Institute of Electrical and Electronics Engineers, Inc., pp. 1-250, Jun. 8, 1999.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft 0.7, Institute of Electrical and Electronics Engineers, Inc., pp. 1-282, Jul. 16, 1999.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft 0.75, Institute of Electrical and Electronics Engineers, Inc., pp. 1-288, Aug. 10, 1999.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft 0.80, Institute of Electrical and Electronics Engineers, Inc., pp. 1-300, Aug. 20, 1999.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft 0.85, Institute of Electrical and Electronics Engineers, Inc., pp. 1-385, Sep. 14, 1999.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft 0.87, Institute of Electrical and Electronics Engineers, Inc., pp. 1-346, Sep. 28, 1999.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft 0.90, Institute of Electrical and Electronics Engineers, Inc., pp. 1-356, Oct. 6, 1999.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft 0.91, Institute of Electrical and Electronics Engineers, Inc., pp. 1-374, Oct. 13, 1999.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft 0.91a, Institute of Electrical and Electronics Engineers, Inc., pp. 1-180, Oct. 27, 1999.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft 0.92, Institute of Electrical and Electronics Engineers, Inc., pp. 1-374, Nov. 10, 1999.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft 0.92, Institute of Electrical and Electronics Engineers, Inc., p. 306, Nov. 10, 1999.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft 1.00, Institute of Electrical and Electronics Engineers, Inc., pp. 1-362, Feb. 25, 2000.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft 1.07, Institute of Electrical and Electronics Engineers, Inc., pp. 1-398, Mar. 13, 2001.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft 1.11, Institute of Electrical and Electronics Engineers, Inc., pp. 1-386, Mar. 27, 2001.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft 1.3, Institute of Electrical and Electronics Engineers, Inc., pp. 1-398, Oct. 10, 2001.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft 1.3.1, Institute of Electrical and Electronics Engineers, Inc., pp. 1-398, Oct. 15, 2001.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft 1.3.3, Institute of Electrical and Electronics Engineers, Inc., pp. 1-408, Nov. 16, 2001.
- P1394b IEEE Draft Standard for a High Performance Serial Bus (Supplement) for P1394b, Draft 0.xx, Section 12, Institute of Electrical and Electronics Engineers, Inc., pp. 145-180, Oct. 1998.
- Dolphin Specification D308/D312, PCI-SCI Adapter Card, Confidential, pp. 1-18, Dec. 18, 1998.
- The Dolphin SCI Interconnect White Paper, pp. 1-16, Feb. 1996.
- Hagg and Lundqvist, Axe Hardware Evolution, Ericsson Review, No. 2, pp. 52-93 (1997).
- Nilsson, T., Toward Third-Generatio Wireless Communcation, Ericsson Review, No. 2, pp. 68-106 (1998).
- Ketris 9000 System Information, 4 pages, Aug. 1, 2000.
- Ketris Media Blade Hardware Manual, 17 pages (2000).
- Ketris Server Blade Hardware Manual, 60 pages (2000).
- Ketris Manager Software Manual, 28 pages (2000).
- Ketris Solution, 4 pages, Jun. 22, 2000.
- Ketris 9000 System Hardward Manual, 46 pages (2000).
- Huq, S., et al., “Overview of LVDS Technology,” National Semiconductor Application Note 971, Semiconductor Corporation, pp. 1-6, Jul. 1998.
- Kempainen, S., “BusLVDS Expands Applications for Low Voltage Differential Signaling (LVDS),” 2000 High-Performance System Design Conference, National Semiconductor, 14 pages.
- SN65LVDS95 LVDS Serdes Transmitter Information, pp. 1-13, Feb. 2000.
- “Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits,” Telecommunciations Industry Association (TIA/EIA-644-A), 35 pages, Aug. 11, 2004.
- LVDS Owner's Manual, 94 pages (2004).
- National Semiconductor LVDS Owner's Manual, 2nd Edition, pp. 1-99 (2000).
- Texas Instruments LVDS Design Notes, pp. 1-12, Sep. 2002.
- Chen, J., et al., NESA Technical White Paper, “Signal Integrity and Validation of National's Bus LVDS (BLVDS) Techology in Heavily Loaded Backplanes,” prepared for Interface Products Group, National Semiiconductor Corporation by North East Systems Associates, Inc., pp. 1-28, May 26, 1998.
- National Semiconductor LVDS Owner's Manual, 66 pages (1997).
- Gustavson and Li, “The Scalable Coherent Interface (SCI),” IEEE Communications Magazine, pp. 52-63 (1996).
- Saulsbury, A., et al., “Missing the Memory Wall: the Case for Processor/Memory Integration,” Sun Microsystems Computer Corporation, Swedish Institute of Computer Science, Association for Computing Machinery, 12 pages (1996).
- Bogaerts, A., et al., “Application of the Scalable Coherent Interface to Data Acquisition at LHC: RD24 Status Report,” CERN-LHCC LHCC 96-33, LCB Status-Report/RD24, Oct. 2, 1996, 29 pages.
- “ServerNet—A High Bandwith, Low Latency Cluster Interconnection White Paper,” prepared by Industry Standard Server Division, Compaq Computer Corporation, pp. 1-9, Sep. 1998.
- Horst, R., “ServerNet Deadlock Avoidance and Fractahedral Topologies,” Proc. International Parallel Processing Symposium, 7 pages, Apr. 1996.
- “Tandem's ServerNet: A scalable and Connected Vision for Breakthrough Applications,” Aberdeen Group, Inc., pp. 1-10, Jul. 1995.
- ServerNet Family of Products, Tandem Computers Incorporated, pp. 1-5 (1998).
- Compaq ProLiant Clusters for the SCO UnixWare 7 U/300 Quick Install Guide for the Compaq ProLiant DL380, 108 pages, Jan. 2001.
- White Paper, Compaq ServerNet II SAN Interconnect for Scalable Computing Clusters, pp. 19, Jun. 2000.
- Heirich, A., et al., “ServerNet-II: a Reliable Interconnect for Scalable High Performance Cluster Computing,” Compaq Computer Corporation, Tandem Division, pp. 2-25 Sep. 21, 1998.
- QuickSpecs, Compaq System Area Network ServerNetII PCI Adapter, 3 pages, Dec. 15, 2000.
- QuickSpecs, Compaq System Area Network ServerNetII Switch, 3 pages, Dec. 26, 2000.
- ServerNet Technology Product Description, ServerNet PCI Adapter Data Sheet, pp. 1-4, Feb. 1998.
- Horst and Garcia, ServerNet San I/O Architecture, Hot Interconnects V, pp. 1-8 1997.
- ServerNet Technology Product Description, ServerNet Swtich 1 Data Sheet, pp. 1-4, Feb. 1998.
- “Evaluating and Implementing Compaq Data Center Solutions for Microsoft Windows 2000 Datacenter Server,” prepared by OS Integration Engineering, Compaq Computer Corporation, pp. 1-28, Dec. 2000.
- QuickSpecs Compaq ProLiant 6400r Pentium III Xeon, pp. 1-35, Dec. 11, 2000.
- Yalamanchili and Duato (Eds.), “Parallel Computing Routing and Communication,” Second International Workshop, PCRCW'97, Atlanta, GA, 120-135 pages, Jun. 26-27, 1997.
- Siemens Hardware Product RM600E, Model E30, E70, 12 pages, 1998.
- RM600 E (Reliant UNIX) Operating Manual, Siemens AG, pp. 1-217 (1999).
- WhiteCross 9800 Disk Card Design Specification by John Phillips, pp. 1-44, May 26, 1998.
- WhiteCross WX-Des Technical Overview, pp. 1-211 (2000).
- WhiteCross WX-Des Technical Overview Revision 2.00, Apr. 21, 1999, pp. 1-222.
- WhiteCross Ethernet Switch Card Rev. 2.0 by M. Fasil Khan, pp. 1-32, Mar. 8, 2001.
- WhiteCross Processor Backplane Functional Requirement Specification Rev. 1.00 by Brendon Smith, pp. 1-11, Jul. 31, 1997.
- WhiteCross Processor Backplane Design Specification Rev. 1.00, pp. 1-16, Feb. 3, 1998, by Brendon Smith.
- WhiteCross Processor Backplane Layout Specification, Rev. 1.02 by Brendon Smith, pp. 1-7, Nov. 12, 1997.
- WhiteCross 9800 Processor Card Design Specification, Rev. 1.01, by John Phillips, pp. 1-42, Feb. 25, 1998.
- WhiteCross 9800 Disk Card Layout Specification, Rev 1.00 by John Phillips, pp. 1-22, Apr. 6, 1998.
- WhiteCross Disk Connector Card Functional Requirement Specification, Rev. 1.00 by Louse Feakes, pp. 1-4, Jan. 14, 1998.
- WhiteCross Disk Connector Card Layout Specification, Rev. 1.00 by Louse Feakes, pp. 1-6, Jan. 14, 1998.
- WhiteCross Data Exploration, Configuration and Maintenance Manual, 354 pages, (1999).
- WhiteCross Data Exploration, White Paper: R&D 99Q3-01, pp. 1-38, Sep. 3, 1999.
- WhiteCross Configuration & Maintenancce Manual, Version 5.2, pp. 1-289, Nov. 2002.
- WhiteCross Technical Overview WXDES 9800, Rev 2.00 by Mike Burrow, pp. 1-90, Mar. 2, 1999.
- WhiteCross WX-DES Hardware Maintenance, pp. 1-72 (2000).
Type: Grant
Filed: Nov 22, 2013
Date of Patent: Jul 10, 2018
Assignee: Acqis LLC (McKinney, TX)
Inventor: William W. Y. Chu (Los Altos, CA)
Primary Examiner: Colin Larose
Application Number: 14/087,640
International Classification: G06F 21/00 (20130101); G06F 21/71 (20130101);
