SRAM design to facilitate single fin cut in double sidewall image transfer process
A double sidewall image transfer process for forming FinFET structures having a fin pitch of less than 40 nm generates paired fins with a spacing determined by the width of a sidewall spacer that forms a second mandrel. Here, the fin pairs are created at two different spacings without requiring the minimum space for the standard sidewall structure. An enlarged space between paired fins is created by placing two first mandrel shapes close enough so as to overlap or merge two sidewall spacer shapes so as to form a wider second mandrel upon further processing. The fin pair created from the wider second mandrel is spaced at about 2 times the fin pair created from the narrower second mandrel. For some circuits, such as an SRAM bitcell, the wider second mandrel can be utilized to form an inactive fin not utilized in the circuit structure, which can be removed. In some embodiments, all dummy inactive fins are eliminated for a simpler process.
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This application The present disclosure is a Broadening Reissue of U.S. Pat. No. 10,096,521, issued Oct. 9, 2018, which is a Continuation of and claims priority to U.S. Non-Provisional application Ser. No. 14/971,212, entitled “SRAM DESIGN TO FACILITATE SINGLE FIN CUT IN DOUBLE SIDEWALL IMAGE TRANSFER PROCESS,” filed Dec. 16, 2015, which is are incorporated herein by reference in its entirety.
BACKGROUNDThe present invention relates to the manufacture of semiconductor devices with fins, and more particularly, to an SRAM design to facilitate single fin cut in a double sidewall image transfer process for the 10 nanometer (nm) technology nodes and beyond.
A fin-type field effect transistor (FinFET) is a type of transistor that has a fin, containing a channel region and source and drain regions. A double-gated FinFET is a FinFET with gate conductors on both sidewall of the fin. A triple-gated FinFET is a FinFET with gate conductors on both sidewall and the top wall of the fin. The gate conductors cover the channel region of the fin, whereas the source and drain regions of the fin extend beyond the coverage of the gate conductors. FinFETs are discussed at length in U.S. Pat. No. 6,413,802 to Hu et al. (hereinafter “Hu”), which is incorporated herein by reference in its entirety. FinFETs may comprise only front and/or back gate conductors. Front gate conductors are generally isolated from any conductive material in the substrate and contacts to front gate conductors are etched from above, Back gate conductors are generally electrically connected to a conductive material in the substrate and contacts to the back conductors are etched from below. In order to improve upon current technology, manufacturers are continuously striving to increase the density of devices on integrated circuits and to simultaneously decrease the cost of producing the integrated circuits without adversely affecting performance.
To scale fin pitch to less than or equal to 40 nm, a double sidewall image transfer (SIT2). To scale fin pitch to less than or equal to 40 nm, a double sidewall image transfer (SIT2) or a self-aligned quadruple patterning (SAQP) process can be utilized. This process generates paired fins with a spacing determined by the width of the sidewall spacer that forms a second mandrel. The spacing being the two paired fins is minimized as much as possible. For some circuits, such as an SRAM bitcell, one needs to remove one of the fins in the pair, i.e., a single fin cut, as they are not intended to be part of the final FinFET devices that are formed on the substrate. The single fin to be cut is referred to as a dummy or inactive fin (i.e., FINI) and the other fin is referred to as an active fin (i.e., FINA), wherein the fin pair collectively is at minimum spacing. That minimum spacing can oftentimes be too small as a function of scaling to allow the effective removal of the FINI without damaging or removing its neighboring FINA.
SUMMARYAccording to an embodiment of the present invention, a process for forming a fin structure having a fin pitch of less than 40 nanometers includes providing a multilayer structure overlaying a semiconductor substrate, wherein the multilayer structure comprises a planar cap layer, and alternating dielectric and hard mask layers stackedly arranged on the semiconductor substrate; lithographically patterning a photoresist disposed on the cap layer to form a first mandrel pattern consisting of first and second mandrel shapes; forming first sidewall spacers on the first mandrel pattern, wherein sidewall spacers between adjacent first and second mandrel shapes overlap or merge; removing the first mandrel pattern and etching the structure to form a second mandrel pattern consisting of a first mandrel shape and a second mandrel shape, wherein the second mandrel shape is at about two times a width of the first mandrel shape; forming second sidewall spacers on the second mandrel pattern; and etching the structure to form multiple fin pairs in the semiconductor substrate comprising fin pairs have a minimal spacing and fin pairs are about two times the minimal spacing.
In another embodiment, a process for forming a fin structure having a fin pitch of less than 40 nanometers includes providing a multilayer structure overlaying a semiconductor substrate, wherein the multilayer structure comprises a planar cap layer, and alternating dielectric and hard mask layers stackedly arranged on the semiconductor substrate; lithographically patterning a photoresist disposed on the cap layer to form a first mandrel pattern consisting of first and second mandrel shapes; forming first sidewall spacers on the first mandrel pattern, wherein sidewall spacers between adjacent first and second mandrel shapes define a small gap therebetween, wherein the small gap is a sub-threshold assist feature; removing the first mandrel pattern and etching the structure to form a second mandrel pattern consisting of a first mandrel shape and a second mandrel shape, wherein the second mandrel shape is at about two times a width of the first mandrel shape, and wherein the second mandrel shape is free of the sub-threshold assist feature; forming second sidewall spacers on the second mandrel pattern; and etching the structure to form multiple fin pairs in the semiconductor substrate comprising fin pairs have a minimal spacing and fin pairs are about two time the minimal spacing.
In yet another embodiment, a process or increasing active fin mask edge location tolerance associated with fabrication of an SRAM cell fin structure includes forming a fin structure comprising multiple fin pairs, wherein fins in the multiple fin pairs are either active or inactive for the SRAM cell fin structure, wherein the inactive fins are included in fin pairs that are about two times the spacing between other fin pairs, wherein the inactive fin are located between active regions of the SRAM cell fin structure; and removing at least one of the inactive fins from the fin structure.
Referring now to the figures wherein the like elements are numbered alike:
Figures ((FIG(S).”) 1A-1M schematically illustrate a process sequence for forming a FinFet structure in accordance with an embodiment;
The present invention is generally directed to SRAM design to facilitate single fin cut in a double sidewall image transfer process for forming fins on a substrate having a fin pitch less than 40 nm and/or having a variable pitch associated with the formation of devices such as SRAM bitcells. In the double sidewall image transfer process, a first spacer is deposited on sidewalls of a first mandrel, which are then used as a second mandrel to form a pair of fins. The spacing between two paired fins is minimized as much as possible so as to maximize fin density. In the present invention, the fin pairs are created at two different spacings without requiring the minimum space for the standard sidewall structure. An enlarged space between paired fins is created by placing two first mandrel shapes close enough so as to overlap or merge two sidewall spacer shapes defined so as to form a wider second mandrel upon further processing. The fin pair created from the wider second mandrel can be spaced to about 2 times the fin pair created from the narrower second mandrel. In some special cases, the dummy FINI can be simply be eliminated instead of being shifted away from the adjacent active FINA. As will be described in greater detail below, the resulting wider fin pair spacing allows for reduced tolerance requirements for FINI removal patterning edge placement. Alternatively, the present invention allows a second wider spacing for paired active FINAs. Advantageously, increased tolerance for the active fin mask edge location is provided.
Referring now to
It should be noted that the substrate 102 can be a bulk semiconductor substrate, a semiconductor-on-insulator substrate or the like. Further, the substrate 102 can be composed of silicon, silicon-germanium, germanium or any other suitable semiconductor materials in which fins for multi-gate devices can be formed. Furthermore, a portion of or the entire semiconductor substrate may be strained. A portion of or entire semiconductor substrate 102 may be amorphous, polycrystalline, or single-crystalline. In addition to the aforementioned types of semiconductor substrates, the semiconductor substrate 102 invention may also comprise a hybrid oriented (HOT) semiconductor substrate in which the HOT substrate has surface regions of different crystallographic orientation. The semiconductor substrate 100 may be doped, undoped or contain doped regions and undoped regions therein. The semiconductor substrate 102 may be strained, untrained, contain regions of strain and no strain therein, or contain regions of tensile strain and compressive strain.
The stack of layers formed on substrate 102 may include, for example and starting from substrate 102, a first dielectric layer 104; a first hard mask layer 106; a second dielectric layer 108; a second hard mask layer 110; and an organic planarization layer (OPL) or anti-reflective coating (ARC) cap layer 112 (e.g., bottom anti-reflective coating), all of which may be formed on top of one another and in sequence. The dielectric layers are not intended to be limited and may be the same or different. By way of example, the dielectric layers 104, 108 may include silicon nitride, for example. Likewise, the hard mask layers 106, 110 are not intended to be limited and may be the same or different. By way of example, the hard mask layers include amorphous silicon, for example, from which the respective mandrels are formed.
As shown in
The photolithography process may comprise, for example, introducing electromagnetic radiation such as ultraviolet light through an overlay mask to cure a photoresist material (not shown). Depending upon whether the resist is positive or negative, uncured portions of the resist are removed to form the first resist pattern 114 including openings to expose portions of the cap layer 112 and sacrificial first mandrel layer 110.
The material defining photo-resist layer may be any appropriate type of photo-resist materials, which may partly depend upon the device patterns to be formed and the exposure method used. For example, material of photo-resist layer 114 may include a single exposure resist suitable for, for example, argon fluoride (ArF); a double exposure resist suitable for, for example, thermal cure system; and/or an extreme ultraviolet (EUV) resist suitable for, for example, an optical process. Photo-resist layer may be formed to have a thickness ranging from about 30 nm to about 150 nm in various embodiments. First resist pattern 114 may be formed by applying any appropriate photo-exposure method in consideration of the type of photo-resist material being used.
As noted above, the first resist pattern 114 is anisotropically etched to remove the first resist pattern 114, the exposed portions of the OPL/ARC layer 112 and hardmask layer 110 such as by reactive ion etching (RIE) to define the first mandrel shapes. The first resist pattern 114 is configured to provide two first mandrel shapes 116 and 117, wherein the first mandrel shapes 116 and 117 are close enough such that subsequent deposition of a spacer layer 118 (see
The first mandrel 116 and 117 may be formed of amorphous silicon and have different widths. However, it should be noted that other materials (e.g., germanium, silicon germanium) may also be used for the mandrels so long as there is an etch selectivity with respect to subsequently formed sidewall spacers thereon. The first mandrel shapes 116a and 116b have nearly vertical etch slopes or nearly vertical contact angles. By use of the terms “nearly vertical etch slope” or “nearly vertical contact angle” is meant an angle defined by the sidewall of the opening being formed of at least 80°, preferably about 90°, with the plane of the layer 110 being etched.
The etching apparatus used in carrying out the anisotropic etch may comprise any commercially available reactive ion etching (RIE) apparatus, or magnetically enhanced reactive ion etching (MERIE) apparatus, capable of supporting a wafer of the size desired to be etched in which gases of the type used herein may be introduced at the flow rates to he discussed and a plasma maintained at the power levels required for the process. Such apparatus will be generally referred to herein as RIE apparatus, whether magnetically enhanced or not. Examples of such commercially available apparatus include the Precision 5000 magnetically enhanced reactive ion etcher available from Applied Materials, Inc.; the Rainbow reactive ion etcher by Lain; the reactive ion apparatus by legal Company; and the Quad reactive ion etcher by Drytek.
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An anisotropic etch is performed to remove portions of the spacer layer 132 as so to as form the sidewall spacers 134 as shown in
Referring now to
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The patterned dielectric layer 104 is then transferred into the substrate 102 to form pairs of fins 150, 152 via an anisotropic etching process, e.g., a RIE process as shown in
Referring now to
In other embodiments shown in
Referring to
In some cases, with very tight fin pitches, the lithography and etching processes that are performed to remove the dummy fins can result in undesirable damage to the device fins, the fins that are intended for final use in the device 10. The present invention advantageously increases the tolerances associated with the masked silicon etching step, thereby increasing. Oftentimes, misalignment can occur for a variety of reasons, e.g., variations on photolithography tools, materials and techniques, overlay errors, etc.
Advantageously, the present invention allows the creation of FIN pairs at two spacings without requiring the minimum space for the standard sidewall structure, an enlarged space between paired FINs created by placing two mandrel (1) shapes close enough to overlap two sidewall shapes to form a wider mandrel (2). The FIN pair created from the wider mandrel (2) is spaced at about 2 times the narrow mandrel (2). The resulting wider FIN pair spacing allows reduced tolerance requirements for FINI removal patterning edge placement. Alternatively, the invention allows a second wider spacing for pair active FINAs. In one aspect, all dummy FINIs are simply eliminated and the step of FINA preserve can be skipped in the process.
In contrast, the masked silicon etching step tolerances to form the single SRAM 6T bitcell in accordance with the present invention is markedly increased. As shown in
Still other aspects, features, and technical effects will be readily apparent to those skilled in this art from the following detailed description, wherein preferred embodiments are shown and described, simply by way of illustration of the best mode contemplated. The disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one more other features, integers, steps, operations, element components, and/or groups thereof.
The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated
The diagrams depicted herein are just one example. There may be many variations to this diagram or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention.
While the preferred embodiment to the invention had been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.
Claims
1. A process for increasing active fin mask edge location tolerance associated with fabrication of an for forming an SRAM cell fin structure, the process comprising:
- forming a fin structure comprising plurality of fin pairs, wherein: multiple fin pairs at of the plurality of fin pairs have a pitch of less than 40 nm,; wherein individual fins in the multiple plurality of fin pairs are either active fins or inactive for the SRAM cell fin structure, fins; wherein the inactive fins are included in fin pairs that are about two times the have a fin spacing between other that is about two times the fin spacing of fin pairs including that include only active fins,; and wherein the inactive fins are located between active regions of the SRAM cell fin structure; fins; and
- removing the inactive fins from cutting one or more of the inactive fins to form the SRAM cell fin structure.
2. The process of claim 1, wherein removing the at least one inactive fin from the fin structure comprises patterning a photoresist layer to form openings exposing the at least one inactive fin within the fin pair having about two times the spacing relative to other fin pairs; and etching to remove the at least one inactive fin from the fin structure.
3. The process of claim 1, wherein etching to remove the at least one inactive fin comprises a timed etching process.
4. The process of claim 3, wherein the inactive fin in the fin pair having about two times the spacing relative to other fin pairs is proximally located to the other fin pairs with the minimal spacing.
5. The process of claim 3, wherein the inactive fin in the fin pair having about two times the spacing relative to other fin pairs is distally located to the other fin pairs with the minimal spacing.
6. The process of claim 3, wherein etching removes all of the inactive fins included in the fin pairs that are about two times the spacing between other fin pairs.
7. The process of claim 1, wherein cutting one or more of the inactive fins comprises exposing the one or more of the inactive fins to an etchant through openings in a mask.
8. The process of claim 1, further comprising forming an isolation region in the location where the one or more of the inactive fins were cut.
9. The process of claim 1, wherein forming the plurality of fin pairs comprises forming sidewall spacers on a plurality of mandrels, each of the fins of the plurality of fin pairs corresponding to a sidewall spacer.
10. A fin cut process for forming an SRAM cell fin structure, the fin cut process comprising:
- forming a plurality of fin pairs, the plurality comprising multiple fin pairs having a fin pitch of less than 40 nm, a first fin pair of the plurality of fin pairs having a fin spacing that is about half the fin spacing of a second fin pair of the plurality of fin pairs; and
- cutting a first fin of the second fin pair through an opening in a mask, wherein an edge of the mask opening extends parallel to and between the first fin and a second fin of the second fin pair, and cutting the first fin comprises etching the first fin through the opening.
11. The process of claim 10, wherein the fin pitch of the first fin pair is less than about 27 nm.
12. The process of claim 10, wherein the fin pitch of the first fin pair is about 24 nm.
13. The process of claim 10, wherein the fin spacing of the first fin pair is less than about 21 nm.
14. The process of claim 10, wherein the fin spacing of the first fin pair is about 18 nm.
15. The process of claim 10, wherein forming the plurality of fin pairs comprises:
- forming first sidewall spacers, wherein the forming causes the first sidewall spacers to merge in a region between at least two adjacent first mandrels; and
- using the first sidewall spacers to form second mandrels, at least one of the second mandrels having a width corresponding to the width of the region between the at least two adjacent first mandrels; and
- forming second sidewall spacers on the second mandrels.
16. The process of claim 10, wherein forming the plurality of fin pairs comprises forming sidewall spacers on a plurality of mandrels, each of the fins of the plurality of fin pairs corresponding to a sidewall spacer.
17. The process of claim 10, wherein the fin structure is formed using a self-aligned quadruple patterning (SAQP) process.
18. A process for forming an SRAM cell fin structure, the process comprising:
- forming a plurality of fin pairs, the plurality of fin pairs comprising: multiple fin pairs having a fin pitch of less than 40 nm; a first fin pair having a first fin spacing less than about 21 nm; and a second fin pair having a second fin spacing about twice the first fin spacing; and
- cutting a fin of the second fin pair by exposing the fin to an etchant through an opening in a mask, wherein the mask is patterned to divide the second fin pair.
19. The process of claim 18, wherein the first fin spacing is about 18 nm.
20. The process of claim 18, wherein forming the plurality of fin pairs comprises:
- forming first sidewall spacers on at least two adjacent first mandrels, wherein the forming causes the sidewall spacers to merge in a region between the at least two adjacent first mandrels; and
- using the first sidewall spacers to form second mandrels, at least one of the second mandrels having a width corresponding to the width of the region between the at least two adjacent first mandrels; and
- forming second sidewall spacers on the second mandrels.
21. The process of claim 18, wherein forming the plurality of fin pairs comprises forming sidewall spacers on a plurality of mandrels, each of the fins of the plurality of fin pairs corresponding to a sidewall spacer.
22. The process of claim 18, wherein forming the fin structure comprises using a self-aligned quadruple patterning (SAQP) process.
23. A process for forming an SRAM cell fin structure comprising:
- forming first sidewall spacers on at least two adjacent first mandrels, wherein the forming causes the first sidewall spacers to merge in a region between the at least two adjacent first mandrels; and
- using the first sidewall spacers to form second mandrels, at least one of the second mandrels having a first width and at least one of the second mandrels having a second width, the first width corresponding to a thickness of the first sidewall spacers, and the second width corresponding to the width of the region between the at least two adjacent first mandrels; and
- forming second sidewall spacers on the second mandrels; and
- using the second sidewall spacers to form a plurality of fin pairs, the plurality of fin pairs comprising at least two first fin pairs and a second fin pair, the at least two first fin pairs having a fin pitch of less than 40 nm and a first spacing corresponding to the first width, the second fin pair has a second spacing corresponding to the second width, and the second spacing is about two times the first spacing.
24. The process of claim 23, further comprising cutting one of the fins of the second fin pair to form the SRAM cell fin structure.
25. The process of claim 24, wherein the cutting comprises exposing the fin of the second fin pair to an etchant through an opening in a mask, wherein the mask is patterned to divide the second fin pair.
26. The process of claim 23, wherein the first spacing is less than or equal to 21 nm.
27. The process of claim 23, wherein the first spacing is about 18 nm.
28. A process for increasing active fin mask edge location tolerance associated with fabrication of an SRAM cell fin structure, the process comprising:
- forming a plurality of fin pairs using a self-aligned quadruple patterning (SAQP) process, the plurality comprising at least two first fin pairs and a second fin pair disposed between the two first fin pairs, wherein: the at least two first fin pairs comprise only active fins; the second fin pair comprises an inactive fin; the at least two first fin pairs have a pitch of less than 40 nm; and a spacing between the fins of the second fin pair is about two times a spacing between fins of the first fin pair; and
- cutting the inactive fin of the second fin pair.
29. The process of claim 28, wherein cutting the inactive fin comprises exposing the inactive fin to an etchant through an opening in a mask patterned to divide the second fin pair.
30. The process of claim 29, wherein cutting the inactive fin comprises a timed etch process.
31. The process of claim 30, wherein the inactive fin of the second fin pair is proximally located with respect to one of the first fin pairs.
32. The process of claim 30, wherein the inactive fin of the second fin pair is distally located with respect to one of the first fin pairs.
33. A process for forming an SRAM fin structure, the process comprising:
- forming first sidewall spacers on at least two first mandrels, wherein the first sidewall spacers merge in a region between the at least two first mandrels;
- transferring a pattern defined by the first sidewall spacers to form a plurality of second mandrels;
- forming second sidewall spacers on the plurality of second mandrels; and
- transferring a pattern defined by the second sidewall spacers to form a plurality of fin pairs, the plurality of fin pairs comprising at least two first fin pairs having a pitch of less than 40 nanometers and a second fin pair disposed between the at least two first fin pairs, wherein a spacing between fins of the second fin pair is about two times a spacing between fins of first fin pairs.
34. The process of claim 33, wherein one of the fins in the second fin pair is an inactive fin, and the process further comprises cutting the inactive fin by exposing the inactive fin to an etchant through an opening in a fin cut mask.
35. The process of claim 1, wherein the fin structure is formed using a self-aligned quadruple patterning (SAQP) process.
36. The process of claim 1, wherein forming the plurality of fin pairs comprises:
- forming first sidewall spacers on at least two adjacent first mandrels, wherein the forming causes the first sidewall spacers to merge in a region between the at least two adjacent first mandrels;
- using the first sidewall spacers to form second mandrels, at least one of the second mandrels having a width corresponding to the width of the region between the at least two adjacent first mandrels; and
- forming second sidewall spacers on the second mandrels.
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Type: Grant
Filed: Oct 8, 2020
Date of Patent: Jan 9, 2024
Assignee: Adeia Semiconductor Solutions LLC (San Jose, CA)
Inventors: Mary E. Weybright (Pleasant Valley, NY), Robert C. Wong (Poughkeepsie, NY)
Primary Examiner: Minh Nguyen
Application Number: 17/066,281
International Classification: H01L 29/66 (20060101); H01L 21/8234 (20060101); H01L 21/308 (20060101); H10B 10/00 (20230101); H01L 21/3065 (20060101); H01L 21/84 (20060101); H01L 21/027 (20060101);