Abstract: It is an object of the present invention to identify a glypican-3-derived peptide which can bind to HLA-A2 and activate human killer T cells, so as to provide a means for carrying out an immunotherapy which is able to target approximately 40% of Japanese patients suffering from several types of cancers, which express GPC3 at a high level. The present invention provides a peptide of any of the following (A) or (B): (A) a peptide, which has the amino acid sequence as shown in any one of SEQ ID NOS: 1 to 3; or (B) a peptide, which has an amino acid sequence comprising a substitution or addition of one or two amino acids with respect to the amino acid sequence as shown in any one of SEQ ID NOS: 1 to 3, and which has ability to induce killer T cells.

Abstract: A novel induction method that effectively produces platelets from platelet precursor cells (e.g., hemopoietic stem/precursor cells) is disclosed. The method includes culturing platelet precursor cells in a culture solution in which a composite membrane is immersed so that the platelet precursor cells differentiate into platelets, the composite membrane including a porous support membrane and a porous thin membrane, the porous thin membrane being stacked on at least one side of the porous support membrane.

Abstract: The present application describes a method of culturing, expanding or growing stem or stem-like cells or induced pluripotent stem cells on a surface, including attaching the cells to the surface through a ligand that binds to the surface and the cells.

Abstract: A system and method for concentrating samples. The system can include a first container adapted to contain a sample. The first container can include a first portion and a second portion adapted to be removably coupled to the first portion. The system can further include a second container comprising the second portion and a third portion adapted to be removably coupled to the second portion. The method can include centrifuging the first container in a first orientation toward the second portion of the first container; retaining a concentrate of the sample in the second portion of the first container; and centrifuging the second container in a second orientation toward the third portion of the second container, such that the concentrate retained in the second portion is moved into the third portion of the second container, the second orientation being different from the first orientation.

Abstract: The response of a patient with an enteropathic disease to therapy, particularly a candidate therapy in a clinical trial setting, is assessed by detecting the ability of the patient to metabolize an orally administered CYP3A substrate. The CYP3A metabolism may be monitored in a variety of ways. Conveniently, the appearance of a metabolite of the CYP3A substrate is detected in a patient sample over a period of time following oral administration, e.g. in urine, plasma, breath, saliva, etc. The CYP3A substrate is optionally labeled, e.g. with an isotopic, fluorescent, etc. label.

Abstract: A method for on-line monitoring of deprotection reaction in a peptide automated synthesizer comprising UV detector is disclosed. A UV source, detector, electronics, and housing are integrated with a line or tube through which liquid reactants flow for periodic measurements in the peptide synthesizer. The method includes determining the progression of the reaction, completion point of the reaction, and the modification of the reaction times and repetitions in real time.

Abstract: The invention provides improved crosslinkers which permit more efficient determination of protein interactions in biological samples.

Abstract: This invention relates to magnetic resonance-based sensors and related methods.

Abstract: Use of a latex of perfluorinated polymers having particles with an average diameter between 5 and 200 nm for determining the binding constant of two interacting molecular species by Laser Light Scattering (LLS), said polymeric particles comprising on the surface an amphiphilic non ionic surfactant, the same or a different surfactant ended with a receptor and a ligand interacting with the receptor.

Abstract: The present disclosure provides a reagent for detection of analyte in a sample and process of preparation of the reagent. The reagent comprises heparin and substrate coated with the analyte-counterpart. The analyte-counterpart of the reagent is capable of binding to said analyte. The present disclosure further provides a process for detection of an analyte in a sample by contacting said sample with said reagent and detecting formation of analyte-analyte counterpart complex. The present disclosure provides a kit for detection of an analyte in a sample.

Abstract: In accordance with a method of the present invention, a method of manufacturing a magnetic random access memory (MRAM) cell and a corresponding structure thereof are disclosed to include a multi-stage manufacturing process. The multi-stage manufacturing process includes performing a front end on-line (FEOL) stage to manufacture logic and non-magnetic portions of the memory cell by forming an intermediate interlayer dielectric (ILD) layer, forming intermediate metal pillars embedded in the intermediate ILD layer, depositing a conductive metal cap on top of the intermediate ILD layer and the metal pillars, performing magnetic fabrication stage to make a magnetic material portion of the memory cell being manufactured, and performing back end on-line (BEOL) stage to make metal and contacts of the memory cell being manufactured.

Abstract: Processes for selectively patterning a magnetic film structure generally include selectively etching an exposed portion of a freelayer disposed on a tunnel barrier layer by a wet process, which includes exposing the freelayer to an etchant solution comprising at least one acid and an organophosphorus acid inhibitor or salt thereof, stopping on the tunnel barrier layer.

Abstract: A magnetoresistive random access memory (MRAM) element includes a bottom electrode embedded in a first insulating layer; an annular reference layer in a first via hole of a second insulating layer on the first insulating layer, the annular reference layer being situated above the bottom electrode; a first gap fill material layer filling the first via hole; a barrier layer covering the annular reference layer, the second insulating layer and the first gap fill material layer; an annular free layer in a second via hole of a third insulating layer on the second insulating layer, the annular free layer being situated above the annular reference layer; and a top electrode stacked on the annular free layer.

Abstract: The present invention relates generally to assembly techniques. According to the present invention, the alignment and probing techniques to improve the accuracy of component placement in assembly are described. More particularly, the invention includes methods and structures to detect and improve the component placement accuracy on a target platform by incorporating alignment marks on component and reference marks on target platform under various probing techniques. A set of sensors grouped in any array to form a multiple-sensor probe can detect the deviation of displaced components in assembly.

Abstract: A chip attach frame is used to align pins of an integrated circuit chip with pads on a chip carrier. A frame block has a socket defining two alignment edges that form a reference corner. The chip is lowered into the socket, and the chip carrier is inclined while it supports the frame block and chip until the chip moves under force of gravity to the reference corner. Once located at the reference corner, the chip position is carefully adjusted by moving the frame block in the x- and y-directions until the pins are aligned with the pads. The frame block is spring biased against movement in the x- and y-directions, and the position of the frame block is adjusted using thumbscrews. A plunger mechanism can be used to secure the integrated circuit chip in forcible engagement with the chip carrier once the pins are aligned with the pads.

Abstract: The present invention may include a first dopant metrology system configured to measure a first plurality of values of at least one parameter of a wafer, an ion implanter configured to implant a plurality of ions into the wafer, a second dopant metrology system configured to measure a second plurality of values of at least one parameter of the wafer following ion implantation of the wafer by the implanter, wherein the first dopant metrology system and the second dopant metrology system are communicatively coupled, an annealer configured to anneal the wafer following ion implantation, and a third dopant metrology system configured to measure a third plurality of values of at least one parameter of the wafer following annealing of the wafer by the annealer, wherein the second dopant metrology system and the third dopant metrology system are communicatively coupled.

Abstract: A method for fabricating a light emitting diode includes steps of: forming a light emitting structure of the light emitting diode on a substrate; arranging a photoresist layer on a first semiconductor layer of the light emitting structure; depositing a plurality of dielectric material structures on the first semiconductor layer through a plurality of voids of the photoresist layer; removing the photoresist layer to form a plurality of voids between the plurality of dielectric material structures; forming a plurality of metal material structures in the plurality of voids; and forming a reflective layer on the plurality of dielectric material structures and the plurality of metal material structures.

Abstract: The present invention relates to a method for manufacturing large lighting which uses a power LED, such as for large LED lighting for street lamps, which incorporates a heat dissipation device that has the ability to dissipate heat with natural convection to maintain ambient temperature. The disclosed method is novel applied technology for producing a large LED lighting, such as for street lamps, which has a power LED device with a unique, rear heat dissipation capability. In addition to maximum thermal efficiency by heat dissipation, the present LED lighting system also increases luminous efficiency by providing high light emission with only a small quantity of LED power.

Abstract: A method for packaging an LED, includes steps: providing a substrate; arranging an LED die on the substrate; forming a photoresist layer on the substrate to cover the LED die; arranging a mask directly on the photoresist layer; exposing the photoresist layer with the mask to a radiation source; removing the mask and the unexposed portion of the photoresist layer formerly sheltered by the mask, thereby leaving the exposed portion of the photoresist layer formerly unsheltered by the mask on the substrate, wherein the remained exposed portion of the photoresist layer surrounds the LED die; spraying fluorescent material toward the LED die surrounded by the remained exposed portion of the photoresist layer; removing the remained exposed portion of the photoresist layer; and finally encapsulating the LED die covered by the fluorescent material.

Abstract: A method of forming a light emitting diode (LED) package includes mounting a LED structure to a carrier, overmolding the LED structure in a package body, backgrinding the package body to expose the LED structure, removing the carrier, and forming a redistribution layer (RDL) buildup structure comprising a RDL circuit pattern coupled to a LED of the LED structure. The LED package is formed without a substrate in one embodiment. By forming the LED package without a substrate, the thickness of the LED package is minimized. Further, by forming the LED package without a substrate, heat removal from the LED is maximized as is electrical performance. Further still, by forming the LED package without a substrate, the fabrication cost of the LED package is minimized.

Abstract: A process of making a microelectronic light-emitting device, including: a) growth on a metallic support of multiple wires based on one or more semi-conducting materials designed to emit radiant light, and b) formation of at least one electrical conducting zone of contact on at least one of the wires.

Abstract: A method for manufacturing an electronic device comprises a step for forming a coating film (100) on a surface of a conductor portion-containing body (500), a step for forming a photosensitive film (110) on the conductor (500) on which the coating film (100) has been formed, a step for exposing the photosensitive film (110) to a pattern corresponding to a patterned recessed or protruded portion, a step for developing the exposed photosensitive film (110), and a step for baking the developed photosensitive film (110). With this method, an excessive removal of a metal film can be prevented or suppressed.

Abstract: A frame assembly to stretch a donor film used in laser induced thermal imaging (LITI), a method of manufacturing the donor film, and a method of manufacturing an organic light emitting device. The frame assembly to stretch a donor film includes: a main body including a center opening; a first support portion including a film mounting guide portion on which the donor film is mounted; a second support portion that including a film pressing portion that presses a donor film in a direction perpendicular to a coupling direction of the frame main body and the first support portion; and an elastic member disposed between the first support portion and the main body, wherein the first support portion is coupled to an inner portion of the main body by a first coupling member, and wherein the second support portion is coupled to an inner portion of the first support portion in a direction perpendicular to the coupling direction of the main body and the first support portion by a second coupling member.

Abstract: The present invention provides a method for forming by plasma CVD a silicon nitride film that can be formed over heat-sensitive elements as well as an electroluminescent element and that has favorable barrier characteristics. Further, the present invention also provides a semiconductor device, a display device and a light-emitting display device formed by using the silicon nitride film. In the method for forming a silicon nitride film by plasma CVD, silane (SiH4), nitrogen (N2) and a rare gas are introduced into a deposition chamber in depositing, and the reaction pressure is within the range from 0.01 Torr to 0.1 Torr.

Abstract: A MEMS structure and methods of manufacture. The method includes forming a sacrificial metal layer at a same level as a wiring layer, in a first dielectric material. The method further includes forming a metal switch at a same level as another wiring layer, in a second dielectric material. The method further includes providing at least one vent to expose the sacrificial metal layer. The method further includes removing the sacrificial metal layer to form a planar cavity, suspending the metal switch. The method further includes capping the at least one vent to hermetically seal the planar cavity.

Abstract: A method for etching a diaphragm pressure sensor based on a hybrid anisotropic etching process. A substrate with an epitaxial etch stop layer can be etched utilizing an etching process in order to form a diaphragm at a selective portion of the substrate. The diaphragm can be oriented at an angle (e.g., 45 degree) with respect to the substrate in order to avoid an uncertain beveled portion in a stress/strain field of the diaphragm. The diaphragm can be further etched utilizing an etch finishing process to create an anisotropic edge portion on the major areas of the diaphragm and optimize the thickness and size of the diaphragm. Such an approach provides an enhanced diaphragm structure with respect to a wide range of pressure sensor applications.

Abstract: Provided are novel photovoltaic cell alignment apparatuses and methods for fabricating photovoltaic module sub-assemblies that include multiple aligned photovoltaic cells. The apparatuses and methods provide high-speed precise alignment of the cells with respect to each other and other components of a photovoltaic module. In certain embodiments, a set of photovoltaic cells is first aligned on an alignment plate of an alignment apparatus and then transferred to a sealing sheet of the module such that the respective alignments of the cells are maintained during transfer. The alignment plate may include multiple cell receiving areas that have corresponding alignment edges. Aligning photovoltaic cells on this plate may involve forcing the cells against the alignment edges and/or moving the cells in the receiving areas in a direction parallel to the alignment edges.

Abstract: A method for manufacturing a solar cell including a photovoltaic layer, a first electrode layer, a second electrode layer, an insulating layer and a light-transparent conductive layer is provided. The photovoltaic layer has a first surface and a second surface. The first electrode layer having at least one gap is disposed on the first surface, wherein the at least one gap exposes a portion of the photovoltaic layer. The second electrode layer is disposed on the second surface. The insulating layer having a plurality of pores is located on the photovoltaic layer exposed by the at least one gap, wherein the holes expose a portion of the photovoltaic layer. The light-transparent conductive layer covers the insulating layer and is connected with the first electrode layer. The transparent electrode is connected with the photovoltaic layer through at least a part of the pores.

Abstract: The invention relates to a manufacturing process of a photovoltaic solar cell (100) comprising: providing high doped areas (20) on the rear side (18) of the photovoltaic solar cell (100), providing localized metal contacts (30) localized on said high doped areas (20), providing a passivation layer (50) covering a surface (52) between said contacts (30), wherein the contacts (30) remain substantially free of the passivation layer (50), and depositing a metal layer (32) for a back surface field.

Abstract: A method is provided for applying back contact silver busbars to an aluminum back surface field (BSF) of a solar cell.

Abstract: Methods of modifying a patterned semiconductor substrate are presented including: providing a patterned semiconductor substrate surface including a dielectric region and a conductive region; and applying an amphiphilic surface modifier to the dielectric region to modify the dielectric region. In some embodiments, modifying the dielectric region includes modifying a wetting angle of the dielectric region. In some embodiments, modifying the wetting angle includes making a surface of the dielectric region hydrophilic. In some embodiments, methods further include applying an aqueous solution to the patterned semiconductor substrate surface. In some embodiments, the conductive region is selectively enhanced by the aqueous solution. In some embodiments, methods further include providing the dielectric region formed of a low-k dielectric material. In some embodiments, applying the amphiphilic surface modifier modifies an interaction of the low-k dielectric region with a subsequent process.

Abstract: A method for producing nanoparticle/block copolymer composites is provided. The method includes mixing nanoparticles having an organic ligand L and a block copolymer A-b-B having block repeating units A and B with different solubility parameters in a solvent S to form micelles by self-assembly. The solubility parameters of the organic ligand L, the block repeating units A and B of the block copolymer A-b-B and the solvent S satisfy the following inequalities: 29??S??A??(1) ?S??B?29??(2) |?L??A|?5 or |?L??B|?5??(3) in which ?S, ?A, ?B and ?L represent the solubility parameters of the solvent S, the block repeating unit A, the block repeating unit B and the ligand L, respectively. According to the method, the inherent electrical, magnetic, optical, chemical and mechanical properties of the nanoparticles can be maintained or improved without the need to modify the surface of the nanoparticles.

Abstract: A composition comprising: at least one compound comprising a hole transporting core, wherein the core is covalently bonded to a first arylamine group and also covalently bonded to a second arylamine group different from the first, and wherein the compound is covalently bonded to at least one intractability group, wherein the intractability group is covalently bonded to the hole transporting core, the first arylamine group, the second arylamine group, or a combination thereof, and wherein the compound has a molecular weight of about 5,000 g/mole or less. Blended mixtures of arylamine compounds, including fluorene core compounds, can provide good film formation and stability when coated onto hole injection layers. Solution processing of OLEDs is a particularly important application.

Abstract: An organic light emitting diode (OLED) display and a method for manufacturing the same are provided. The OLED display includes a substrate, an active layer and a capacitor lower electrode positioned on the substrate, a gate insulating layer positioned on the active layer and the capacitor lower electrode, a gate electrode positioned on the gate insulating layer at a location corresponding to the active layer, a capacitor upper electrode positioned on the gate insulating layer at a location corresponding to the capacitor lower electrode, a first electrode positioned to be separated from the gate electrode and the capacitor upper electrode, an interlayer insulating layer positioned on the gate electrode, the capacitor upper electrode, and the first electrode, a source electrode and a drain electrode positioned on the interlayer insulating layer, and a bank layer positioned on the source and drain electrodes.

Abstract: An integrated chip package structure and method of manufacturing the same is by adhering dies on a ceramic substrate and forming a thin-film circuit layer on top of the dies and the ceramic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.

Abstract: According to one embodiment, a semiconductor device manufacturing method includes producing a first substrate with an electrode, producing a second substrate with a through hole, stacking the second substrate on the first substrate, with an insulating layer intervening between the first substrate and the second substrate, making a hole reaching the electrode in the insulating layer under the through hole by etching the insulating layer with the second substrate as a mask, and filling the through hole and the hole with conductive substance.

Abstract: A method of manufacturing a semiconductor chip comprising placing a plurality of die units each having an active front surface and a back surface facing front surface up on an encapsulant layer, encapsulating the plurality of die units on the active surface of the encapsulant layer with an encapsulant covering a front surface and four side surfaces of each of the plurality of die units, and exposing, through the encapsulation on the front surface, conductive interconnects electrically connecting a die bond pad to a redistribution layer.

Abstract: A manufacturing method of a semiconductor element substrate including: forming a first photoresist pattern on a first surface of a metallic plate, to form a semiconductor element mounting part, a semiconductor element electrode connection terminal, a wiring, an outer frame part, and a slit; forming a second photoresist pattern on the second surface of the metallic plate; forming the slit by half etching to connect the metallic chip with a four corners of the outer frame part; forming a plurality of concaved parts on the second surface of the metallic plate; forming a resin layer by injecting a resin to the plurality of concaved parts; and etching the first surface of the metallic plate and forming the semiconductor element electrode connection terminal and the outer frame.

Abstract: A process for manufacturing semiconductor packages is provided, that includes drilling blind apertures in a reconstituted wafer, adhering a dry film resist on the wafer over the apertures, and patterning the film to expose a space around each of the apertures. The apertures and spaces are then filled with conductive paste by wiping a quantity of the paste across a surface of the film so that paste is forced into the spaces and apertures. The spaces around the apertures define contact pads whose thickness is constrained by the thickness of the film, preferably to about 10 ?m or less. To prevent paste from trapping air pockets in the apertures, the wiping process can be performed in a chamber from which much or all of the air has been evacuated. After curing the paste, the wafer is thinned from the back to expose the cured paste in the apertures.

Abstract: A method of manufacturing of an integrated circuit packaging system includes: providing a bottom package in a cavity in a central region of the bottom package having inter-package interconnects in the cavity; forming a vent on an inter-package connection side of the bottom package from an exterior of the bottom package to the cavity; mounting a top package on the inter-package interconnects; and applying an underfill through the vent and into the cavity.

Abstract: A mechanism is provided by which optically-inspectable features formed during surface mount bonding of no-leads packages are enhanced. Embodiments of the present invention use a lead frame having features that will lie upon the edges of the finished semiconductor device package, where molding material is prevented from lying in those features through the use of a preplaced film on the lead frame or film-assisted molding in conjunction with a mold chase that conforms to the features provided on the lead frame. Embodiments use a lead frame that has a pre-plated solderable surface, such that the exposed features enhance formation of the optically-inspectable features during solder reflow operations of PCB mounting.

Abstract: In one embodiment a method for manufacturing a semiconductor device comprises arranging a wafer on a carrier, the wafer comprising singulated chips; bonding the singulated chips to a support wafer, and removing the carrier.

Abstract: Electronic modules are formed by encapsulating microelectronic dies within cavities in a substrate.

Abstract: A method of making a semiconductor chip assembly includes providing a bump and a ledge, mounting an adhesive on the ledge including inserting the bump into an opening in the adhesive, mounting a conductive layer on the adhesive including aligning the bump with an aperture in the conductive layer, then flowing the adhesive between the bump and the conductive layer, solidifying the adhesive, then providing a conductive trace that includes a pad, a terminal and a selected portion of the conductive layer, then mounting a semiconductor device on the bump opposite a cavity in the bump, wherein a heat spreader includes the bump and a base that includes a portion of the ledge adjacent to the bump, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader.

Abstract: An integrated circuit 15 is placed onto a lead frame 101 having lead fingers 109 of substantially constant thickness along their length. Wires are formed from the lead fingers 109 to corresponding electrical contacts the integrated circuit. Following the wire bonding process, the thickness of the tips of the lead fingers 109 is reduced by a laser process, to form tips of reduced thickness desirable for a subsequent moulding operation. Thus, at the time of the wire bonding the tips of the fingers 109 need not have a gap beneath them, so that more secure wire bonds to the lead fingers 109 can be formed.

Abstract: A manufacturing method of a substrate for a semiconductor element, wherein a first step includes: forming a first and second photosensitive resin layer on a first and second surface of a metal plate, respectively; forming a first and second resist pattern on the first and second surface, for forming a connection post and a wiring pattern, respectively. A second step includes: forming the connection post and wiring pattern; filling in a premold liquid resin to the first surface which was etched; forming a premold resin layer by hardening the premold liquid resin; performing a grinding operation on the first surface, and exposing an upper bottom surface of the connection post from the premold resin layer. A groove structure is formed by the first and second steps, wherein a depth of the groove is up to an intermediate part in a thickness direction of the metal plate.

Abstract: A method of manufacturing an integrated circuit package includes mounting a large panel leadframe having a substantially square shape to a ring. The large panel leadframe includes a plurality of die pads and a corresponding plurality of leads arranged in a matrix pattern. An integrated circuit chip is attached to each of the die pads. An encapsulant material is applied over the integrated circuit chips and at least a part of the large panel leadframe. Each of the die pads and its corresponding leads are separated from the large panel leadframe to form individual integrated circuit packages. The steps of attaching the integrated circuit chips and applying the encapsulant material are performed while the large panel leadframe is mounted to a taped ring.

Abstract: A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.

Abstract: An integrated circuit containing logic transistors and an array of SRAM cells in which the logic transistors are formed in semiconductor material with one crystal orientation and the SRAM cells are formed in a second semiconductor layer with another crystal orientation. A process of forming an integrated circuit containing logic transistors and an array of SRAM cells in which the logic transistors are formed in a top semiconductor layer with one crystal orientation and the SRAM cells are formed in an epitaxial semiconductor layer with another crystal orientation. A process of forming an integrated circuit containing logic transistors and an array of SRAM cells in which the SRAM cells are formed in a top semiconductor layer with one crystal orientation and the logic transistors are formed in an epitaxial semiconductor layer with another crystal orientation.

Abstract: An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.