Distinctly Layered Product (e.g., Twin, Soi, Epitaxial Crystallization) Patents (Class 117/43)
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Patent number: 10472229Abstract: A method for fabricating a nanostructure utilizes a templated monocrystalline substrate. The templated monocrystalline substrate is energetically (i.e., preferably thermally) treated, with an optional precleaning and an optional amorphous material layer located thereupon, to form a template structured monocrystalline substrate that includes the monocrystalline substrate with a plurality of epitaxially aligned contiguous monocrystalline pillars extending therefrom. The monocrystalline substrate and the plurality of epitaxially aligned contiguous monocrystalline pillars may comprise the same or different monocrystalline materials.Type: GrantFiled: March 4, 2011Date of Patent: November 12, 2019Assignee: Cornell University—Cornell Center for TechnologyInventors: Ulrich Wiesner, Michael Thompson, Hitesh Arora
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Patent number: 10418238Abstract: Amorphous silicon devices, systems, and related methods are described herein. An example method for fabricating a thin film with light-emitting or light-detecting capability can include depositing a thin film of amorphous silicon on a wafer such that crystalline defects are distributed throughout the thin film. Additionally, an example photonic device can include a p-doped region and an n-doped region formed on a wafer, and a resonator structure formed on the wafer. The resonator structure can be formed from amorphous silicon and can be arranged between the p-doped and n-doped regions to form a PIN junction. Optionally, the photonic device can be incorporated into a monolithic integrated optical system.Type: GrantFiled: May 14, 2018Date of Patent: September 17, 2019Assignee: Ohio State Innovation FoundationInventors: Ronald M. Reano, Michael Wood, Ryan Patton
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Patent number: 10090351Abstract: A semiconductor device according to an embodiment includes a low-adhesion film, a pair of substrates, and a metal electrode. The low-adhesion film has lower adhesion to metal than a semiconductor oxide film. The pair of substrates is provided with the low-adhesion film interposed therebetween. The metal electrode passes through the low-adhesion film and connects the pair of substrates, and includes, between the pair of substrates, a part thinner than parts embedded in the pair of substrates. A portion of the metal electrode embedded in one substrate is provided with a gap interposed between the portion and the low-adhesion film on the other substrate.Type: GrantFiled: May 5, 2017Date of Patent: October 2, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hiroaki Ashidate, Kazumasa Tanida
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Patent number: 10032919Abstract: The invention relates to a method for forming a uniform silicide film using a crystalline semiconductor film in which orientation of crystal planes is controlled, and a method for manufacturing a thin film transistor with less variation in electric characteristics, which is formed over an insulating substrate using the silicide film. A semiconductor film over which a cap film is formed is irradiated with a laser to be crystallized under the predetermined condition, so that a crystalline semiconductor film including large grain crystals in which orientation of crystal planes is controlled in one direction is formed. The crystalline semiconductor film is used for silicide, whereby a uniform silicide film can be formed.Type: GrantFiled: September 9, 2015Date of Patent: July 24, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Tomoaki Moriwaka
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Patent number: 9989208Abstract: A light emitting apparatus for a vehicle includes a light source, a diffuser and a beam guider. The light source emits light having a beam pattern with a first imaginary line starting from a center of the beam pattern and extending to a perimeter of the beam pattern and a second imaginary line starting from the center of the beam pattern and extending to the perimeter of the beam pattern at a preset angle relative to the first imaginary line. The first and second imaginary lines have lengths different from each other. The diffuser receives the light of the light source and diffuses the received light to reduce the difference between the lengths of the first and second imaginary lines. The beam guider guides the diffused light along a path to produce an outlet light within a preset range.Type: GrantFiled: July 23, 2015Date of Patent: June 5, 2018Assignee: Hyundai Motor CompanyInventor: Byoung Suk Ahn
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Patent number: 9768109Abstract: An integrated circuit (IC) includes a first semiconductor device on a glass substrate. The first semiconductor device includes a first semiconductive region of a bulk silicon wafer. The IC includes a second semiconductor device on the glass substrate. The second semiconductor device includes a second semiconductive region of the bulk silicon wafer. The IC includes a through substrate trench between the first semiconductive region and the second semiconductive region. The through substrate trench includes a portion disposed beyond a surface of the bulk silicon wafer.Type: GrantFiled: September 22, 2015Date of Patent: September 19, 2017Assignee: QUALCOMM IncorporatedInventors: Shiqun Gu, Daeik Daniel Kim, Matthew Michael Nowak, Jonghae Kim, Changhan Hobie Yun, Je-Hsiung Jeffrey Lan, David Francis Berdy
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Patent number: 9711354Abstract: A template for growing a semiconductor, a method of separating a growth substrate and a method of fabricating a light emitting device using the same are disclosed. The template for growing a semiconductor includes a growth substrate including a nitride substrate; a seed layer disposed on the growth substrate and including at least one trench; and a growth stop layer disposed on a bottom surface of the trench, wherein the trench includes an upper trench and a lower trench, and the upper trench has a smaller width than the lower trench.Type: GrantFiled: December 19, 2014Date of Patent: July 18, 2017Assignee: SEOUL VIOSYS CO., LTD.Inventors: Jong Min Jang, Hee Sub Lee, Won Young Roh, Jong Hyeon Chae, Joon Sup Lee, Daewoong Suh, Hyun A Kim, Seon Min Bae
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Patent number: 9698300Abstract: A method of manufacturing a solar cell is discussed. The method of manufacturing the solar cell includes: forming a conductive region on a semiconductor substrate; forming an electrode connected to the conductive region; and post-processing the semiconductor substrate to passivate the semiconductor substrate. The post-processing of the semiconductor substrate comprises a main processing process for heat-treating the semiconductor substrate while providing light to the semiconductor substrate. A temperature of the main processing process is about 100° C. to about 800° C., and the temperature and light intensity of the main processing process satisfy Equation of 1750?31.8·T+(0.16)·T2?I. Here, T is the temperate (° C.) of the main processing process, and I is the light intensity (mW/cm2) of the main processing process.Type: GrantFiled: June 8, 2015Date of Patent: July 4, 2017Assignee: LG ELECTRONICS INC.Inventors: Kyoungsoo Lee, Minho Choi, Jinhyung Lee, Gyeayoung Kwag, Sangwook Park
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Patent number: 9601428Abstract: Semiconductor fuses with nanowire fuse links and fabrication methods thereof are presented. The methods include, for instance: fabricating a semiconductor fuse, the semiconductor fuse including at least one nanowire fuse link, and the fabricating including: forming at least one nanowire, the at least one nanowire including a semiconductor material; and reacting the at least one nanowire with a metal to form the at least one nanowire fuse link of the semiconductor fuse, the at least one nanowire fuse link including a semiconductor-metal alloy. In another aspect, a structure is presented. The structure includes: a semiconductor fuse, the semiconductor fuse including: at least one nanowire fuse link, the at least one nanowire fuse link including a semiconductor-metal alloy.Type: GrantFiled: September 25, 2015Date of Patent: March 21, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Chun Yu Wong, Jagar Singh, Ashish Baraskar, Min-hwa Chi
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Patent number: 9218964Abstract: Methods of manufacturing a III-V compound semiconductor material, and the semiconductor material thus manufactured, are disclosed. In one embodiment, the method comprises providing a substrate comprising a first semiconductor material having a {001} orientation and an insulating layer overlaying the first semiconductor material. The insulating layer comprises a recessed region exposing an exposed region of the first semiconductor material. The method further comprises forming a buffer layer overlaying the exposed region that comprises a group IV semiconductor material. The method further comprises thermally annealing the substrate and the buffer layer, thereby roughening the buffer layer to create a rounded, double-stepped surface having a step density and a step height. A product of the step density and the step height is greater than or equal to 0.05 on the surface.Type: GrantFiled: August 5, 2011Date of Patent: December 22, 2015Assignees: IMEC, Katholieke Universiteit Leuven, KU Leuven R&DInventors: Gang Wang, Matty Caymax, Maarten Leys, Wei-e Wang, Niamh Waldron
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Patent number: 9214339Abstract: Group III nitride semiconductor having reduced threading dislocation density and uniform Ga-polar surface is provided. Forming a capping layer on a buffer layer containing Al as an essential element at a temperature lower than a temperature at which an oxide of element constituting the buffer layer is formed. Heat treating the substrate having the buffer layer covered by the capping layer at a temperature higher than a temperature at which a crystal of body semiconductor grows without exposing the surface of the buffer layer. The substrate temperature is decreased to a temperature at which a crystal of the body semiconductor grows and the body semiconductor is grown.Type: GrantFiled: February 11, 2014Date of Patent: December 15, 2015Assignee: TOYODA GOSEI CO., LTD.Inventors: Koji Okuno, Takahide Oshio, Naoki Shibata, Hiroshi Amano
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Patent number: 9096928Abstract: Provided is a method of manufacturing a semiconductor device, including: forming a silicon oxide film on a surface of a substrate holder by repeatedly performing forming a silicon-containing layer on the surface of the substrate holder and oxidizing the silicon-containing layer; forming a thin film on a substrate by using a process gas; removing deposits attached onto the substrate holder by using a fluorine-containing gas; and reforming a silicon oxide film on the surface of the substrate holder after removal of the deposits by repeatedly performing forming a silicon-containing layer on the surface of the substrate holder and oxidizing the silicon-containing layer by using an oxygen-containing gas and a hydrogen-containing gas.Type: GrantFiled: September 7, 2011Date of Patent: August 4, 2015Assignee: HITACHI KOKUSAI ELECTRIC INC.Inventors: Ryota Sasajima, Yoshiro Hirose, Naonori Akae, Osamu Kasahara
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Patent number: 9054061Abstract: An OLED display device includes a first oxide semiconductor layer including first to fourth regions; a first gate electrode on a first insulating layer and the first oxide semiconductor layer, and completely overlapping the first region; a first storage electrode extending from the first gate electrode and overlapping the second region; a second insulating layer covering the first gate electrode and the first storage electrode and exposing the third and fourth regions; first source and drain electrodes on the second insulating layer and contacting the third and fourth regions; and an emitting diode connected to the first drain electrode, wherein a portion of the second region at an edge of the first storage electrode except a center of the first storage electrode is conductive to form a second storage electrode, and the first and second storage electrodes and the first insulating layer constitute a first storage capacitor.Type: GrantFiled: November 25, 2014Date of Patent: June 9, 2015Assignee: LG DISPLAY CO., LTD.Inventors: Kyo-Seop Choo, Jong-Uk Bae, Bo-Kyoung Cho
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Patent number: 9048809Abstract: Switchable and/or tunable filters and methods of manufacture. The method of forming the filters includes forming at least one piezoelectric filter structure comprising a plurality of electrodes formed on a piezoelectric substrate. The method further includes forming a micro-electro-mechanical structure (MEMS) comprising a MEMS beam formed above the piezoelectric substrate and at a location in which, upon actuation, the MEMS beam shorts the piezoelectric filter structure by contacting at least one of the plurality of electrodes.Type: GrantFiled: January 3, 2012Date of Patent: June 2, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James W. Adkisson, Panglijen Candra, Thomas J. Dunbar, Jeffrey P. Gambino, Mark D. Jaffe, Anthony K. Stamper, Randy L. Wolf
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Patent number: 8940095Abstract: An apparatus for growth of uniform multi-component single crystals is provided. The single crystal material has at least three elements and has a diameter of at least 50 mm, a dislocation density of less than 100 cm?2 and a radial compositional variation of less than 1%.Type: GrantFiled: November 4, 2011Date of Patent: January 27, 2015Assignee: Rensselaer Polytechnic InstituteInventor: Partha Dutta
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Patent number: 8927376Abstract: A method for forming epitaxial layer is disclosed. The method includes the steps of providing a semiconductor substrate, and forming an undoped first epitaxial layer in the semiconductor substrate. Preferably, the semiconductor substrate includes at least a recess, the undoped first epitaxial layer has a lattice constant, a bottom thickness, and a side thickness, in which the lattice constant is different from a lattice constant of the semiconductor substrate and the bottom thickness is substantially larger than or equal to the side thickness.Type: GrantFiled: April 24, 2014Date of Patent: January 6, 2015Assignee: United Microelectronics Corp.Inventors: Chin-I Liao, Teng-Chun Hsuan, Chin-Cheng Chien
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Publication number: 20140331915Abstract: Inexpensive semiconductors are produced by depositing a single crystal or large grained silicon on an inexpensive substrate. These semiconductors are produced at low enough temperatures such as temperatures below the melting point of glass.Type: ApplicationFiled: July 25, 2014Publication date: November 13, 2014Applicants: TRUSTEES OF DARTMOUTH COLLEGE, SOLAR-TECTIC LLCInventors: Karin Chauchari, Ashok Chaudhari, Pia Chaudhari
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Patent number: 8754448Abstract: A semiconductor device includes a semiconductor substrate and a plurality of transistors. The semiconductor substrate includes at least an iso region (namely an open region) and at least a dense region. The transistors are disposed in the iso region and the dense region respectively. Each transistor includes at least a source/drain region. The source/drain region includes a first epitaxial layer having a bottom thickness and a side thickness, and the bottom thickness is substantially larger than or equal to the side thickness.Type: GrantFiled: November 1, 2011Date of Patent: June 17, 2014Assignee: United Microelectronics Corp.Inventors: Chin-I Liao, Teng-Chun Hsuan, Chin-Cheng Chien
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Patent number: 8585821Abstract: In one embodiment of the present invention, a monocrystal SiC epitaxial substrate is produced which includes a monocrystal SiC substrate; a buffer layer made of a first SiC epitaxial film formed on the monocrystal SiC substrate; and an active layer made of a second SiC epitaxial film formed on the buffer layer. The buffer layer is grown by heat-treating a set of the monocrystal SiC substrate, a carbon source plate, and a metal Si melt layer having a predetermined thickness and interposed between the monocrystal SiC substrate and the metal Si melt layer, so as to epitaxially grow monocrystal SiC on the monocrystal SiC substrate. The active layer is grown by epitaxially growing monocrystal SiC on the buffer layer by vapor phase growth method. This allows for production of a monocrystal SiC epitaxial substrate including a high-quality monocrystal SiC active layer being low in defects.Type: GrantFiled: March 11, 2008Date of Patent: November 19, 2013Assignees: Ecotron Co., Ltd., Research Institute of Innovative Technology for the EarthInventors: Nobuhiko Nakamura, Toru Matsunami, Kimito Nishikawa
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Publication number: 20120273792Abstract: A solar cell comprises a recrystallized layer wherein the recrystallized layer has at least one crystal grain at least 90% of the size of the illuminated area of the solar cell.Type: ApplicationFiled: September 16, 2011Publication date: November 1, 2012Applicant: INTEGRATED PHOTOVOLTAIC, INC.Inventors: Larry Hendler, Sharone Zehavi, De Phuoc Ly
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Publication number: 20120240843Abstract: A method and system is disclosed for making ultra thin wafer(s) or thin film(s) of c-Si on demand. One aspect of certain embodiments includes using a planar seed or crystal template in combination with shaped scanning heat sources to produce an intermediate seed or secondary crystal template, and finally producing an ultra thin wafer or thin film with a single crystal structure over an arbitrary area and film thickness starting from an initial low quality Si coating.Type: ApplicationFiled: March 22, 2011Publication date: September 27, 2012Inventor: Francisco Machuca
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Patent number: 7999319Abstract: The present invention discloses the use of edge-angle-optimized solid phase epitaxy for forming hybrid orientation substrates comprising changed-orientation Si device regions free of the trench-edge defects typically seen when trench-isolated regions of Si are recrystallized to the orientation of an underlying single-crystal Si template after an amorphization step. For the case of amorphized Si regions recrystallizing to (100) surface orientation, the trench-edge-defect-free recrystallization of edge-angle-optimized solid phase epitaxy may be achieved in rectilinear Si device regions whose edges align with the (100) crystal's in-plane <100> directions.Type: GrantFiled: March 7, 2008Date of Patent: August 16, 2011Assignee: International Business Machines CorporationInventors: Katherine L. Saenger, Chun-yung Sung, Haizhou Yin
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Patent number: 7964036Abstract: A crystallization apparatus is provided. In the crystallization apparatus, a light intensity distribution formed by a light modulation device or a metal aperture and transferred to a processed substrate can be visualized. The crystallization apparatus has an ultraviolet (UV) irradiation system and a visible light irradiation system. The UV irradiation system irradiates pulses of laser beam in the UV range to the processed substrate. The visible light irradiation system continuously irradiates a visible light laser beam on the same irradiated region on the processed substrate. In a melted region resulted from the uniform irradiation of the laser beam in the UV range, the light intensity distribution of the visible laser beam is used to form crystal growth. The crystallization apparatus irradiates pulses of the laser beam in the UV range to melt the processed substrate, and continuously irradiates the visible light laser beam to crystallize the processed substrate.Type: GrantFiled: October 29, 2007Date of Patent: June 21, 2011Assignee: Shimadzu CorporationInventors: Noritaka Akita, Yoshio Takami
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Mask for silicon crystallization, method for crystallizing silicon using the same and display device
Patent number: 7892704Abstract: A mask for silicon crystallization capable of minimizing the number of grain boundaries in crystallized silicon, a method for crystallizing silicon using the mask, and a display device are presented. The mask includes a group of slits that are inclined at a predetermined angle with respect to a scan direction and a group of slits including slits inclined at a predetermined angle with respect to the former group of slits. The groups of slits are separated by an interval along the scan direction, and the substrate and/or mask is moved by the interval between irradiation by laser through the slits. Further, there are provided a method for crystallizing silicon using the mask and a display device. By reducing the number of grain boundaries that extend horizontally or vertically on the substrate, the invention obviates a design limitation associated with the directional anisotropy in sequential lateral solidification (SLS) technique.Type: GrantFiled: January 12, 2007Date of Patent: February 22, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Myung Koo Kang, Soong Yong Joo -
Patent number: 7824493Abstract: A method for manufacturing a silicon wafer includes a step of annealing a silicon wafer which is sliced from a silicon single crystal ingot, thereby forming a DZ layer in a first surface and in a second surface of the silicon wafer and a step of removing either a portion of the DZ layer in the first surface or a portion of the DZ layer in the second surface.Type: GrantFiled: July 20, 2005Date of Patent: November 2, 2010Assignee: Sumitomo Mitsubishi Silicon CorporationInventors: Toshiaki Ono, Wataru Sugimura, Masataka Hourai
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Patent number: 7820501Abstract: Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first semiconductor material, the first semiconductor region having a <110> crystal orientation. An epitaxial layer including the first semiconductor material is grown on the first semiconductor region, the epitaxial layer having the <110> crystal orientation. The substrate is then annealed with the epitaxial layer at a temperature greater than 1100 degrees Celsius in an ambient including hydrogen, whereby the step of annealing reduces stacking faults in the epitaxial layer.Type: GrantFiled: October 11, 2006Date of Patent: October 26, 2010Assignees: International Business Machines Corporation, GlobalFoundries, IncInventors: Yun-Yu Wang, Christopher D. Sheraw, Anthony G. Domenicucci, Linda Black, Judson R. Holt, David M. Fried
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Patent number: 7790341Abstract: Provided is a method for crystallizing using a laser mask for selectively crystallizing active regions without a laser shot mark, including: providing an array substrate in which N×M active regions are defined; positioning a laser mask having first and second blocks over the substrate, wherein the first and second blocks have first and second mask patterns, respectively, and the second mask pattern is a reverse pattern of the first mask pattern; irradiating a first laser beam onto the active regions through the first block; and irradiating a second laser beam onto the active regions through the second block.Type: GrantFiled: March 13, 2008Date of Patent: September 7, 2010Assignee: LG Display Co., Ltd.Inventor: JaeSung You
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Patent number: 7648576Abstract: After cleaning the front and back sides of a silicon wafer with a liquid SC-1 and liquid SC-2, the front and back sides of the silicon wafer are cleaned with an HF solution to be water-repellent surfaces. Following that, an epitaxial layer of silicon is formed on the front side. Consequently, there can be reduced stacking faults after formation of the epitaxial layer and occurrence of cloud on the back side. Alternatively, the front and back sides of a silicon wafer are cleaned with the liquid SC-1 and liquid SC-2, and then the back side of the silicon wafer is cleaned with an HF solution to be a water-repellent surface while the front side is cleaned with purified water to be a hydrophilic surf ace. Following that, an epitaxial layer of silicon is formed on the front side. Consequently, there can be reduced mounds on the front side and occurrence of cloud on the back side.Type: GrantFiled: December 10, 2004Date of Patent: January 19, 2010Assignee: SUMCO CorporationInventors: Yasuo Fukuda, Makoto Takemura, Koichi Okuda
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Patent number: 7645337Abstract: In accordance with one aspect, the present invention provides a method for providing polycrystalline films having a controlled microstructure as well as a crystallographic texture. The methods provide elongated grains or single-crystal islands of a specified crystallographic orientation. In particular, a method of processing a film on a substrate includes generating a textured film having crystal grains oriented predominantly in one preferred crystallographic orientation; and then generating a microstructure using sequential lateral solidification crystallization that provides a location-controlled growth of the grains orientated in the preferred crystallographic orientation.Type: GrantFiled: November 18, 2004Date of Patent: January 12, 2010Assignee: The Trustees of Columbia University in the City of New YorkInventors: James S. Im, Paul Christian van der Wilt
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Patent number: 7608144Abstract: A process of lateral crystallization is provided for increasing the lateral growth length (LGL). A localized region of the substrate is heated for a short period of time. While the localized region of the substrate is still heated, a silicon film overlying the substrate is irradiated to anneal the silicon film to crystallize a portion of the silicon film in thermal contact with the heated substrate region. A CO2 laser may be used as a heat source to heat the substrate, while a UV laser or a visible spectrum laser is used to irradiate and crystallize the film.Type: GrantFiled: October 31, 2005Date of Patent: October 27, 2009Assignee: Sharp Laboratories of America, Inc.Inventors: Apostolos T. Voutsas, Robert S. Sposili, Mark A. Crowder
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Patent number: 7518187Abstract: The present invention is an SOI wafer in which at least a silicon active layer is formed over a support substrate via an insulator film or on a support substrate directly, wherein, at least, the silicon active layer consists of a P(phosphorus)-doped silicon single crystal grown by Czochralski method, which is occupied by N region and/or defect-free I region, and contains Al (aluminum) with concentration of 2×1012 atoms/cc or more. There can be provided with ease and at low cost an SOI wafer with high electrical reliability in a device fabrication process, that has an excellent electric property without generation of micro pits by cleaning with hydrofluoric acid etc. even in the case of forming an extremely thin silicon active layer, or that retains high insulation property even in the case of forming an extremely thin inter-layer insulator film.Type: GrantFiled: March 12, 2004Date of Patent: April 14, 2009Assignee: Shin-Etsu Handotai Co., Ltd.Inventor: Masahiro Sakurada
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Patent number: 7431766Abstract: Processing and systems to create, and resulting products related to, very small-dimension singular, or monolithically arrayed, mechanical devices. Processing is laser-performed in relation to a selected material whose internal crystalline structure becomes appropriately changed thereby to establish the desired mechanical properties for a created device.Type: GrantFiled: September 14, 2005Date of Patent: October 7, 2008Assignee: Sharp Laboratories of America, Inc.Inventor: John W. Hartzell
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Patent number: 7396407Abstract: The present invention discloses the use of edge-angle-optimized solid phase epitaxy for forming hybrid orientation substrates comprising changed-orientation Si device regions free of the trench-edge defects typically seen when trench-isolated regions of Si are recrystallized to the orientation of an underlying single-crystal Si template after an amorphization step. For the case of amorphized Si regions recrystallizing to (100) surface orientation, the trench-edge-defect-free recrystallization of edge-angle-optimized solid phase epitaxy may be achieved in rectilinear Si device regions whose edges align with the (100) crystal's in-plane <100> directions.Type: GrantFiled: April 18, 2006Date of Patent: July 8, 2008Assignee: International Business Machines CorporationInventors: Katherine L. Saenger, Chun-yung Sung, Haizhou Yin
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Patent number: 7384476Abstract: A method for crystallizing silicon is provided. The method includes: forming an amorphous silicon layer on a substrate; aligning a mask above the substrate, the mask being divided into a plurality of blocks, each block having at least two transmission patterns, the transmission patterns of one block and the transmission patterns of another adjacent block being complimentary with each other and the mask including at least two diffraction patterns disposed between the transmission patterns; forming a first crystallization region on the amorphous silicon layer by irradiating a laser beam through the transmission patterns of the mask; and displacing the substrate or the mask by a predetermined distance and irradiating a laser beam onto the substrate to recrystallize the crystallization region using the laser beam that passes through the diffraction patterns, and forming a second crystallization region using the laser beam that passes through the transmission patterns.Type: GrantFiled: May 24, 2004Date of Patent: June 10, 2008Assignee: LG Display Co., Ltd.Inventor: JaeSung You
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Publication number: 20080115718Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: depositing an amorphous silicon layer on an insulating substrate; converting the amorphous silicon layer to a polysilicon layer by a plurality of laser shots using a mask; forming a gate insulating layer on the polysilicon layer; forming a plurality of gate lines on the gate insulating layer; forming a first interlayer insulating layer on the gate lines; forming a plurality of data lines on the first interlayer insulating layer; forming a second interlayer insulating layer on the data lines; and forming a plurality of pixel electrodes on the second interlayer insulating layer, wherein the mask comprises a plurality of transmitting areas and a plurality of blocking areas arranged in a mixed manner.Type: ApplicationFiled: October 3, 2007Publication date: May 22, 2008Inventors: Hyun-Jae Kim, Sook-Young Kang, Dong-Byum Kim, Su-Gyeong Lee, Myung-Koo Kang
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Publication number: 20080118754Abstract: A method of fabricating a single crystal silicon rod may include forming an insulation layer on a substrate, forming a hole in the insulation layer, selectively growing silicon in the hole, forming a silicon layer on the hole and on the insulation layer, forming a rod pattern on the silicon layer in a direction that is non-radial with respect to the hole, and melting the silicon layer and crystallizing the silicon layer by illuminating a laser beam on the silicon layer where the rod pattern is formed to generate a nucleation site at a position corresponding to the hole. According to the method, a single crystal silicon rod having no defects may be formed.Type: ApplicationFiled: October 19, 2007Publication date: May 22, 2008Inventors: Wenxu Xianyu, Young-soo Park, Hans S. Cho, Huaxiang Yin, Hyuck Lim
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Patent number: 7351283Abstract: A crystalline thin structure (104, 204, 404) is grown on a surface (108, 228) of a substrate (112, 208, 400) by depositing molecules (136, 220) from a molecular precursor to a lateral growth front (144, 224) of the structure using a crystal grower (116, 200). In one embodiment, the crystal grower comprises a solution (124) containing the molecular precursor in a solvent (140). Molecules are added to the lateral growth front by moving one or both of the free surface (120, 120?) of the solution and deposition surface relative to the other at a predetermined rate. In another embodiment, the crystal grower comprises a mask (212) that includes at least one opening (216). Precursor molecules are vacuum deposited via a molecular beam (236) at the growth front (228) of the crystalline thin structure (204) as one or both of the opening and surface are moved relative to the other at a predetermined rate.Type: GrantFiled: March 11, 2005Date of Patent: April 1, 2008Assignee: The University of Vermont and State Agricultural CollegeInventor: Randall L. Headrick
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Patent number: 7320732Abstract: A method for preparing film oxides deposited on a substrate with a resulting grain boundary junction that is atomistically straight. A bicrystal substrate having a straight grain boundary is prepared as a template. The Miller indices h1, k1, h2, k2 of the two grains of the substrate are chosen such that the misorientation angle of the film is equal to arctan k1/h1+arctan k2/h2. The film is grown on the substrate using a layer-by-layer growth mode.Type: GrantFiled: July 27, 2005Date of Patent: January 22, 2008Assignee: The Trustees of Columbia University in the City of New YorkInventor: Siu-Wai Chan
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Patent number: 7311778Abstract: A method of processing a polycrystalline film on a substrate includes generating a plurality of laser beam pulses, positioning the film on a support capable of movement in at least one direction, directing the plurality of laser beam pulses through a mask to generate patterned laser beams; each of said beams having a length l?, a width w? and a spacing between adjacent beams d?, irradiating a region of the film with the patterned beams, said beams having an intensity that is sufficient to melt an irradiated portion of the film to induce crystallization of the irradiated portion of the film, wherein the film region is irradiated n times; and after irradiation of each film portion, translating either the film or the mask, or both, a distance in the x- and y-directions, where the distance of translation in the y-direction is in the range of about 1?/n-?, where ? is a value selected to form overlapping the beamlets from the one irradiation step to the next, and where the distance of translation in the x-directionType: GrantFiled: September 17, 2004Date of Patent: December 25, 2007Assignee: The Trustees of Columbia University in the City of New YorkInventors: James S. Im, Paul Christiaan van der Wilt
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Publication number: 20070277728Abstract: A wafer having a silicon layer that is strained is used to form transistors. The silicon layer is formed by first forming a silicon germanium (SiGe) layer of at least 30 percent germanium that has relaxed strain on a donor wafer. A thin silicon layer is epitaxially grown to have tensile strain on the relaxed SiGe layer. The amount tensile strain is related to the germanium concentration. A high temperature oxide (HTO) layer is formed on the thin silicon layer by reacting dichlorosilane and nitrous oxide at a temperature of preferably between 800 and 850 degrees Celsius. A handle wafer is provided with a supporting substrate and an oxide layer that is then bonded to the HTO layer. The HTO layer, being high density, is able to hold the tensile strain of the thin silicon layer. The relaxed SiGe layer is cleaved then etched away to expose the thin silicon layer.Type: ApplicationFiled: May 30, 2006Publication date: December 6, 2007Inventors: Mariam G. Sadaka, Alexander L. Barr, Bich-Yen Nguyen, Voon-Yew Thean, Ted R. White
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Patent number: 7294197Abstract: Metallurgical grade silicon or high purity silicon beads developed from a fluidized bed process are melted in a cooled aluminum crucible, such that a non wetted interface is created between the molten silicon and a cooled supporting substrate that includes a surface layer of substantially inert aluminum oxide. It is believed that the molten silicon does not wet the surface of the supporting substrate and the surface of the supporting substrate does not chemically interact with the silicon. It is shown that, in spite of the enormous temperature difference, molten silicon (ca. 1450° C.) can be stabilized, by appropriate energy control, in direct (but non-wetted) contact with cold (ca. 40° C.) material such as aluminum.Type: GrantFiled: August 13, 2004Date of Patent: November 13, 2007Inventor: Nicholas Gralenski
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Patent number: 7276317Abstract: A laser mask and method of crystallization using the same that can produce a polycrystalline silicon thin film having uniform crystallization characteristics. According to the present invention, a method of crystallization using a laser mask having a reference pattern in a first block and the reverse pattern of the reference pattern in a second block includes providing a substrate having a silicon thin film; positioning the first block of the laser mask over a portion of the silicon film and irradiating a first laser beam through the first block; and moving either the laser mask or the substrate to position the second block of the laser mask over the portion of the silicon film and irradiating a second laser beam through the second block.Type: GrantFiled: December 14, 2004Date of Patent: October 2, 2007Assignee: LG.Philips LCD Co., Ltd.Inventor: JaeSung You
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Patent number: 7192481Abstract: A radiation detector made from a compound, or alloy, comprising CdxZn1?xTe (0=x=1), Pb in a concentration between 10 and 10,000 atomic parts per billion and at least one element selected from the group consisting of (i) Cl and (ii) elements in column III of the periodic table in a concentration between 10 and 10,000 atomic parts per billion. The radiation detector exhibits full electrical compensation, high-resistivity, full depletion under an applied electrical bias and excellent charge transport.Type: GrantFiled: June 10, 2003Date of Patent: March 20, 2007Assignee: II-VI IncorporatedInventors: Csaba Szeles, Kelvin G. Lynn
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Patent number: 7169226Abstract: A method of fabricating high-quality, substantially relaxed SiGe-on-insulator substrate materials which may be used as a template for strained Si is described. A silicon-on-insulator substrate with a very thin top Si layer is used as a template for compressively strained SiGe growth. Upon relaxation of the SiGe layer at a sufficient temperature, the nature of the dislocation motion is such that the strain-relieving defects move downward into the thin Si layer when the buried oxide behaves semi-viscously. The thin Si layer is consumed by oxidation of the buried oxide/thin Si interface. This can be accomplished by using internal oxidation at high temperatures. In this way the role of the original thin Si layer is to act as a sacrificial defect sink during relaxation of the SiGe alloy that can later be consumed using internal oxidation.Type: GrantFiled: July 1, 2003Date of Patent: January 30, 2007Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Huajie Chen, Anthony G. Domenicucci, Keith E. Fogel, Devendra K. Sadana
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Patent number: 7153359Abstract: A crystalline semiconductor film, the crystalline semiconductor film being formed over an insulative substrate, and including semiconductor crystal grains laterally grown along a surface of the insulative substrate, wherein the laterally-grown semiconductor crystal grains are in contact with each other at grain boundaries, and a distance between adjacent grain boundaries is equal to or smaller than two times a lateral growth distance of the semiconductor crystal grains.Type: GrantFiled: September 25, 2002Date of Patent: December 26, 2006Assignee: Sharp Kabushiki KaishaInventors: Masashi Maekawa, Keiichi Fukuyama, Michinori Iwai, Kohei Tanaka
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Patent number: 7135070Abstract: Monolithic stacked/layered room-temperature-processed materials whose internal crystalline structures are laser modification to create arrays of mechanical, and combined mechanical and electrical, devices with precision-established properties, such as important mechanical properties. Methodology and system configurations are disclosed.Type: GrantFiled: April 23, 2002Date of Patent: November 14, 2006Assignee: Sharp Laboratories of America, Inc.Inventor: John W. Hartzell
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Patent number: 7128783Abstract: Thin-film laser-effected internal crystalline structure modified materials suitable for the creation of various small-dimension mechanical devices, either singly or in monolithic arrays, such as MEMS devices. Processing is carried out at room temperature and atmospheric pressure.Type: GrantFiled: April 23, 2002Date of Patent: October 31, 2006Assignee: Sharp Laboratories of America, Inc.Inventor: John W. Hartzell
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Patent number: 7125451Abstract: Laser processing of various materials to create mechanical devices whose internal mechanical properties are provided in final useable form by adjustments made in internal crystalline structure.Type: GrantFiled: April 23, 2002Date of Patent: October 24, 2006Assignee: Sharp Laboratories of America, Inc.Inventor: John W. Hartzell
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Patent number: 7105048Abstract: Each region, which should be left on a substrate after patterning, of a semiconductor film is grasped in accordance with a mask. Then, each region to be scanned with laser light is determined so that at least the region to be obtained through the patterning is crystallized, and a beam spot is made to hit the region to be scanned, thereby partially crystallizing the semiconductor film. Each portion with low output energy of the beam spot is shielded by a slit. In the present invention, the laser light is not scanned and irradiated onto the entire surface of the semiconductor film but is scanned such that at least each indispensable portion is crystallized to a minimum. With the construction described above, it becomes possible to save time taken to irradiate the laser light onto each portion to be removed through the patterning after the crystallization of the semiconductor film.Type: GrantFiled: November 27, 2002Date of Patent: September 12, 2006Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hisashi Ohtani, Masaaki Hiroki, Koichiro Tanaka, Aiko Shiga, Satoshi Murakami, Mai Akiba
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Patent number: 7056382Abstract: A method of crystallizing an amorphous silicon layer includes the steps of generating an excimer laser beam having a first energy density and a second energy density, irradiating an amorphous silicon layer with at least one exposure of the excimer, wherein the first energy density melts the amorphous silicon layer to a first depth from a surface of the amorphous silicon layer equal to the first thickness and the second energy density melts the amorphous silicon layer to a second depth from the surface of the amorphous silicon layer less than the first thickness.Type: GrantFiled: October 21, 2003Date of Patent: June 6, 2006Assignee: LG.Philips LCD Co., Ltd.Inventor: Se-Jin Chung