With Pretreatment Of Epitaxy Substrate (e.g., Autodoping Control, Cleaning, Polishing, Leveling, Masking) Patents (Class 117/58)
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Publication number: 20120043644Abstract: A method of manufacturing a silicon wafer provides a silicon wafer which can reduce the precipitation of oxygen to prevent a wafer deformation from being generated and can prevent a slip extension due to boat scratches and transfer scratches serving as a reason for a decrease in wafer strength, even when the wafer is provided to a rapid temperature-rising-and-falling thermal treatment process.Type: ApplicationFiled: March 25, 2010Publication date: February 23, 2012Applicant: SUMCO CORPORATIONInventors: Toshiaki Ono, Wataru Ito, Jun Fujise
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Publication number: 20120034550Abstract: Palladium-seeded, dendritic platinum nanostructures that are useful as electrocatalysts and methods for preparing such nanostructures. The palladium-platinum nanostructures may be incorporated into fuel cell electrodes including fuel cells that include a proton exchange membrane (PEM).Type: ApplicationFiled: April 20, 2010Publication date: February 9, 2012Applicant: WASHINGTON UNIVERSITY IN ST. LOUISInventors: Younan Xia, Byungkwon Lim, Majiong Jiang
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Publication number: 20120017825Abstract: A method for growing a crystalline composition, the first crystalline composition may include gallium and nitrogen. The crystalline composition may have an infrared absorption peak at about 3175 cm?1, with an absorbance per unit thickness of greater than about 0.01 cm?1. In one embodiment, the composition ay have an amount of oxygen present in a concentration of less than about 3×1018 per cubic centimeter, and may be free of two-dimensional planar boundary defects in a determined volume of the first crystalline composition.Type: ApplicationFiled: November 9, 2006Publication date: January 26, 2012Applicant: General Electric CompanyInventors: Mark Philip D'Evelyn, Kristi Jean Narang, Dong-Sil Park, Huicong Hong, Xian-An Cao, Larry Qiang Zeng
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Publication number: 20110265708Abstract: Epitaxy is carried out by immersing a single crystal substrate having a first principal surface, a second principal surface and a dislocation exposed on the first principal surface into an electrolytic solution including a cation of a metal having a melting point; carrying out electrolytic plating on the first principal surface to deposit the metal on the dislocation so as to cover the dislocation with the metal but leave a portion of the first principal surface where the dislocation is exposed uncovered with the metal; and causing epitaxy of a semiconductor layer on both the portion of the first principal surface and the metal covering the dislocation at a temperature below the melting point.Type: ApplicationFiled: April 26, 2011Publication date: November 3, 2011Applicant: Sanken Electric Co., Ltd.Inventor: Ken SATO
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Publication number: 20110247548Abstract: Disclosed herein are a method for preparing zinc oxide (ZnO) nanoparticles and a method for preparing ZnO nanorods. The method for preparing ZnO nanoparticles may include: preparing a growth solution containing a zinc salt, a precipitator, and a growth inhibitor; and applying heat to the growth solution to prepare ZnO nanoparticles. Moreover, the method for preparing ZnO nanorods may include: forming a ZnO seed layer on a substrate; forming a pattern layer including a plurality of holes on the ZnO seed layer; preparing a growth solution containing a zinc salt, a precipitator, and a growth inhibitor; and immersing the substrate including the pattern layer in the growth solution such that ZnO nanorods are grown in the holes.Type: ApplicationFiled: April 12, 2011Publication date: October 13, 2011Applicant: GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Gun-Young JUNG, Ki-Seok KIM
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Publication number: 20110232564Abstract: In a method of growing GaN crystal in one aspect, the following steps are performed. An underlying substrate is prepared. Then, a mask layer having an opening portion and composed of SiO2 is formed on the underlying substrate. Then, GaN crystal is grown on the underlying substrate and the mask layer. The mask layer has surface roughness Rms not greater than 2 nm or a radius of curvature not smaller than 8 m. In a method of growing GaN crystal in one aspect, the following steps are performed. An underlying substrate is prepared. Then, using a resist, a mask layer having an opening portion is formed on the underlying substrate. Then, the underlying substrate and the mask layer are cleaned with an acid solution. Then, after of cleaning with an acid solution, the underlying substrate and the mask layer are cleaned with an organic solvent. Then, GaN crystal is grown on the underlying substrate and the mask layer.Type: ApplicationFiled: November 26, 2009Publication date: September 29, 2011Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventor: Tomoharu Takeyama
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Publication number: 20110237441Abstract: A method is proposed for producing a biaxially textured metal substrate having a metal surface, wherein the substrate is modified in order to produce a high-temperature superconductor coating arrangement and wherein the metal surface is modified in order to deposit a buffer layer or another intermediate layer epitaxially thereon and/or to deposit an oriented high-temperature superconductor (HTS) layer thereon. The method includes producing a biaxially textured metal substrate, subjecting the metal substrate surface to a polishing treatment, in particular an electropolishing treatment, and subjecting the metal substrate to a post-annealing after the surface polishing treatment and before a subsequent coating is performed involving epitaxial deposition of a layer of the HTS coating arrangement. This method results in smooth metal substrates with high textural overcoats and thereby improved HTS layers.Type: ApplicationFiled: November 24, 2009Publication date: September 29, 2011Applicant: ZENERGY POWER GMBHInventors: Michael Baecker, Martina Falter, Jan Kunert
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Publication number: 20110193196Abstract: Affords methods of manufacturing InP substrates, methods of manufacturing epitaxial wafers, InP substrates, and eptiaxial wafers whereby deterioration of the electrical characteristics can be kept under control, and at the same time, deterioration of the PL characteristics can be kept under control. An InP substrate manufacturing method of the present invention is provided with the following steps. An InP substrate is prepared (Steps S1 through S3). The InP substrate is washed with sulfuric acid/hydrogen peroxide (Step S5). After the step of washing with sulfuric acid/hydrogen peroxide (Step S5), the InP substrate is washed with phosphoric acid (Step S6).Type: ApplicationFiled: January 12, 2010Publication date: August 11, 2011Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventor: Kyoko Okita
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Patent number: 7993453Abstract: A method for the production of an SiC single crystal includes the steps of growing a first SiC single crystal in a first direction of growth on a first seed crystal formed of an SiC single crystal, disposing the first SiC single crystal grown on the first seed crystal in a direction parallel or oblique to the first direction of growth and cutting the disposed first SiC single crystal in a direction of a major axis in a cross section perpendicular to the first direction of growth to obtain a second seed crystal, using the second seed crystal to grow thereon in a second direction of growth a second SiC single crystal to a thickness greater than a length of the major axis in the cross section, disposing the second SiC single crystal grown on the second seed crystal in a direction parallel or oblique to the second direction of growth and cutting the disposed second SiC single crystal in a direction of a major axis in a cross section perpendicular to the second direction of growth to obtain a third seed crystal, uType: GrantFiled: May 10, 2007Date of Patent: August 9, 2011Assignee: Showa Denko K.K.Inventors: Naoki Oyanagi, Tomohiro Syounai, Yasuyuki Sakaguchi
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Patent number: 7988784Abstract: It is used a substrate main body 1 having a side face 1b and a pair of main faces 1a and an underlying film 2 of a single crystal of a nitride of a metal belonging to the group III formed at least on one main face of the substrate main body 1. A single crystal 3 of a nitride of a metal belonging to the group III is grown on the main face 1a of the substrate main body 1 by a liquid phase process. The underlying film 2 has a shape of a convex figure in a plan view. A surface 4 without the underlying film thereon surrounds the entire circumference of the underlying film 2. The single crystal 3 of a nitride of a metal belonging to the group III grown on the underlying film 2 is not brought into contact with a single crystal of a nitride of a metal belonging to group III formed on another underlying film.Type: GrantFiled: July 23, 2010Date of Patent: August 2, 2011Assignee: NGK Insulators, Ltd.Inventors: Takayuki Hirao, Katsuhiro Imai, Mikiya Ichimura
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Publication number: 20110100292Abstract: A method for growing a GaN crystal includes a step of preparing a substrate (10) that includes a main surface (10m) and includes a Gax Aly In1-x-y N seed crystal (10a) including the main surface (10m) and a step of growing a GaN crystal (20) on the main surface (10m) at an atmosphere temperature of 800° C. or more and 1500° C. or less and at an atmosphere pressure of 500 atmospheres or more and less than 2000 atmospheres by bringing a solution (7) provided by dissolving (5) nitrogen in a Ga melt (3) into contact with the main surface (10m) of the substrate (10). The method further includes, after the step of preparing the substrate (10) and before the step of growing the GaN crystal (20), a step of etching the main surface (10m) of the substrate (10). Thus, a method for growing a GaN crystal having a low dislocation density and high crystallinity is provided without adding impurities other than raw materials to the melt and without increasing the size of a crystal growth apparatus.Type: ApplicationFiled: July 14, 2009Publication date: May 5, 2011Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Koji Uematsu, Hiroaki Yoshida, Masanori Morishita, Shinsuke Fujiwara
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Publication number: 20110089431Abstract: A method for producing a compound single crystal includes a process (I) of growing the compound single crystal while causing an anti-phase boundary and a stacking fault to equivalently occur in a <110> direction parallel to the surface, the stacking fault being attributable to the elements A and B; a process (II) of merging and annihilating the stacking fault, attributable to the element A, and the anti-phase boundary, which occurs in the process (I); a process (III) of vanishing the stacking fault attributable to the element B, which occurs in the process (I); and a process (IV) of completely merging and annihilating the anti-phase boundary. The process (IV) is carried out simultaneously with the processes (II) and (III) or after the processes (II) and (III).Type: ApplicationFiled: October 15, 2010Publication date: April 21, 2011Applicant: HOYA CORPORATIONInventors: Kuniaki YAGI, Takahisa SUZUKI, Yasutaka YANAGISAWA, Masao HIROSE, Noriko SATO, Junya KOIZUMI, Hiroyuki NAGASAWA
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Publication number: 20110030610Abstract: This disclosure enables high-productivity fabrication of semiconductor-based separation layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers), optical reflectors (made of multi-layer/multi-porosity porous semiconductors such as porous silicon), formation of porous semiconductor (such as porous silicon) for anti-reflection coatings, passivation layers, and multi-junction, multi-band-gap solar cells (for instance, by forming a variable band gap porous silicon emitter on a crystalline silicon thin film or wafer-based solar cell). Other applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation).Type: ApplicationFiled: May 5, 2010Publication date: February 10, 2011Applicant: SOLEXEL, INC.Inventors: George D. Kamian, Somnath Nag, Subbu Tamilmani, Mehrdad M. Moslehi, Karl-Josef Kramer, Takao Yonehara
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Publication number: 20100307404Abstract: It is used a substrate main body 1 having a side face 1b and a pair of main faces 1a and an underlying film 2 of a single crystal of a nitride of a metal belonging to the group III formed at least on one main face of the substrate main body 1. A single crystal 3 of a nitride of a metal belonging to the group III is grown on the main face 1a of the substrate main body 1 by a liquid phase process. The underlying film 2 has a shape of a convex figure in a plan view. A surface 4 without the underlying film thereon surrounds the entire circumference of the underlying film 2 The single crystal 3 of a nitride of a metal belonging to the group III grown on the underlying film 2 is not brought into contact with a single crystal of a nitride of a metal belonging to group III formed on another underlying film.Type: ApplicationFiled: July 23, 2010Publication date: December 9, 2010Applicant: NGK Insulators, Ltd.Inventors: Takayuki Hirao, Katsuhiro Imai, Mikiya Ichimura
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Publication number: 20100229786Abstract: A III-nitride crystal growth method that enables growing large-scale crystal under a liquid-phase technique is made available. The present III-nitride crystal growth method is a method of growing III-nitride crystal (10) by a liquid-phase technique, and is provided with: a step of preparing a III-nitride crystal substrate (1) having the same chemical composition as the III-nitride crystal (10), and having a thickness of not less than 0.5 mm; and a step of contacting onto a major surface (1m) of the III-nitride crystal substrate (1) a solution in which a nitrogen-containing gas (5) is dissolved in a solvent (3) that includes a Group-III metal, to grow III-nitride crystal (10) onto the major surface (1m).Type: ApplicationFiled: September 19, 2008Publication date: September 16, 2010Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Koji Uematsu, Hiroaki Yoshida, Ryu Hirota, Shinsuke Fujiwara, Haruko Tanaka
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Publication number: 20100129996Abstract: A method of surface treatment for silicon material. The method includes providing a first silicon material having a surface region. The first silicon material has a first purity characteristics and a first surface roughness characteristics. A chemical polishing process is perform to the surface region to cause the surface region to have a second roughness characteristics. Thereafter, a chemical leaching process is performed to the surface region to cause the first silicon material in a depth within a vicinity of the surface region to have a second purity characteristics. A polysilicon material characterized by a grain size greater than about 0.1 mm is formed using a deposition process overlying the surface region.Type: ApplicationFiled: April 28, 2009Publication date: May 27, 2010Applicant: Jian Zhong YuanInventor: JIAN ZHONG YUAN
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Patent number: 7641988Abstract: A self-supported nitride semiconductor substrate of 10 mm or more in diameter having an X-ray diffraction half width of 500 seconds or less in at least one of a {20-24} diffraction plane and a {11-24} diffraction plane.Type: GrantFiled: April 12, 2004Date of Patent: January 5, 2010Assignee: Hitachi Cable, Ltd.Inventor: Takayuki Suzuki
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Patent number: 7641736Abstract: A method of manufacturing an SiC single crystal wafer according to the present invention includes the steps of: (a) preparing an SiC single crystal wafer 10 with a mirror-polished surface; (b) oxidizing the surface of the SiC single crystal wafer 10 with plasma, thereby forming an oxide layer 12 on the surface of the SiC single crystal wafer; and (c) removing at least a portion of the oxide layer 12 by a reactive ion etching process. Preferably, the surface of the wafer is planarized by repeatedly performing the steps (b) and (c) a number of times.Type: GrantFiled: February 22, 2005Date of Patent: January 5, 2010Assignee: Hitachi Metals, Ltd.Inventor: Taisuke Hirooka
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Publication number: 20090155580Abstract: To provide a semiconductor substrate of high quality suitable for fabricating an electronic device or an optical device. The present invention provides a method for producing a semiconductor substrate for an electronic device or an optical device, the method including reacting nitrogen (N) with gallium (Ga), aluminum (Al), or indium (In), which are group III elements, in a flux mixture containing a plurality of metal elements selected from among alkali metals and alkaline earth metals, to thereby grow a group III nitride based compound semiconductor crystal. The group III nitride based compound semiconductor crystal is grown while the flux mixture and the group III element are mixed under stirring.Type: ApplicationFiled: April 5, 2007Publication date: June 18, 2009Inventors: Naoki Shibata, Koji Hirata, Shiro Yamazaki, Katsuhiro Imai, Makoto Iwai, Takatomo Sasaki, Yusuke Mori, Fumio Kawamura
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Patent number: 7535082Abstract: Nitride semiconductor wafers which are produced by epitaxially grown nitride films on a foreign undersubstrate in vapor phase have strong inner stress due to misfit between the nitride and the undersubstrate material. A GaN wafer which has made by piling GaN films upon a GaAs undersubstrate in vapor phase and eliminating the GaAs undersubstrate bends upward due to the inner stress owing to the misfit of lattice constants between GaN and GaAs. Ordinary one-surface polishing having the steps of gluing a wafer with a surface on a flat disc, bringing another surface in contact with a lower turntable, pressing the disc, rotating the disc, revolving the turntable and whetting the lower surface, cannot remedy the inherent distortion. The Distortion worsens morphology of epitaxial wafers, lowers yield of via-mask exposure and invites cracks on surfaces. Nitride crystals are rigid but fragile. Chemical/mechanical polishing has been requested in vain.Type: GrantFiled: February 11, 2005Date of Patent: May 19, 2009Assignees: Sumitomo Electric Industries, Ltd., Sony CorporationInventors: Masahiro Nakayama, Naoki Matsumoto, Koshi Tamamura, Masao Ikeda
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Publication number: 20080295762Abstract: Disclosed is a method for producing, controlling the shape and size oft Pb-chalcogenide nanoparticles. The method includes preparing a Pb (Pb) precursor containing Pb and a carboxylic acid dissolved in a hydrocarbon solution and preparing a chalcogen element precursor containing a chalcogen element dissolved in a hydrocarbon solution. The amount of Pb and chalcogen in the respective precursor affords for a predetermined Pb:chalcogen element ratio to be present when the Pb precursor is mixed with the chalcogen element precursor. The Pb precursor is mixed with the chalcogen element precursor to form a Pb-chalcogen mixture in such a manner that Pb-chalcogenide nanoparticle nucleation does not occur. A nucleation and growth solution containing a surfactant is also prepared by heating the solution to a nucleation temperature sufficient to nucleate nanoparticles when the Pb-chalcogen element mixture is added.Type: ApplicationFiled: May 30, 2007Publication date: December 4, 2008Applicants: Toyota Engineering & Manufacturing North America, Inc., University of California, BerkeleyInventors: Taleb Mokari, Minjuan Zhang, Peidong Yang
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Patent number: 7459614Abstract: It is the aim of the invention to provide a technology for the stimulation of the crystallization of biomolecules contained in a liquid solution that leads to significant improvements in the reliability of crystal growth processes and shortens the time and the number of attempts to grow a certain biomolecule crystal, also under the condition that only very small amounts of the biomolecules are available.Type: GrantFiled: August 12, 2004Date of Patent: December 2, 2008Assignee: Paul Scherrer InstitutInventors: Celestino Padeste, Christian Kambach, Jens Grobrecht, Harun Solak
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Publication number: 20080237660Abstract: A semiconductor device and a method to fabricate a semiconductor device on a silicon substrate are illustrated. The semiconductor may comprise an amorphous silicon film, in the source/drain region of a semiconductor, having low amount of hydrogen and high concentration of carbon and phosphorous, which enhances performance of the semiconductor device.Type: ApplicationFiled: March 30, 2007Publication date: October 2, 2008Inventors: Ajay K. Sharma, Anand Murthy, Din-How Mei, Dennis Hanken
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Patent number: 7077901Abstract: A process for producing a single crystal silicon wafer, comprising the steps of forming a porous layer on a single crystal silicon substrate comprising a silicon whose concentration of mass number 28 silicon isotope is less than 92.5% on an average; dissolving a starting silicon whose concentration of mass number 28 silicone isotope whose mass number is more than 98% on an average in a melt for liquid-phase epitaxy until said starting silicon becomes to be a supersaturated state in said melt under reductive atmosphere maintained at high temperature: immersing said single crystal silicon substrate in said melt to grow a single crystal silicon layer on the surface of said porous layer of said single crystal silicon substrate; and peeling said single crystal silicon layer from a portion of said porous layer.Type: GrantFiled: March 31, 2003Date of Patent: July 18, 2006Assignee: Canon Kabushiki KaishaInventors: Katsumi Nakagawa, Takao Yonehara, Kazuaki Ohmi, Shoji Nishida
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Patent number: 6869479Abstract: The present invention provides a method for fabrication of integrated optical structures and micro-lenses on different substrates based on new process of laser-assisted deposition of optical materials on various crystalline or amorphous solid-state materials. The deposition of target material takes place as a result of interaction of the laser beam with the substrate surface being in direct contact with a liquid containing precursor of appropriate target material. In one preferred embodiment, the micro-lens is fabricated directly on optical fibers or light emitting devices providing improved light collimation as required for efficient laser-to-fiber pig tailing. In another preferred embodiment, the micro-lenses are fabricated on each active element of a laser diode array.Type: GrantFiled: March 29, 2002Date of Patent: March 22, 2005Assignee: Altair Center, LLCInventors: George A. Shafeev, Sergei G. Krivoshlykov
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Publication number: 20030199153Abstract: Disclosed is a method of producing elementary semiconductor devices such as a field-effect transistor, a capacitor, a resistor, an inductor, a transformer, or a diode, and devices produced by said method. According to the method, a semiconductor seed layer is applied to a substrate having regions of exposed semiconductor material and regions of exposed dielectric material. The method comprises a step of disposing the substrate in a growth chamber and nucleating the seed layer by exposing the semiconductor material and dielectric material to an atmosphere of gases presented at a predetermined flow rate, temperature and pressure selected to provide contiguous growth of the seed layer, the seed layer growing in a single crystal lattice over predetermined windows within the mixed topology substrate.Type: ApplicationFiled: December 23, 2002Publication date: October 23, 2003Inventors: Stephen J. Kovacic, John N.M. Peirce, John William Mitchell Rogers, Nader Fayyaz, David Rahn
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Patent number: 6620710Abstract: A method of forming a single crystal semiconductor film on a non-crystalline surface is described. In accordance with this method, a template layer incorporating an ordered array of nucleation sites is deposited on the non-crystalline surface, and the single crystal semiconductor film is formed on the non-crystalline surface from the ordered array of nucleation sites. An integrated circuit incorporating one or more single crystal semiconductor layers formed by this method also is described.Type: GrantFiled: September 18, 2000Date of Patent: September 16, 2003Assignee: Hewlett-Packard Development Company, L.P.Inventor: Theodore I. Kamins
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Patent number: 6440212Abstract: A process of making thermoelectric coolers by direct printing of n- and p-type semiconductor materials suitable for making thermoelectric coolers is disclosed. Micro Jet Printing of arrays on n and p-type materials belong to conductive site pads on non-conductive substrate and crystalization of these materials in the preferred direction as they cool produces thermoelectric cooler components without the need for sawing and machining operations. A non-conductive top substrate having conductive bonding pads is secured to the tops of the columns n and p-type semiconductor materials thereby forming an electrical and physical bond to make a thermoelectric cooler package.Type: GrantFiled: February 27, 2001Date of Patent: August 27, 2002Assignee: MicroFab Technologies, Inc.Inventor: Donald J. Hayes
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Patent number: 6402836Abstract: The invention concerns a method for epitaxial growth of a material on a first solid material from a material melting on the material, characterized in that it comprises: a step of growth of the first material on the substrate, made of a second material; a step whereby crystalline tips of the first material are made to grow from the contact surface between the first material and the melting material; a step which consists in causing crystals to grow laterally from the crystalline tips in a plane parallel to that of the free surface of the melting material.Type: GrantFiled: October 25, 2000Date of Patent: June 11, 2002Assignee: CNRS (Centre National de la Recherche Scientifique)Inventor: André Leycuras
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Patent number: 6106613Abstract: In a semiconductor substrate comprising a silicon substrate having a porous region, and a semiconductor layer provided on the porous region, the semiconductor layer comprises a single-crystal compound and is formed on the surface of the porous region with its pores having been sealed at the surface. This substrate can be produced by a process comprising the steps of heat-treating the silicon substrate 11 having a porous region, to seal pores at the surface of the porous region 13, and forming a single-crystal compound-semiconductor layer 14 by heteroepitaxial growth on the porous region having the pores sealed by the heat treatment.Single-crystal compound semiconductor films with less crystal defects can be formed on large-area silicon substrates in a high productivity, a high uniformity, a high controllability and a great economical advantage.Type: GrantFiled: March 12, 1998Date of Patent: August 22, 2000Assignee: Canon Kabushiki KaishaInventors: Nobuhiko Sato, Takao Yonehara
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Patent number: 6103072Abstract: A piezoelectric thin-film device includes: a substrate; and a piezoelectric thin film formed on the substrate, wherein a thickness of the piezoelectric thin film is 1 to 10 .mu.m, a crystal grain size of the piezoelectric thin film is 0.05 to 1 .mu.m, and a surface roughness (Rmax) of the piezoelectric thin film is no more than 1 .mu.m.Type: GrantFiled: February 24, 1998Date of Patent: August 15, 2000Assignee: Seiko Epson CorporationInventors: Tsutomu Nishiwaki, Kouji Sumi, Masami Murai, Masato Shimada
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Patent number: 5683506Abstract: A method of manufacturing a bismuth-substituted rare-earth iron garnet single crystal film used for short wavelengths, includes the steps of: manufacturing a BIG-grown substrate in an LPE furnace by the LPE method, the BIG-grown substrate having a bismuth-substituted rare-earth iron garnet single crystal film grown on one surface of a non-magnetic garnet single crystal substrate, the film having a thickness in the range of 20-100 .mu.m; spinning the BIG-grown substrate at a high speed to remove a melt adhering thereto prior to taking the BIG-grown substrate out of the LPE furnace; and cooling the BIG-grown substrate to 300.degree. C. within one minute.Type: GrantFiled: June 17, 1996Date of Patent: November 4, 1997Assignee: Mitsubishi Gas Chemical Company, Inc.Inventors: Kazushi Shirai, Norio Takeda
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Patent number: 5654229Abstract: A method for providing an nonlinear, frequency converting optical QPM waveguide device by growing a first ferroelectric oxide film or layer on a second ferroelectric layer or medium wherein, in first and second embodiments, respectively, the second layer is initially provided with a periodic nonlinear coefficient pattern or a periodic pattern comprising a seed layer. During the growth of the first layer, the periodic pattern formed in the second layer, is replicated, transformed or induced into the first layer resulting in a plurality of substantially rectangular prismatic-shaped domains in the first layer having the periodic nonlinear coefficient pattern status based upon the periodic patterning of the second layer.Type: GrantFiled: April 26, 1995Date of Patent: August 5, 1997Assignee: Xerox CorporationInventors: Florence E. Leplingard, John J. Kingston, Ross D. Bringans, David K. Fork, Robert G. Waarts, David F. Welch, Randall S. Geels
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Patent number: 5639299Abstract: The disclosed method of making a compound semiconductor single-crystalline substrate for liquid phase epitaxial growth has a relatively low cost and excellent practicality. The compound semiconductor single-crystalline substrate is prepared to have a surface roughness of at least 1 .mu.m and not more than 10 .mu.m as measured over a line of 1 mm length. This substrate is employed as a substrate for an epitaxial wafer for an infrared- or visible light-emitting diode. Due to its particular roughness, the substrate can be prevented from slipping or falling while it is transported during processing. Furthermore, no lapping and polishing are required for manufacturing the substrate. Thus, the substrate for liquid phase epitaxial growth can be provided at a relatively low cost.Type: GrantFiled: May 26, 1995Date of Patent: June 17, 1997Assignee: Sumitomo Electric Industries, Ltd.Inventors: Tetsuya Inoue, Makoto Otsuki, Tetsuichi Yokota
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Patent number: 5603762Abstract: A process is disclosed for producing a film of an oxide type single crystal on a substrate of such an oxide type single crystal by epitaxially growing the oxide type single crystal on the substrate through contacting the substrate onto a melt in an overcooled state. The substrate of the oxide type single crystal is contacted with the melt held in a first furnace, and the substrate of the oxide type single crystal is held inside a second furnace separated from said first furnace, and the temperature of the substrate is adjusted in the second furnace. An oxide type single crystal film-producing apparatus is also disclosed.Type: GrantFiled: May 16, 1995Date of Patent: February 18, 1997Assignee: NGK Insulators, Ltd.Inventors: Nobuyuki Kokune, Kazuaki Yamaguchi, Shoji Sogo, Ryuichi Ohuchi, Tatsuo Kawaguchi, Minoru Imaeda
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Patent number: 5587015Abstract: An apparatus for production of single crystal oxide films by liquid-phase epitaxy comprises an insulating core tube with an external high frequency heating means, an electroconductive cylindrical member having openings at both ends and being arranged in the core tube, and a crucible made of an electroconductive material and coaxially arranged in the cylindrical member.Type: GrantFiled: April 6, 1995Date of Patent: December 24, 1996Assignee: Murata Manufacturing Co., Ltd.Inventors: Masaru Fujino, Hiroshi Takagi
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Patent number: 5571321Abstract: This disclosure herein pertains to a method for producing a GaP epitaxial wafer used for fabrication of light emitting diodes having higher brightness than light emitting diodes fabricated from a GaP epitaxial wafer produced by a conventional method have. The method comprises the steps of: preparing a GaP layered substrate 15 with one or more GaP layers on a GaP single crystal substrate 10 in the first series of liquid phase epitaxial growth; obtaining a layered GaP substrate 15a by eliminating surface irregularities of said GaP layered substrate 15 by mechano-chemical polishing to make the surface to be planar; and then forming a GaP light emitting layer composite 19 on said layered GaP substrate 15a in the second series of liquid phase epitaxial growth.Type: GrantFiled: October 20, 1994Date of Patent: November 5, 1996Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Munehisa Yanagisawa, Yuuki Tamura, Susumu Arisaka, Hidetoshi Matsumoto
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Patent number: 5500390Abstract: A method for controlling the Si concentration in a GaP single crystal layer grown in a series of runs of GaP liquid phase epitaxial growth with the repeated use of one and the same Ga solution, which comprise the steps of: measuring the Si concentrations of the GaP single crystal layers in preceding runs; then determining the additional Si amounts to be added into the Ga solution to refresh the Si effective concentration therein in reference to the Si concentrations in the layers; and adding Si of the thus determined amount into the Ga solution to commence the subsequent run, wherein the Si concentration in each of the GaP liquid phase epitaxial growth layers is determined from measurement of the O/G ratio in the layer, which is computed from each pair of the both values of the photoluminescent spectral peak intensity around the wavelength of 6300 .ANG. (O component) as the numerator and the other photoluminescent spectral peak intensity around the wavelength of 5540 .ANG.Type: GrantFiled: June 1, 1995Date of Patent: March 19, 1996Assignee: Shin-Etsu Handatoi Co., Ltd.Inventors: Munehisa Yanagisawa, Yuki Tamura, Norihide Kokubu
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Patent number: 5356509Abstract: A method for growing a compound semiconductor, such as GaAs or InP, on a non-lattice matched substrate, such as Si, utilizes close-spaced vapor transport to deposit nucleation enhancing interlayer and liquid phase epitaxy to form the compound semiconductor. When used in conjunction with a growth mask, the method is also adapted to selective area epitaxy.Type: GrantFiled: October 16, 1992Date of Patent: October 18, 1994Assignee: AstroPower, Inc.Inventors: Nancy Terranova, Allen M. Barnett
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Patent number: 5310446Abstract: A method for producing a semiconductor film comprising steps of: preparing a first substrate and a second substrate; superposing the first substrate on the second substrate to form an assembly of combined substrates; applying energy to the assembly of combined substrates to melt a portion within the assembly to form a molten portion therein; cooling the molten portion to crystallize the portion to form a single crystal structure therein; and separating the first substrate from the second substrate. The method makes it possible to control the crystal axis orientation of the recrystallized single crystal structure.Type: GrantFiled: July 13, 1992Date of Patent: May 10, 1994Assignee: Ricoh Company, Ltd.Inventors: Junichi Konishi, Kouichi Maari, Toshihiko Taneda, Akiko Kishimoto