Using An Energy Beam Or Field, A Particle Beam Or Field, Or A Plasma (e.g., Ionization, Pecvd, Cbe, Mombe, Rf Induction, Laser) Patents (Class 117/92)
  • Patent number: 11965799
    Abstract: An electromagnetic signal detector includes a photonic crystal substrate, an antenna disposed on the substrate and having an active feed region and a ground region spaced apart from one another by a gap, a photonic crystal disposed on the substrate at the gap, and an electro optic polymer disposed on the photonic crystal.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: April 23, 2024
    Assignee: United States of America as represented by the Administrator of NASA
    Inventors: Eleanya Onuma, Manohar Deshpande, Mark Stephen, Fabrizio Gambini, Charles Turner
  • Patent number: 11725301
    Abstract: The method for manufacturing a crystal for a synthetic gem includes the step of preparing a SiC single crystal including an n-type impurity, and the step of irradiating the SiC single crystal with an electron beam to generate a carbon vacancy in the SiC single crystal. Irradiation energy and dose in electron beam irradiation are set such that the density of the carbon vacancy is higher than the density of the n-type impurity.
    Type: Grant
    Filed: November 26, 2021
    Date of Patent: August 15, 2023
    Assignee: BRILLAR CO., LTD.
    Inventors: Iso Ohara, Tsunenobu Kimoto
  • Patent number: 11319630
    Abstract: [Object] To make it difficult for components other than films to be contained in a lamination interface. [Solving Means] In a deposition apparatus, a vacuum chamber includes a partition wall which defines a plasma formation space and includes quartz. An deposition preventive plate is provided between at least a part of the partition wall and the plasma formation space and includes at least one of yttria, silicon nitride, or silicon carbide. On a support stage, a substrate including a trench or hole including a bottom portion and a side wall is capable of being disposed. A plasma generation source generates first plasma of deposition gas including silicon introduced into the plasma formation space to thereby form a semiconductor film including silicon on the bottom portion and the side wall. The plasma generation source generates second plasma of etching gas including halogen introduced into the plasma formation space to thereby selectively remove the semiconductor film formed on the side wall.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: May 3, 2022
    Assignee: ULVAC, INC.
    Inventor: Kazuhiko Tonari
  • Patent number: 11306389
    Abstract: The invention is directed to an ion plasma deposition (IPD) method adapted to coat polymer surfaces with highly adherent antimicrobial films. A controlled ion plasma deposition (IPD) process is used to coat a metal or polymer with a selected metal/metal oxide. Exposing the coated surface to ultraviolet light significantly improves the antimicrobial properties of the deposited coatings.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: April 19, 2022
    Assignee: METASCAPE LLC
    Inventors: Terrence S. Mcgrath, Deidre Sewell, Daniel M. Storey
  • Patent number: 11164737
    Abstract: Implementations of the present disclosure generally relates to a transfer chamber coupled to at least one vapor phase epitaxy chamber a plasma oxide removal chamber coupled to the transfer chamber, the plasma oxide removal chamber comprising a lid assembly with a mixing chamber and a gas distributor; a first gas inlet formed through a portion of the lid assembly and in fluid communication with the mixing chamber; a second gas inlet formed through a portion of the lid assembly and in fluid communication with the mixing chamber; a third gas inlet formed through a portion of the lid assembly and in fluid communication with the mixing chamber; and a substrate support with a substrate supporting surface; a lift member disposed in a recess of the substrate supporting surface and coupled through the substrate support to a lift actuator; and a load lock chamber coupled to the transfer chamber.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: November 2, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Lara Hawrylchak, Schubert S. Chu, Tushar Mandrekar, Errol C. Sanchez, Kin Pong Lo
  • Patent number: 11107690
    Abstract: A method of forming a semiconductor device includes forming source/drain regions on opposing sides of a gate structure, where the gate structure is over a fin and surrounded by a first dielectric layer; forming openings in the first dielectric layer to expose the source/drain regions; selectively forming silicide regions in the openings on the source/drain regions using a plasma-enhanced chemical vapor deposition (PECVD) process; and filling the openings with an electrically conductive material.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: August 31, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Hsiu Hung, Chien Chang, Yi-Hsiang Chao, Hung-Yi Huang, Chih-Wei Chang
  • Patent number: 10852240
    Abstract: A facet region detecting method for detecting a facet region of an SiC single crystal ingot includes: an irradiation step of irradiating a first surface of the SiC single crystal ingot with light; a fluorescence intensity detection step of detecting the intensity of fluorescence generated from the first surface of the SiC single crystal ingot by the light; and a determination step of determining a region of the first surface where the fluorescence intensity is comparatively low as a facet region and determining a region where the fluorescence intensity is comparatively high as a non-facet region.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: December 1, 2020
    Assignee: DISCO CORPORATION
    Inventors: Naoki Murazawa, Kunimitsu Takahashi
  • Patent number: 10454181
    Abstract: Techniques are described for a lens containing high dielectric resonators. In one example, a lens comprises a substrate for propagating an electromagnetic wave and a plurality of resonators dispersed throughout the substrate. Each of the plurality of resonators has a diameter selected based at least in part on a wavelength of the electromagnetic wave and is formed of a dielectric material having a resonance frequency selected based at least in part on a frequency of the electromagnetic wave. Each of the plurality of resonators also has a relative permittivity that is greater than a relative permittivity of the substrate. At least two of the plurality of resonators are spaced within the substrate according to a lattice constant that defines a distance between a center of a first one of the resonators and a center of a neighboring second one of the resonators.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: October 22, 2019
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: Jaewon Kim, Douglas B. Gundel, Ronald D. Jesme, Justin M. Johnson
  • Patent number: 10351949
    Abstract: A vapor phase growth method according to an embodiment is a vapor phase growth method of forming on a single substrate a film having a composition different from a composition of the substrate. The method includes, rotating the single substrate with a center of the single substrate being a rotation center, heating a single substrate to a first temperature, and forming a silicon carbide film having a film thickness of 10 nm or more and 200 nm or less on a surface of the single substrate by supplying a first process gas containing silicon and carbon as a laminar flow in a direction substantially perpendicular to the surface of the single substrate.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: July 16, 2019
    Assignee: NuFlare Technology, Inc.
    Inventors: Hideshi Takahashi, Kiyotaka Miyano, Masayuki Tsukui, Hajime Nago, Yasushi Iyechika
  • Patent number: 10170482
    Abstract: A method for preventing epitaxial growth in a semiconductor device is described. The method includes cutting the fins of FinFET structure to form a set of exposed fin ends. A set of sidewall spacers are formed on the set of exposed fin ends, forming a set of spacer covered fin ends. The set of sidewall spacers prevent epitaxial growth at the set of spacer covered fin ends. A semiconductor device includes a set of fin structures having a set of fin ends. A set of inhibitory layers are disposed at the set of fin ends to inhibit excessive epitaxial growth at the fin ends.
    Type: Grant
    Filed: February 27, 2016
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Balasubramanian Pranatharthiharan, Hui Zang
  • Patent number: 9960047
    Abstract: A test pattern for testing a trench POLY over-etched step is provided. The test pattern is a trench (14) formed on a substrate (1); the trench (14) comprises a bottom surface and two side surfaces extending from the bottom surface; the trench (14) is formed on the substrate (1) with a preset angle of non-90° formed between the longitudinal direction (L) thereof and the longitudinal direction (X) of a wafer scribing trench. The test pattern can extend the scanning length of a step scanning equipment without changing the width of the trench.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: May 1, 2018
    Assignees: CSMC Technologies Fab1 Co., Ltd., CSMC Technologies Fab2 Co., Ltd.
    Inventor: Zheng Bian
  • Patent number: 9870921
    Abstract: Implementations of the present disclosure generally relate to methods and apparatuses for epitaxial deposition on substrate surfaces. More particularly, implementations of the present disclosure generally relate to methods and apparatuses for surface preparation prior to epitaxial deposition. In one implementation, a method of processing a substrate is provided. The method comprises etching a surface of a silicon-containing substrate by use of a plasma etch process, where at least one etching process gas comprising chlorine gas and an inert gas is used during the plasma etch process and forming an epitaxial layer on the surface of the silicon-containing substrate.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: January 16, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Christopher S. Olsen, Peter Stone, Teng-fang Kuo, Ping Han Hsieh, Manoj Vellaikal
  • Patent number: 9786559
    Abstract: Techniques are disclosed for forming through-silicon vias (TSVs) implementing a negative thermal expansion (NTE) material such as zirconium tungstate (ZrW2O8) or hafnium tungstate (HfW2O8). In some cases, the NTE material is disposed between the substrate and conductive core material of the TSV and serves to offset, at least in part, the coefficient of thermal expansion (CTE) mismatch there between, thus reducing heat-induced stresses and/or protrusion (pumping) of the conductive core material. The NTE material also may protect against leakage, voltage breakdown, and/or diffusion of the conductive core material. Furthermore, the NTE material may reduce radial stresses in high-aspect-ratio TSVs. In some cases, techniques disclosed herein may improve TSV reliability, enhance three-dimensional integration, and/or enhance performance in three-dimensional integrated circuits and/or other three-dimensional packages.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: October 10, 2017
    Assignee: INTEL CORPORATION
    Inventors: Paul A. Zimmerman, Scott B. Clendenning, Patricio E. Romero, Paul B. Fischer, Robert Edgeworth
  • Patent number: 9684094
    Abstract: A photonic crystal supporting highly frequency-sensitive self-collimation phenomenon, which is formed by at least two kinds of materials, and has a periodic distribution of refractive index, the photonic crystal has straight equi-frequency contours or flat equi-frequency surfaces in a certain band in the first Brillouin zone of wave-vector space, and the frequency-sensitivity of self-collimation is at least 50 times higher than the change rate of curvatures of the equi-frequency contours or the equi-frequency surfaces with frequencies in a vacuum.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: June 20, 2017
    Assignees: SHANGHAI INSITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY OF SCIENCES, FUDAN UNIVERSITY
    Inventors: Xunya Jiang, Xulin Lin, Xiaogang Zhang, Wei Li, Liang Chen
  • Patent number: 9034104
    Abstract: A larger substrate can be used, and a transistor having a desirably high field-effect mobility can be manufactured through formation of an oxide semiconductor layer having a high degree of crystallinity, whereby a large-sized display device, a high-performance semiconductor device, or the like can be put into practical use. A single-component oxide semiconductor layer is formed over a substrate; then, crystal growth is carried out from a surface to an inside by performing heat treatment at 500° C. to 1000° C. inclusive, preferably 550° C. to 750° C. inclusive so that a single-component oxide semiconductor layer including single crystal regions is formed; and a multi-component oxide semiconductor layer including single crystal regions is stacked over the single-component oxide semiconductor layer including single crystal regions.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: May 19, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takuya Hirohashi, Masahiro Takahashi, Takashi Shimazu
  • Patent number: 9023306
    Abstract: The invention relates to a single crystal boron doped CVD diamond that has a toughness of at least about 22 MPa m1/2. The invention further relates to a method of manufacturing single crystal boron doped CVD diamond. The growth rate of the diamond can be from about 20-100 ?m/h.
    Type: Grant
    Filed: May 5, 2009
    Date of Patent: May 5, 2015
    Assignee: Carnegie Institution of Washington
    Inventors: Russell J. Hemley, Ho-Kwang Mao, Chih-Shiue Yan, Qi Liang
  • Patent number: 9005363
    Abstract: Methods of depositing thin film materials having crystalline content are provided. The methods use plasma enhanced chemical vapor deposition. According to one embodiment of the present invention, microcrystalline silicon films are obtained. According to a second embodiment of the present invention, crystalline films of zinc oxide are obtained. According to a third embodiment of the present invention, crystalline films of iron oxide are obtained.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: April 14, 2015
    Assignee: Sencera Energy, Inc.
    Inventors: Russell F Jewett, Steven F Pugh, Paul Wickboldt
  • Patent number: 8986645
    Abstract: A method of producing a CVD single crystal diamond layer on a substrate includes adding into a DVD synthesis atmosphere a gaseous source comprising silicon. The method can be used to mark the diamond material, for instance to provide means by which its synthetic nature can more easily be determined. It can also be exploited to generate single crystal diamond material of high color.
    Type: Grant
    Filed: July 6, 2006
    Date of Patent: March 24, 2015
    Assignee: Element Six Limited
    Inventors: Daniel James Twitchen, Geoffrey Alan Scarsbrook, Philip Maurice Martineau, Paul Martyn Spear, Stephen David Williams, Ian Friel
  • Publication number: 20150068581
    Abstract: A fabrication method for high-efficiency multi junction solar cells, including: providing a Ge substrate for semiconductor epitaxial growth; growing an emitter region over the Ge substrate (as the base) to form a first subcell with a first band gap; forming a second subcell with a second band gap larger than the first band gap and lattice matched with the first subcell over the first subcell via MBE; forming a third subcell with a third band gap larger than the second band gap and lattice matched with the first and second subcells over the second subcell via MOCVD; and forming a fourth subcell with a fourth band gap larger than the third band gap and lattice matched with the first, second and third subcells over the third subcell via MOCVD.
    Type: Application
    Filed: November 13, 2014
    Publication date: March 12, 2015
    Applicant: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: JINGFENG BI, GUIJIANG LIN, JIANQING LIU, JIE DING
  • Patent number: 8961687
    Abstract: Disclosed embodiments include methods of fabricating a semiconductor layer or device and devices fabricated thereby. The methods include, but are not limited to, providing a substrate having a cubic crystalline surface with a known lattice parameter and growing a cubic crystalline group III-nitride alloy layer on the cubic crystalline substrate by coincident site lattice matched epitaxy. The cubic crystalline group III-nitride alloy may be prepared to have a lattice parameter (a?) that is related to the lattice parameter of the substrate (a). The group III-nitride alloy may be a cubic crystalline InxGayAl1-x-yN alloy. The lattice parameter of the InxGayAl1-x-yN or other group III-nitride alloy may be related to the substrate lattice parameter by (a?)=?2(a) or (a?)=(a)/?2. The semiconductor alloy may be prepared to have a selected band gap.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: February 24, 2015
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: Andrew G. Norman, Aaron J. Ptak, William E. McMahon
  • Patent number: 8945302
    Abstract: Method for crystal growth from a surfactant of a metal-nonmetal (MN) compound, including the procedures of providing a seed crystal, introducing atoms of a first metal to the seed crystal thus forming a thin liquid metal wetting layer on a surface of the seed crystal, setting a temperature of the seed crystal below a minimal temperature required for dissolving MN molecules in the wetting layer and above a melting point of the first metal, each one of the MN molecules being formed from an atom of a second metal and an atom of a first nonmetal, introducing the MN molecules which form an MN surfactant monolayer, thereby facilitating a formation of the wetting layer between the MN surfactant monolayer and the surface of the seed crystal, and regulating a thickness of the wetting layer, thereby growing an epitaxial layer of the MN compound on the seed crystal.
    Type: Grant
    Filed: March 4, 2012
    Date of Patent: February 3, 2015
    Assignee: Mosaic Crystals Ltd.
    Inventor: Moshe Einav
  • Patent number: 8945304
    Abstract: A system and method A method of growing an elongate nanoelement from a growth surface includes: a) cleaning a growth surface on a base element; b) providing an ultrahigh vacuum reaction environment over the cleaned growth surface; c) generating a reactive gas of an atomic material to be used in forming the nanoelement; d) projecting a stream of the reactive gas at the growth surface within the reactive environment while maintaining a vacuum of at most 1×10?4 Pascal; e) growing the elongate nanoelement from the growth surface within the environment while maintaining the pressure of step c); f) after a desired length of nanoelement is attained within the environment, stopping direction of reactive gas into the environment; and g) returning the environment to an ultrahigh vacuum condition.
    Type: Grant
    Filed: August 13, 2008
    Date of Patent: February 3, 2015
    Assignee: The Board of Regents of the Nevada System of Higher Education on behalf of the University of Nevada, Las Vegas University of Nevada
    Inventors: Biswajit Das, Myung B. Lee
  • Patent number: 8936681
    Abstract: A method for making an epitaxial structure is provided. The method includes the following steps. A substrate is provided. The substrate has an epitaxial growth surface for growing epitaxial layer. A carbon nanotube layer is placed on the epitaxial growth surface. An epitaxial layer is epitaxially grown on the epitaxial growth surface. The carbon nanotube layer is removed. The carbon nanotube layer can be removed by heating.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: January 20, 2015
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Yang Wei, Shou-Shan Fan
  • Patent number: 8876973
    Abstract: There is provided an n type (100) oriented single crystal diamond semiconductor film into which phosphorous atoms have been doped and a method of producing the same. The n type (100) oriented single crystal diamond semiconductor film, characterized in that (100) oriented diamond is epitaxially grown on a substrate under such conditions that; the diamond substrate is (100) oriented diamond, a means for chemical vapor deposition provides hydrogen, hydrocarbon and a phosphorous compound in the plasma vapor phase, the ratio of phosphorous atoms to carbon atoms in the plasma vapor phase is no less than 0.1%, and the ratio of carbon atoms to hydrogen atoms is no less than 0.05%, and the method of producing the same.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: November 4, 2014
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Hiromitsu Kato, Satoshi Yamasaki, Hideyo Ookushi, Shinichi Shikata
  • Patent number: 8853078
    Abstract: Material is deposited in a desired pattern by spontaneous deposition of precursor gas at regions of a surface that are prepared using a beam to provide conditions to support the initiation of the spontaneous reaction. Once the reaction is initiated, it continues in the absence of the beam at the regions of the surface at which the reaction was initiated.
    Type: Grant
    Filed: January 30, 2011
    Date of Patent: October 7, 2014
    Assignee: FEI Company
    Inventors: Aurelien Philippe Jean Maclou Botman, Steven Randolph, Milos Toth
  • Patent number: 8821635
    Abstract: Si—Ge materials are grown on Si(100) with Ge-rich contents (Ge>50 at. %) and precise stoichiometries SiGe, SiGe2, SiGe3 and SiGe4. New hydrides with direct Si—Ge bonds derived from the family of compounds (H3Ge)xSiH4-x (x=1-4) are used to grow uniform, relaxed, and highly planar films with low defect densities at unprecedented low temperatures between about 300-450° C. At about 500-700° C., SiGex quantum dots are grown with narrow size distribution, defect-free microstructures and highly homogeneous elemental content at the atomic level. The method provides for precise control of morphology, composition, structure and strain. The grown materials possess the required characteristics for high frequency electronic and optical applications, and for templates and buffer layers for high mobility Si and Ge channel devices.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: September 2, 2014
    Assignee: Arizona Board of Regents on Behalf of Arizona State University
    Inventors: John Kouvetakis, Ignatius S. T. Tsong, Changwu Hu, John Tolle
  • Patent number: 8790461
    Abstract: The invention provides a method for manufacturing the silicon carbide single crystal wafer capable of improving the utilization ratio of the bulk silicon carbide single crystal, capable of improving characteristics of the element and capable of improving cleavability, and the silicon carbide single crystal wafer obtained by the manufacturing method. An ?(hexagonal)-silicon carbide single crystal wafer which has a flat homoepitaxial growth surface with a surface roughness of 2 nm or less and which has an off-angle from the (0001)c plane of 0.4° or less.
    Type: Grant
    Filed: August 24, 2005
    Date of Patent: July 29, 2014
    Assignee: Showa Denko K.K.
    Inventors: Takayuki Maruyama, Toshimi Chiba
  • Patent number: 8728586
    Abstract: In large area plasma processing systems, process gases may be introduced to the chamber via the showerhead assembly which may be driven as an RF electrode. The gas feed tube, which is grounded, is electrically isolated from the showerhead. The gas feed tube may provide not only process gases, but also cleaning gases from a remote plasma source to the process chamber. The inside of the gas feed tube may remain at either a low RF field or a zero RF field to avoid premature gas breakdown within the gas feed tube that may lead to parasitic plasma formation between the gas source and the showerhead. By feeding the gas through an RF choke, the RF field and the processing gas may be introduced to the processing chamber through a common location and thus simplify the chamber design.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: May 20, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Jozef Kudela, Carl A. Sorensen, John M. White
  • Publication number: 20140116327
    Abstract: The method for fabricating a free-standing group III nitride plate (6) comprises the steps of growing at a growth temperature within a growth reactor (7) a first group III nitride layer (2) on a foreign growth substrate (1); growing at the growth temperature within the growth reactor (7) a second group III nitride layer (5) on the first group III nitride layer (2); and separating by laser lift-off the second group III nitride layer (5) from the growth substrate (1) so as to form a free-standing group III nitride plate (6). According to the present invention, the step of separating the second group III nitride layer (5) from the growth substrate (6) is performed at the growth temperature and within the growth reactor (7), and the method further comprises a step of treating the first group III nitride layer (1) by laser treatment at the growth temperature within the growth reactor (7) so as to provide stress relaxation areas (4) in the first group III nitride layer (2).
    Type: Application
    Filed: May 31, 2012
    Publication date: May 1, 2014
    Applicant: "PERFECT CRYSTALS" LIMITED LIABILITY COMPANY
    Inventor: Maxim Blashenkov
  • Patent number: 8580034
    Abstract: A method of forming a semiconductor device includes providing a substrate in a vacuum processing tool, the substrate having a strained Ge-containing layer on the substrate and a Si layer on the strained Ge-containing layer, maintaining the substrate at a temperature less than 700° C., and generating a soft plasma in the vacuum processing tool. The Si layer is exposed to the soft plasma to form a Si-containing dielectric layer while minimizing oxidation and strain relaxation in the underlying strained Ge-containing layer. A semiconductor device containing a substrate, a strained Ge-containing layer on the substrate, and an Si-containing dielectric layer formed on the strained Ge-containing layer is provided. The semiconductor device can further contain a gate electrode layer on the Si-containing dielectric layer or a high-k layer on the Si-containing dielectric layer and a gate electrode layer on the high-k layer.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: November 12, 2013
    Assignee: Tokyo Electron Limited
    Inventor: Gert Leusink
  • Patent number: 8557041
    Abstract: A method for manufacturing a P-I-N microcrystalline silicon structure for thin-film solar cells, includes the steps of: (a) forming a P-type layer; (b) forming an I-type layer including a plurality of sub-layers successively stacked on the P-type layer using gas mixtures including fluoride and hydride that have different gas ratios, respectively; and (c) forming an N-type layer on the I-type layer. First, second, and third I-type sub-layers may be formed on the P-type layer using gas mixtures including fluoride and hydride at a first, second, and third gas ratios, respectively. Then, advantageously, the third gas ratio may be larger than the second gas ratio and the second gas ratio may be larger than the first gas ratio, and the first gas ratio may be 8%, the second gas ratio may range between 15% and 35%, and the third gas ratio may range between 35% and 50%.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: October 15, 2013
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Hung Chen, Jun-Chin Liu, Chun-Heng Chen
  • Patent number: 8551246
    Abstract: A method for manufacturing a silicon single crystal wafer, having at least: a step of preparing a silicon single crystal ingot; a step of slicing the silicon single crystal ingot to fabricate a plurality of sliced substrates; a processing step of processing the plurality of sliced substrates into a plurality of substrates by performing at least one of lapping, etching, and polishing; a step of sampling at least one from the plurality of substrates; a step of measuring surface roughness of the substrate sampled at the sampling step by an AFM and obtaining an amplitude (an intensity) of a frequency band corresponding to a wavelength of 20 nm to 50 nm to make a judgment of acceptance; and a step of sending the substrate to the next step if a judgment result is acceptance or performing reprocessing if the judgment result is rejection.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: October 8, 2013
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Fumio Tahara, Tsuyoshi Ohtsuki, Takatoshi Nagoya, Kiyoshi Mitani
  • Patent number: 8540817
    Abstract: There are provided a method for manufacturing a Si(1-v-w-x)CwAlxNv substrate having a reduced number of cracks and high processability, a method for manufacturing an epitaxial wafer, a Si(1-v-w-x)CwAlxNv substrate, and an epitaxial wafer. A method for manufacturing a Si(1-v-w-x)CwAlxNv substrate 10a includes the following steps. First, a Si substrate 11 is prepared. A Si(1-v-w-x)CwAlxNv layer (0<v<1, 0<w<1, 0<x<1, and 0<v+w+x<1) is then grown on the Si substrate at a temperature below 550° C.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: September 24, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Issei Satoh, Michimasa Miyanaga, Shinsuke Fujiwara, Hideaki Nakahata
  • Patent number: 8394197
    Abstract: Enhanced corrosion resistance is achieved in a coating by using a germanium-containing precursor and hollow cathode techniques to form a first layer directly on the surface of a workpiece, prior to forming an outer layer, such as a layer of diamond-like carbon (DLC). The use of a germanium or germanium-carbide precursor reduces film stress and enables an increase in the thickness of the subsequently formed DLC. Germanium incorporation also reduces the porosity of the layer. In one embodiment, a cap layer containing germanium is added after the DLC in order to further reduce the susceptibility of the coating to chemical penetration from the top.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: March 12, 2013
    Assignee: Sub-One Technology, Inc.
    Inventors: Andrew W. Tudhope, Thomas B. Casserly, Karthik Boinapally, Deepak Upadhyaya, William J. Boardman
  • Patent number: 8395164
    Abstract: Silicon carbide substrate wafers are prepared by transferring a monocrystalline silicon layer from a donor wafer onto a handle wafer, the silicon layer being implanted with carbon and annealed to form a monocrystalline SiC layer prior to or after transfer of the silicon layer.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: March 12, 2013
    Assignee: Siltronic AG
    Inventors: Brian Murphy, Reinhold Wahlich
  • Patent number: 8394196
    Abstract: Methods for formation epitaxial layers containing silicon and carbon doped with phosphorus are disclosed. The pressure is maintained equal to or above 100 torr during deposition. The methods result in the formation of a film including substitutional carbon. Specific embodiments pertain to the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: March 12, 2013
    Assignee: Applied Materials, Inc.
    Inventor: Yihwan Kim
  • Patent number: 8372197
    Abstract: A control system and method for controlling temperatures while performing a MBE deposition process, wherein the control system comprises a MBE growth structure; a heater adapted to provide heat for the MBE deposition process on the MBE growth structure; and a control computer adapted to receive a plurality of dynamic feedback control signals derived from the MBE growth structure; switch among a plurality of control modes corresponding with the plurality of dynamic feedback control signals; and send an output power signal to the heater to control the heating for the MBE deposition process based on a combination of the plurality of control modes. In one embodiment, the plurality of dynamic feedback control signals comprises thermocouple signals and pyrometer signals.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: February 12, 2013
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventor: Stefan P. Svensson
  • Patent number: 8372196
    Abstract: In a manufacturing apparatus for manufacturing an epitaxial wafer with a wafer being mounted substantially concentrically with a susceptor, a center rod is provided to extend in an up-and-down direction on a side of a non-mounting surface of the susceptor so that its upper end is adjacent to the center of the susceptor. With this arrangement, part of radiation light irradiated toward the susceptor is diffusely reflected by the center rod before reaching the central portion of the susceptor, thereby reducing the amount of the radiation light irradiated to the central portion of the susceptor as well as lowering the temperature of the portion. Since the center rod and the susceptor are not in surface contact, the center rod does not take the heat from the susceptor, thereby suppressing the temperature from decreasing locally at the central portion of the susceptor.
    Type: Grant
    Filed: November 2, 2009
    Date of Patent: February 12, 2013
    Assignee: Sumco Techxiv Corporation
    Inventors: Motonori Nakamura, Yoshinobu Mori, Takeshi Masuda, Hidenori Kobayashi, Kazuhiro Narahara
  • Patent number: 8357242
    Abstract: Methods of depositing thin film materials having crystalline content are provided. The methods use plasma enhanced chemical vapor deposition. According to one embodiment of the present invention, microcrystalline silicon films are obtained. According to a second embodiment of the present invention, crystalline films of zinc oxide are obtained. According to a third embodiment of the present invention, crystalline films of iron oxide are obtained.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: January 22, 2013
    Inventors: Russell F. Jewett, Steven F. Pugh, Paul Wickboldt
  • Patent number: 8268076
    Abstract: SOI wafers are manufactured by forming on a silicon substrate a monocrystalline first, cubic 1a-3 metal or mixed metal oxide layer whose lattice constant differs from that of the substrate by 5% or less; forming a second cubic 1a-3 mixed metal oxide layer having a lattice constant within 2% of the lattice constant of the first metal or mixed metal oxide layer, and having a graded metal content to vary the lattice content in the second mixed metal oxide layer from that of the first layer, and thermally treating the layered product in an oxygen atmosphere to form an amorphous interlayer between the substrate and the first metal or mixed metal oxide layer.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: September 18, 2012
    Assignee: Siltronic AG
    Inventors: Thomas Schroeder, Peter Storck, Hans Joachim Muessig
  • Patent number: 8262796
    Abstract: A thin-film single crystal growing method includes preparing a substrate, irradiating an excitation beam on a metallic target made of a pure metal or an alloy in a predetermined atmosphere, and combining chemical species including any of atoms, molecules, and ions released from the metallic target by irradiation of the excitation beam with atoms contained in the predetermined atmosphere to form a thin film on the substrate.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: September 11, 2012
    Assignee: Waseda University
    Inventors: Noboru Ichinose, Kiyoshi Shimamura, Kazuo Aoki, Encarnacion Antonia Garcia Villora
  • Patent number: 8252112
    Abstract: A method and apparatus for the unusually high rate deposition of thin film materials on a stationary or continuous substrate. The method includes delivery of a pre-selected precursor intermediate to a deposition chamber and formation of a thin film material from the intermediate. The intermediate is formed outside of the deposition chamber and includes a metastable species such as a free radical. The intermediate is pre-selected to include a metastable species conducive to the formation of a thin film material having a low defect concentration. By forming a low defect concentration material, deposition rate is decoupled from material quality and heretofore unprecedented deposition rates are achieved. In one embodiment, the pre-selected precursor intermediate is SiH3.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: August 28, 2012
    Assignee: Ovshinsky Innovation, LLC
    Inventor: Stanford R. Ovshinsky
  • Patent number: 8226767
    Abstract: “Super-hetero-epitaxial” combinations comprise epitaxial growth of one material on a different material with different crystal structure. Compatible crystal structures may be identified using a “Tri-Unity” system. New bandgap engineering diagrams are provided for each class of combination, based on determination of hybrid lattice constants for the constituent materials in accordance with lattice-matching equations. Using known bandgap figures for previously tested materials, new materials with lattice constants that match desired substrates and have the desired bandgap properties may be formulated by reference to the diagrams and lattice matching equations. In one embodiment, this analysis makes it possible to formulate new super-hetero-epitaxial semiconductor systems, such as systems based on group IV alloys on c-plane LaF3; group IV alloys on c-plane langasite; Group III-V alloys on c-plane langasite; and group II-VI alloys on c-plane sapphire.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: July 24, 2012
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventors: Yeonjoon Park, Sang H. Choi, Glen C. King, James R. Elliott
  • Patent number: 8216368
    Abstract: A method of forming an epitaxially grown layer, preferably by providing a region of weakness in a support substrate and transferring a nucleation portion to the support substrate by bonding. A remainder portion of the support substrate is detached at the region of weakness and an epitaxial layer is grown on the nucleation portion. The remainder portion is separated or otherwise removed from the support portion.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: July 10, 2012
    Assignee: Soitec
    Inventors: Bruce Faure, Fabrice Letertre
  • Patent number: 8212254
    Abstract: By a laser crystallization method, a crystalline semiconductor film in which grain boundaries are all in one direction is provided as well as a manufacturing method thereof. In crystallizing a semiconductor film formed over a substrate with linear laser light, a phase-shift mask in which trenches are formed in a stripe form is used. The stripe-form trenches formed in the phase-shift mask are formed so as to make a nearly perpendicular angle with a major axis direction of the linear laser light. CW laser light is used as the laser light, and a scanning direction of the laser light is nearly parallel to a direction of the stripe-form trenches (grooves). By changing luminance of the laser light periodically in the major axis direction, a crystal nucleation position in a semiconductor that is completely melted can be controlled.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: July 3, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hidekazu Miyairi
  • Patent number: 8192543
    Abstract: A nitride crystal is characterized in that, in connection with plane spacing of arbitrary specific parallel crystal lattice planes of the nitride crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of the crystal while X-ray diffraction conditions of the specific parallel crystal lattice planes are satisfied, a uniform distortion at a surface layer of the crystal represented by a value of |d1?d2|/d2 obtained from the plane spacing d1 at the X-ray penetration depth of 0.3 ?m and the plane spacing d2 at the X-ray penetration depth of 5 ?m is equal to or lower than 2.1×10?3.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: June 5, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Tokiko Kaji, Seiji Nakahata, Takayuki Nishiura
  • Patent number: 8163444
    Abstract: A mask for crystallizing a semiconductor layer includes a plurality of first main-slit portions, a plurality of second main-slit portions, upper slit portion and lower slit portion. The first main-slit portions extend along an inclined direction with respect to a first direction. The second main-slit portions are spaced apart from the first main-slit portions. The upper slit portion is disposed on the first main-slit portions along a second direction to be parallel to the first main-slit portions, and extends partway over the second main-slit portions to be longer than the first main-slit portions. The lower slit portion is disposed under the second main-slit portions along the second direction to be parallel to the second main-slit portions, and extends partway under the first main-slit portions to be longer than the second main-slit portions.
    Type: Grant
    Filed: January 27, 2009
    Date of Patent: April 24, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Cheol-Ho Park
  • Patent number: 8137461
    Abstract: A piezoelectric substrate of a perovskite-type oxide is expressed by a general formula of ABO3 having a laminate structure of a single crystal structure or a uniaxial crystal structure expressed by (Pb1-xMx)xm(ZryTi1-y)O3 (where M represents an element selected from La, Ca, Ba, Sr, Bi, Sb and W). The laminate structure has a first crystal phase layer having a crystal structure selected from a tetragonal structure, a rhombohedral structure, a pseudocubic structure and a monoclinic structure, a second crystal phase layer having a crystal structure different from the crystal structure of said first crystal phase layer and a boundary layer arranged between the first crystal phase layer and the second crystal phase layer with a crystal structure gradually changing in a thickness direction of the layer. The thicknesses of the first and second crystal phase layer differ.
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: March 20, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takanori Matsuda, Toshihiro Ifuku
  • Patent number: 8101018
    Abstract: In a method for fabricating a semiconductor device and an apparatus for inspecting a semiconductor, laser processing is performed at different laser powers at different positions on a monitor substrate from a plurality of substrates having undergone an SPC step, to form polycrystalline silicon film over the entire area of the substrate. Thereafter, in an optimum power inspection/extraction step, the polycrystalline silicon film formed with varying film quality on the monitor substrate is inspected on inspection equipment to determine the optimum laser power. Then, in a laser processing step, the surface of the subsequent substrates having undergone the SPC step is irradiated with laser at the optimum laser power. Thus, high-quality polycrystalline silicon film is formed over the entire area of the substrate.
    Type: Grant
    Filed: March 2, 2005
    Date of Patent: January 24, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Yasunobu Tagusa
  • Patent number: 8080106
    Abstract: Provided are an epitaxial silicon wafer in which the warping is reduced by rendering a cross-sectional form of a silicon wafer for epitaxial growth into an adequate form as compared with the conventional one, and a production method thereof. An epitaxial silicon wafer comprising a silicon wafer for epitaxial growth and an epitaxial layer is characterized in that the epitaxial layer is formed on a silicon wafer for epitaxial growth having a cross-sectional form satisfying a relation of a given expression.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: December 20, 2011
    Assignee: Sumco Corporation
    Inventors: Takayuki Kihara, Kazushige Takaishi, Yasuyuki Hashimoto