Abstract: A plasma generation apparatus according to the present invention includes an electrode cell and a housing that encloses an electrode cell. The electrode cell includes a first electrode, a second electrode facing the first electrode with interposition of a discharge space therebetween, and dielectrics arranged on main surfaces of the electrodes. The plasma generation apparatus further includes a pipe passage configured to directly supply a source gas from the outside of the housing to the discharge space without being connected to a space within the housing where the electrode cell is not arranged.

Abstract: One embodiment can provide a system for curing conductive paste applied on photovoltaic structures using induction heating. The system can include a wafer carrier for carrying a plurality of photovoltaic structures and an induction heater. The wafer carrier can include a surface element that is in direct contact with the photovoltaic structures and is substantially thermally insulating. The induction heater can be positioned above the wafer carrier. The induction heater can include a heating coil and core that do not directly contact the photovoltaic structures.

Abstract: Methods and apparatuses for filling an epitaxial layer into a trench/via/structure formed in a substrate with good deposition profile control and film uniformity across the substrate are provided. In one embodiment, a method of depositing a epitaxial layer on the substrate includes supplying a gas mixture having a first ratio of a dichlorosilane gas to a chlorine containing gas into the processing chamber, altering the gas mixture to have a second ratio of the dichlorosilane gas to the chlorine containing gas into the processing chamber, maintaining a substrate temperature of between about 600 degrees Celsius and about 1000 degrees Celsius, and filling an opening formed in a substrate.

Abstract: Merged and unmerged raised active regions on semiconductor fins can be simultaneously formed on a same substrate by control of growth rates of a deposited semiconductor material on surfaces of the semiconductor fins. In one embodiment, a growth-rate-retarding dopant can be implanted by angled ion implantation onto sidewall surfaces of first semiconductor fins on which retardation of growth rates is desired, while second semiconductor fins are masked by a masking layer. In another embodiment, a growth-rate-enhancing dopant can be implanted by ion implantation onto sidewall surfaces of second semiconductor fins, while first semiconductor fins are masked by a masking layer. The differential growth rates of the deposited semiconductor material can cause raised active regions on the first semiconductor fins to remain unmerged, and raised active regions on the second semiconductor fins to become merged.

Abstract: A method of determining a temperature in a deposition reactor includes the steps of depositing a first epitaxial layer of silicon germanium on a substrate, depositing a second epitaxial layer of silicon above the first epitaxial layer, measuring the thickness of the second epitaxial layer and determining the temperature in the deposition reactor using the measured thickness of the second epitaxial layer. The method may also include heating the deposition reactor to approximately a predetermined temperature using a heating device and a temperature measuring device and generating a signal indicative of a temperature within the deposition reactor. The method may also contain the steps of comparing the measured thickness with a predetermined thickness of the second epitaxial layer corresponding to the predetermined temperature and determining the temperature in the deposition reactor using the measured thickness of the second epitaxial layer and the predetermined thickness of the second epitaxial layer.

Abstract: This disclosure enables high-productivity fabrication of semiconductor-based separation layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers), optical reflectors (made of multi-layer/multi-porosity porous semiconductors such as porous silicon), formation of porous semiconductor (such as porous silicon) for anti-reflection coatings, passivation layers, and multi-junction, multi-band-gap solar cells (for instance, by forming a variable band gap porous silicon emitter on a crystalline silicon thin film or wafer-based solar cell). Other applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation).

Abstract: A method for using a silicon film formation apparatus includes performing a pre-coating process to cover a reaction tube with a silicon coating film, an etching process to etch natural oxide films on product target objects, a silicon film formation process to form a silicon product film on the product target objects, and a cleaning process to etch silicon films on the reaction tube, in this order. The pre-coating process includes supplying a silicon source gas into the reaction tube from a first supply port having a lowermost opening at a first position below the process field, while exhausting gas upward from inside the reaction tube. The etching process includes supplying an etching gas into the reaction tube from a second supply port having a lowermost opening between the process field and the first position, while exhausting gas upward from inside the reaction tube by the exhaust system.

Abstract: The invention relates to a method for forming a thin film of molecular organic semiconductor material (OSCM), said film being intended to be integrated into a device for applications in electronics or optoelectronics, which includes the following steps: step (c) of supplying a defined quantity of the molecular OSCM in the form of a melt to the surface of a substrate so as to form a thin film; and a step (d) of cooling according to a defined temperature profile in order to solidify the thin film, characterized in that the temperature of the substrate surface is equal to or above the melting point of the molecular OSCM at the moment of implementing step (a) and in that the temperature profile of step (b) comprises: a first part corresponding to a sufficiently slow controlled cooling of the molecular OSCM down to a temperature close to the crystallization temperature of the molecular OSCM, so as to cause only a single seed to appear in the thin film in melt form; and a second part corresponding to controlled coo

Abstract: A Czochralski process (“CZ”) crystal growth method and furnace having a heater capable of generating a heating zone, a crucible within the heating zone and capable of retaining a volume of molten crystal growth material forming a melt line oriented in a designated position within the heating zone, a seed growth rod retractable from the crucible with a rod retraction mechanism, for forming a crystal boule thereon proximal the melt line from the molten crystal growth material. The furnace causes relative movement between the crucible and heating zone as the crystal boule is retracted, so that the melt line is maintained in the designated position within the heating zone. In some embodiments relative movement is based at least in part on sensed weight of the growing crystal boule. In other embodiments the crucible growth rod retraction mechanism are fixed relative to each other by a gantry.

Abstract: The present invention relates to an electrode composed of carbon having at least two different zones, wherein an outer zone (A) forms the base of the electrode and carries one or more inner zones, wherein the innermost zone (B) projects from the zone (A) at the top and has a lower specific thermal conductivity than zone (A).

Abstract: Devices and methods for providing stimulated Raman lasing are provided. In some embodiments, devices include a photonic crystal that includes a layer of silicon having a lattice of holes and a linear defect that forms a waveguide configured to receive pump light and output Stokes light through Raman scattering, wherein the thickness of the layer of silicon, the spacing of the lattice of holes, and the size of the holes are dimensioned to provide Raman lasing. In some embodiments, methods include forming a layer of silicon, and etching the layer of silicon to form a lattice of holes with a linear defect that forms a waveguide configured to receive pump light and output Stokes light through Raman scattering, wherein the thickness of the layer of silicon, the spacing of the lattice of holes, and the size of the holes are dimensioned to provide Raman lasing.

Abstract: A method for making iron silicide nano-wires comprises the following steps. Firstly, providing a growing substrate and a growing device, the growing device comprising a heating apparatus and a reacting room. Secondly, placing the growing substrate and a quantity of iron powder into the reacting room. Thirdly, introducing a silicon-containing gas into the reacting room. Finally, heating the reacting room to a temperature of 600˜1200° C.

Abstract: The present invention provides silicon-germanium hydride compounds, methods for their synthesis, methods for their deposition, and semiconductor structures made using the compounds. The compounds are defined by formula: SiHnI (GeHn2)y, wherein y is 2, 3, or 4 wherein n1 is 0 1, 2 or 3 to satisfy valency and wherein n2 is independently 0, 1, 2 or 3 for each Ge atom in the compound, to satisfy valency.

Abstract: A method of manufacturing a nano-crystalline silicon dot layer is provided. A silicon layer is formed over a substrate. The silicon layer includes crystalline silicon region and amorphous silicon region. An oxidation process is performed to oxidize the amorphous silicon region and the surfaces of the crystalline silicon region to form a silicon oxide layer containing nano-crystalline silicon dots.

Abstract: The present invention can provide a silicon semiconductor substrate used for and epitaxial wafer, in which uniform and high-level gettering ability is obtained irrespective of slicing positions from a silicon single crystal while generation of epitaxial defects can be suppressed, by doping carbon or carbon along with nitrogen during a pulling process of a CZ method or by performing appropriate heat treatment prior to the epitaxial process. Therefore, a crystal production yield can remarkably be improved because a permissible upper limit (concentration margin) of an oxygen concentration which is restricted by formation of a ring-shaped OSF region can be higher and also an excellent gettering ability is exhibited, while allowing an epitaxial wafer to be produced wherein epitaxial defects attributable to substrate crystal defects are not formed.

Abstract: A method for forming a structure of a desired cross-section on a substrate is provided. The method provides a seed structure comprising at least one support layer on the substrate. The support layer has a geometric shape related to the desired cross-section of the structure and is diffusive to a precursor constituent. The method further includes growing the structure by supplying at least one precursor constituent on the substrate. The desired cross-section of the structure is defined by the geometric shape of at least one support layer.

Abstract: Methods of making Si-containing films that contain relatively high levels of substitutional dopants involve chemical vapor deposition using trisilane and a dopant precursor. Extremely high levels of substitutional incorporation may be obtained, including crystalline silicon films that contain 2.4 atomic % or greater substitutional carbon. Substitutionally doped Si-containing films may be selectively deposited onto the crystalline surfaces of mixed substrates by introducing an etchant gas during deposition.

Abstract: The present invention relates to a method of manufacturing a wafer comprising a single crystalline bulk substrate of a first material and at least one epitaxial layer of a second material which has a lattice different from the lattice of the first material. The present invention provides a method for manufacturing a wafer in which a layer which is lattice-mismatched with the substrate can be grown on the substrate with a high effectiveness and high quality at a low cost. A roughening step is included for roughening the surface of the bulk substrate and a growing step is included for growing the second material on the rough surface with a reduced number of threading dislocations and an enhanced strain relaxation compared to a second material that is epitaxially grown on a polished surface.

Abstract: High throughput screening of crystallization of a target material is accomplished by simultaneously introducing a solution of the target material into a plurality of chambers of a microfabricated fluidic device. The microfabricated fluidic device is then manipulated to vary the solution condition in the chambers, thereby simultaneously providing a large number of crystallization environments. Control over changed solution conditions may result from a variety of techniques, including but not limited to metering volumes of crystallizing agent into the chamber by volume exclusion, by entrapment of volumes of crystallizing agent determined by the dimensions of the microfabricated structure, or by cross-channel injection of sample and crystallizing agent into an array of junctions defined by intersecting orthogonal flow channels.

Abstract: A growth crucible (2) for depositing on a seed crystal substrate (5) a silicon carbide single crystal (6) using a sublimate gas of a silicon carbide raw material (11) is disposed inside of an outer crucible (1). During the course of silicon carbide single crystal, a silicon raw material (22) is continuously fed from outside into a space between the growth crucible and the outer crucible for the purpose of vaporizing the silicon raw material. An atmosphere gas surrounding the growth crucible is constituted of a silicon gas. The pressure of the atmosphere silicon gas is controlled to suppress a variation in the composition of the sublimate gas within the growth crucible to thereby grow a large-sized silicon carbide single crystal with few crystal defects on the seed crystal substrate reliably at a high growth rate.

Abstract: The present invention is to produce a silicon crystal wherein the boron concentration in the silicon crystal and the growth condition V/G are controlled so that the boron concentration in the silicon crystal is no less than 1×1018 atoms/cm3 and the growth condition V/G falls within the epitaxial defect-free region ?2 whose lower limit line LN1 is the line indicating that the growth rate V gradually drops as the boron concentration increases. A silicon wafer is also produced wherein the boron concentration in the silicon crystal and the growth condition V/G are controlled so as to include at least the epitaxial defect region ?1, and both the heat treatment condition and the oxygen concentration of the silicon crystal are controlled so that no OSF nuclei grow to OSFs.

Abstract: A method of fabricating an epitaxial silicon-germanium layer for an integrated semiconductor device comprises the step of depositing an arsenic in-situ doped silicon-germanium layer, wherein arsenic and germanium are introduced subsequently into different regions of said silicon-germanium layer during deposition of said silicon-germanium layer. By separating arsenic from germanium any interaction between arsenic and germanium is avoided during deposition thereby allowing fabricating silicon-germanium layers with reproducible doping profiles.

Abstract: A single crystal of quartz thin film and a production method therefor are provided. A method for producing a quartz epitaxial thin film comprises the steps of vaporizing a silicon alkoxide as a silicon source under atmospheric pressure to introduce the silicon alkoxide to a substrate with hydrogen chloride as a reaction promoter, and reacting ethyl silicate with oxygen to deposit a quartz on the substrate. The single crystal of quartz thin film has excellent crystalinity, and optical properties.

Abstract: A silicon wafer and a method for manufacturing the same are provided, wherein the silicon wafer has no crystal defects in the vicinity of the surface and provides excellent gettering efficiency in the process of manufacturing devices without IG treatment. The oxygen concentration and the carbon concentration are controlled respectively within a range of 11×1017–17×1017 atoms/cm3 (OLD ASTM) and within a range of 1×1016–15×1016 atoms/cm3 (NEW ASTM). A denuded zone having no crystal defects due to the existence of oxygen is formed on the surface and in the vicinity thereof, and oxygen precipitates are formed at a density of 1×104–5×106 counts/cm2, when a heat treatment is carried out at a temperature of 500–1000° C. for 1 to 24 hours. In the method for manufacturing the silicon wafer, moreover, the silicon wafer having the oxygen and carbon concentrations as controlled above is heat-treated at a temperature of 1100° C.–1380° C. for 1 to 10 hours.

Abstract: The present invention provides a method of forming a strained semiconductor layer. The method comprises growing a strained first semiconductor layer, having a graded dopant profile, on a wafer, having a first lattice constant. The dopant imparts a second lattice constant to the first semiconductor layer. The method further comprises growing a strained boxed second semiconductor layer having the second lattice constant on the first semiconductor layer and growing a sacrificial third semiconductor layer having the first lattice constant on the second semiconductor layer. The method further comprises etch annealing the third and second semiconductor layer, wherein the third semiconductor layer is removed and the second semiconductor layer is relaxed.

Abstract: The present invention improves upon the Czochralski method for growing a single-crystal silicon ingot and provides a high quality silicon wafer having an oxide layer with superior voltage-resistance characteristics. An apparatus and method are also provided, whereby vacancy defect density and distribution are uniformly controlled. A single-crystal silicon ingot is grown under a condition where the temperature variation of the ingot is less than or equal to 20° C./cm in the temperature range of 1000 to 1100° C.

Abstract: Methods and apparatus for concurrent growth of multiple crystalline ribbons from a single crucible employ meniscus shapers to facilitate continuous growth of discrete and substantially flat crystalline ribbons having controlled width.

Abstract: In a semiconductor element comprising microcrystalline semiconductor, a semiconductor junction is provided within a microcrystal grain. Further, in a semiconductor element comprising microcrystalline semiconductor, microcrystal grains of different grain diameters are provided as a mixture to form a semiconductor layer. Thereby, discontinuity of a semiconductor junction is lessened to thereby improve the characteristics, durability, and heat resisting properties of a semiconductor element. Distortion in a semiconductor layer is also reduced.

Abstract: A wafer is characterized in that the wafer has a non-uniform distribution of crystal lattice vacancies, wherein the concentration of crystal lattice vacancies in the bulk layer are greater than the concentration of crystal lattice vacancies in the front surface layer. In addition, the front surface of the wafer has an epitaxial layer, having a thickness of less than about 2.0 çm, deposited thereon. A process comprises heating a surface of a wafer starting material to remove a silicon oxide layer from the surface and depositing an epitaxial layer onto the surface to form an epitaxial wafer. The epitaxial wafer is then heated to a soak temperature of at least about 1175C. while exposing the epitaxial layer to an oxidizing atmosphere comprising an oxidant, and the wafer is cooled at a rate of at least about 10C./sec.

Abstract: The present invention provides a method and apparatus for growing a single crystal by the Czochralski method, wherein a single crystal is grown with forced cooling of neighborhood of a crystal growth interface by disposing a cooling cylinder formed of copper or a metal having a heat conductivity larger than that of copper at least in the vicinity of the crystal growth interface so as to surround the single crystal under pulling and circulating a cooling medium in the cooling cylinder. Thus, there are provided a method and apparatus for growing a single crystal, which can exert cooling effect on a growing single crystal to the maximum extent so as to realize higher crystal growth rate, even when a silicon single crystal having a diameter of 300 mm or more is grown.

Abstract: Analysis of residual gases from a process for depositing a film containing silicon on a crystalline silicon surface to determine partial pressure of hydrogen evolved during deposition develops a signature which indicates temperature and/or concentration of germanium at the deposition surface. Calibration and collection of hydrogen partial pressure data at a rate which is high relative to film deposition rate allows real-time, in-situ, non-destructive determination of material concentration profile over the thickness of the film and/or monitoring the temperature of a silicon film deposition process with increased accuracy and resolution to provide films of a desired thickness with high accuracy.

Abstract: Foamed polycrystalline silicon having bubbles therein and an apparent density of 2.20 g/cm3 or less. This silicon generates an extremely small amount of fine grains by crushing and can be easily crushed. There is also provided a method of producing foamed polycrystalline silicon. There is further provided a polycrystalline silicon production apparatus in which the deposition and melting of silicon are carried out on the inner surface of a cylindrical vessel, a chlorosilane feed pipe is inserted into the cylindrical vessel to a silicon molten liquid, and seal gas is supplied into a space between the cylindrical vessel and the chlorosilane feed pipe.

Abstract: A method and apparatus for controlled, extended and repeatable growth of high quality silicon carbide boules of a desired polytype is disclosed which utilizes graphite crucibles coated with a thin coating of a metal carbide and in particular carbides selected from the group consisting of tantalum carbide, hafnium carbide, niobium carbide, titanium carbide, zirconium carbide, tungsten carbide and vanadium carbide.

Abstract: Methods and apparatus for concurrent growth of multiple crystalline ribbons from a single crucible employ meniscus shapers to facilitate continuous growth of discrete and substantially flat crystalline ribbons having controlled width.

Abstract: There is provided a manufacturing process for a CZ silicon single crystal wafer which is subjected to heat treatment wherein slip resistance of a portion of the CZ silicon single crystal wafer in contact with a heat treatment boat is improved with extreme simplicity, convenience and very low cost. A silicon single crystal rod is grown by means of a Czochralski method in a condition that an OSF ring region is formed in a peripheral region of the silicon single crystal rod and the grown silicon signal crystal rod is processed into silicon single crystal wafers, whereby the silicon single crystal wafer is obtained such that when the silicon single crystal wafer is subjected to heat treatment, at least a portion of the silicon single crystal wafer in contact between the wafer and the boat is formed of an OSF ring region.

Abstract: A method for making photonic crystal structures using amorphous silicon that is temperature compatible with a wide variety of substrates. Both hydrogenated and non-hydrogenated amorphous silicon may be used.

Abstract: A process of fabricating a CMOS device comprised with super-steep retrograde (SSR), twin well regions, has been developed. The process features the use of two, selective epitaxial growth (SEG), procedures, with the first SEG procedure resulting in the growth of bottom silicon shapes in the PMOS, as well as in the NMOS region of the CMOS device. After implantation of the ions needed for the twin well regions, into the bottom silicon shapes, a second SEG procedure is employed resulting in growth of top silicon shapes on the underlying, implanted bottom silicon shapes. An anneal procedure then distributes the implanted ions resulting in an SSR N well region in the composite silicon shape located in the PMOS region, and resulting in an SSR P well region in the composite silicon shape located in the NMOS region of the CMOS device.

Abstract: A method for the high-throughput non-photochemical laser induced nucleation of crystals from aged supersaturated solutions in which short high-intensity laser pulses are used to induce nucleation in an array or sequence aged supersaturated solutions. The laser reduces nucleation time and induces nucleation only in the area where the beam is focused or passes through, resulting in fewer nuclei than would be achieved by spontaneous nucleation. The high-throughput methodologies allow more crystals to grow in a given amount of time.

Abstract: When a polycrystalline or single crystal silicon layer is grown by catalytic CVD, a catalyst having a nitride covering at least its surface is used. In case that tungsten is used as the catalyst, tungsten nitride is formed as the nitride. The nitride is made by heating the surface of the catalyst to a high temperature around 1600 to 2100° C. in an atmosphere containing nitrogen prior to the growth. When the catalyst is heated to the temperature for its use or its nitrification, it is held in a hydrogen atmosphere.

Abstract: A method for the production of a semiconductor wafer having a front and a back and an epitaxial layer of semiconductor material deposited on the front, includes the following process steps: (a) preparing a substrate wafer having a polished front and a specific thickness; (b) pretreating the front of the substrate wafer in the presence of HCl gas and a silane source at a temperature of from 950 to 1250 degrees Celsius in an epitaxy reactor, the thickness of the substrate wafer remaining substantially unchanged; and (c) depositing the epitaxial layer on the front of the pretreated substrate wafer.

Abstract: A method for the non-photochemical laser induced nucleation in which short high-intensity laser pulses are used to induce nucleation in supersaturated solutions including protein solutions. The laser induces nucleation only in the area where the beam is focused or passes through, resulting in fewer nuclei than would be achieved by spontaneous nucleation. In addition, the laser reduces nucleation time significantly.

Abstract: A single crystal silicon wafer with a back surface free of an oxide seal and substantially free of a chemical vapor deposition process induced halo and an epitaxial silicon layer on the front surface, the epitaxial layer is characterized by an axially symmetric region extending radially outwardly from the central axis of the wafer toward the circumferential edge of the wafer having a substantially uniform resistivity, the radius of the axially symmetric region being at least about 80% of the length of the radius of the wafer.

Abstract: Performing the post-implantation annealing for recovering crystallinity in a hydrogen atmosphere can successfully suppress the surface roughening on the ion-implanted layers without pre-implantation oxidation. This allows omission of the pre-implantation oxidation and allows ion implantation using only a photoresist film as a mask in a method for producing an epitaxial wafer having buried ion-implanted layers. Since an intentional formation of an oxide film, including such pre-implantation oxidation, on an epitaxial layer is omitted, the number of repetition of the thermal history exerted to the buried ion-implanted layers can be reduced, which effectively suppresses lateral diffusion of implanted ions. Since the formation and removal of the oxide film is thus no more necessary, the number of process steps in the production of the epitaxial wafer can dramatically be reduced.

Abstract: A method of forming a periodic index of refraction pattern in a superlattice of a solid material to achieve photonic bandgap effects at desired optical wavelengths is disclosed. A plurality of space group symmetries, including a plurality of empty-spaced buried patterns, are formed by drilling holes in the solid material and annealing the solid material to form empty-spaced patterns of various geometries. The empty-spaced patterns may have various sizes and may be formed at different periodicities, so that various photonic band structures can be produced for wavelength regions of interest.

Abstract: This invention is directed to a novel a single crystal silicon wafer. In one embodiment, this wafer comprises: (a) two major generally parallel surfaces (i.e., the front and back surfaces); (b) a central plane between and parallel to the front and back surfaces; (c) a front surface layer which comprises the region of the wafer extending a distance of at least about 10 &mgr;m from the front surface toward the central plane; and (d) a bulk layer which comprises the region of the wafer extending from the central plane to the front surface layer.

Abstract: A process for preparing a silicon epitaxial wafer. The wafer has a front surface having an epitaxial layer deposited thereon, a back surface, and a bulk region between the front and back surfaces, wherein the bulk region contains a concentration of oxygen precipitates. In the process, the wafer is first subjected to an ideal oxygen precipitating heat treatment to causes the formation of a non-uniform distribution of crystal lattice vacancies with the concentration of vacancies in the bulk region being greater than the distribution of vacancies in the front surface. The ideal precipitating wafer is then subjected to an oxygen precipitation heat treatment to cause the nucleation and growth of oxygen precipitates to a size sufficient to stabilize the oxygen precipitates, with the oxygen precipitates being formed primarily according to the vacancy profile. An epitaxial layer is then deposited on the surface of the oxygen precipitate stabilized wafer.

Abstract: A method of optimizing a process of selective epitaxial growth sets a guideline for the reaction temperature, pressure, and gas ratio and calculates a non-equilibrium factor (NEF=[exp(l−(A/B))×C−D]×F×(1/S)) depending on the characteristic of the equipment and the types of source gases by controlling a super-saturation ratio depending on a basic thermodynamic law. The selective epitaxial growth by CVD is a deposition method by which a reactive product by thermal activation of a reactive gas is obtained in the shape of a thin film. Therefore, it can successfully form the selective epitaxial growth through control of the super-saturation ratio so that the selective epitaxial growth can be optimized. Also, the method can optimize the process by monitoring the quality of the thin film such as selectivity securing control of deposition speed, facet, reduction in deflects, etch depending on the pattern material.

Abstract: By forming a silicon single-crystal thin film direct on a chemically etched substrate, a time required for all the process can be effectively shortened, which largely contributes to reduction in production cost of a silicon epitaxial wafer and improvement on production efficiency thereof, with the result that a reduced wafer price at a user's end and a short delivery time are ensured. In a technical aspect, an etching removal in a chemical etching treatment is set to be 60 &mgr;m or more and thereby, a glossiness of a front main surface of a chemically etched substrate can be ensured to be 95% or higher. With such a glossiness of the front main surface of the substrate employed, a surface glossiness of a silicon single-crystal thin film formed on the front main surface of the chemically etched substrate can be increased to 95% or higher, thereby, enabling an auto-alignment treatment in a lithographic step coming later with no trouble.

Abstract: AFM/STM probes are based on whiskers grown by the vapor-liquid-solid (VLS) mechanism. Silicon cantilevers oriented along the crystallographic plane (111) are prepared from silicon-on-insulator structures that contain a thin layer (111) on a (100) substrate with SiO2 interposed layer. At removal of solidified alloy globules inherent in the growth mechanism sharpening of the whiskers takes place and, in such a way, the probes are formed. Cross-sections of the wiskers grown by the mechanism on the cantilevers can be controllably changed during the growth process so that step-shaped whiskers optimal for fabrication of the probes can be prepared. Also, whiskers with expansions/contractions can be formed that are important for fabrication of probes suitable for investigations in coarse surfaces, complicated cavitites, grooves typical for semiconductor microelectronics, etc.

Abstract: The method is characterized in that layers of sufficient quality for epitaxy are placed on workpieces, at a considerably increased deposition rate. To this end, instead of a UHV-CVD or ECR-CVD method, for example, a PECVD method is used by means of a DC plasma discharge.