With Significant Flow Manipulation Or Condition, Other Than Merely Specifying The Components Or Their Sequence Or Both Patents (Class 117/93)
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Patent number: 6994751Abstract: A nitride-based semiconductor element having superior mass productivity and excellent element characteristics is obtained. This nitride-based semiconductor element comprises a substrate comprising a surface having projection portions, a mask layer formed to be in contact with only the projection portions of the surface of the substrate, a first nitride-based semiconductor layer formed on recess portions of the substrate and the mask layer and a nitride-based semiconductor element layer, formed on the first nitride-based semiconductor layer, having an element region. Thus, the first nitride-based semiconductor layer having low dislocation density is readily formed on the projection portions of the substrate and the mask layer through the mask layer serving for selective growth.Type: GrantFiled: February 25, 2002Date of Patent: February 7, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Masayuki Hata, Tatsuya Kunisato, Nobuhiko Hayashi
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Patent number: 6972050Abstract: The invention relates to a method for depositing especially, crystalline layers onto especially, crystalline substrates, in a process chamber of a CVD reactor. At least one first and one second reaction gas are each led into a gas outlet area in an input area of the process chamber, by means of separate delivery lines. The gas outlet areas lie one above the other between the floor of the process chamber and the cover of the process chamber and have different heights. The first reaction gas flows out of the gas outlet area that is situated next to the process chamber floor, optionally together with a carrier gas. A carrier gas is added at least to the second reaction gas, which flows out of the gas outlet area lying further away from the process chamber floor.Type: GrantFiled: May 15, 2003Date of Patent: December 6, 2005Assignee: Aixtron AGInventors: Michael Bremser, Martin Dauelsberg, Gerhard Karl Strauch
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Patent number: 6932866Abstract: The invention relates to a method and a device for depositing especially crystalline layers on especially crystalline substrates in a process chamber of a reactor housing having a water-cooled wall. The floor of said process chamber is heated. At least one reaction gas as a process gas, and hydrogen as a carrier gas, are centrally introduced into the process chamber, and are extracted by a gas evacuation ring surrounding the process chamber. A flush gas flows between the cover of the reactor and the cover of the process chamber. Said flush gas and the flush gas which flushes the area between the reactor wall and the gas evacuation ring are introduced into the outer region of the process chamber, via a gap between the cover of the reactor and the gas evacuation ring which can be lowered for loading the process chamber, in order to be sucked through the openings in the gas evacuation ring with the process gas.Type: GrantFiled: June 23, 2003Date of Patent: August 23, 2005Assignee: Aixtron AGInventor: Martin Dauelsberg
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Patent number: 6923860Abstract: The present invention is a tunneling magnetoresistive (TMR) stack configured to operate in a current-perpendicular-to-plane (CPP) mode, wherein a sense current flows substantially perpendicular to a longitudinal plane of the barrier layer. The TMR stack has a plurality of layers including a barrier layer. The barrier layer may made of titanium and may be oxidized with an aggressive oxidation method, such as with UV illumination, for a predetermined time period. The barrier layer may be formed on a first ferromagnetic layer before oxidation, and then a second ferromagnetic layer may be formed on the oxidized barrier layer. The TMR stack exhibits an increased magnetoresistive (MR) ratio, a lower RA product, a higher breakdown voltage of the TMR stack, and greater thermal stability.Type: GrantFiled: March 27, 2003Date of Patent: August 2, 2005Assignee: Seagate Technology LLCInventors: Brian W. Karr, Mark T. Kief, Janusz J. Nowak
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Patent number: 6902620Abstract: Atomic layer deposition systems and methods are disclosed utilizing a multi-wafer sequential processing chamber. The process gases are sequentially rotated among the wafer stations to deposit a portion of a total deposition thickness on each wafer at each station. A rapid rotary switching of the process gases eliminates having to divert the process gases to a system vent and provides for atomic layer film growth sufficient for high-volume production applications. Conventional chemical vapor deposition can also be performed concurrently with atomic layer deposition within the multi-wafer sequential processing chamber.Type: GrantFiled: December 19, 2001Date of Patent: June 7, 2005Assignee: Novellus Systems, Inc.Inventors: Thomas R. Omstead, Karl B. Levy
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Patent number: 6896730Abstract: An atomic layer deposition method includes positioning a semiconductor substrate within an atomic layer deposition chamber. A fixed volume first precursor gas charge is provided within a gas flow path to the deposition chamber. A fixed volume purge gas charge is provided within the gas flow path serially upstream of the first precursor gas charge. The first precursor gas charge and the purge gas charge are serially flowed along the gas flow path to the substrate within the deposition chamber effective to form a monolayer on the substrate and purge at least some of the first precursor gas from the substrate. Apparatus are also disclosed.Type: GrantFiled: June 5, 2002Date of Patent: May 24, 2005Assignee: Micron Technology, Inc.Inventors: Garo J. Derderian, Cem Basceri, Gurtej S. Sandhu, Demetrius Sarigiannis
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Patent number: 6875272Abstract: In a method for growing a GaN based compound semiconductor on a front surface of a substrate to obtain the GaN based compound semiconductor crystal in one body, because the gas for reducing and decomposing the substrate is supplied to the rear surface of the substrate and a heat treatment is carried out in a gas atmosphere in which the nitrogen partial pressure is not less than a predetermined value, in order to remove the substrate, it can be prevented that cracks are caused in the crystal, or fracture or warp is caused by causing strain of the GaN based compound semiconductor crystal in a cooling step.Type: GrantFiled: June 14, 2002Date of Patent: April 5, 2005Assignee: Nikko Materials Co., Ltd.Inventors: Keiji Kainosho, Shinichi Sasaki
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Patent number: 6869480Abstract: Methods are disclosed that provide for structures and techniques for the fabrication of ordered arrangements of crystallographically determined nanometer scale steps on single crystal substrates, particularly SiC. The ordered nanometer scale step structures are produced on the top surfaces of mesas by a combination of growth and etching processes. These structures, sometimes referred to herein as artifacts, are to enable step-height calibration, particularly suitable for scanning probe microscopes and profilometers, from less than one nanometer (nm) to greater than 10 nm, with substantially no atomic scale roughness of the plateaus on either side of each step.Type: GrantFiled: July 17, 2002Date of Patent: March 22, 2005Assignee: The United States of America as represented by the United States National Aeronautics and Space AdministrationInventors: Phillip B. Abel, J. Anthony Powell, Philip G. Neudeck
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Patent number: 6869481Abstract: A method and a device for regulating a pressure in an epitaxy reactor, wherein the epitaxy reactor has a wafer handling chamber WHC, a process chamber PC, and a gate valve GV connecting the two chambers. The wafer handling chamber is continuously purged with inert gas. The pressure difference between the wafer handling chamber and the process chamber is measured, and the resulting measurement signal is used in a control circuit to regulate the pressure in the wafer handling chamber. In this case the pressure in the wafer handling chamber is reduced if the pressure difference is above a predetermined value and the pressure in the wafer handling chamber is increased if the pressure difference is below a predetermined value. The predetermined pressure difference is defined as a pressure being between 5 and 500 PA. The WHC and the PC each have a gas discharge line and a gas input line.Type: GrantFiled: December 27, 2002Date of Patent: March 22, 2005Assignee: Siltronic AGInventors: Anton Schatzeder, Georg Brenninger
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Patent number: 6863727Abstract: This invention concerns a method for depositing transition metal nitride thin films by an Atomic Layer Deposition (ALD) type process. According to the method vapor-phase pulse of a source material, a reducing agent capable of reducing metal source material, and a nitrogen source material capable of reacting with the reduced metal source material are alternately and sequentially fed into a reaction space and contacted with the substrate. According to the invention as the reducing agent is used a boron compound which is capable of forming gaseous reaction byproducts when reacting with the metal source material.Type: GrantFiled: October 13, 2000Date of Patent: March 8, 2005Assignee: ASM International N.V.Inventors: Kai-Erik Elers, Suvi Päivikki Haukka, Ville Antero Saanila, Sari Johanna Kaipio, Pekka Juha Soininen
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Patent number: 6863726Abstract: A vapor phase growth method of an oxide dielectric film for forming an oxide dielectric film having a perovskite crystal structure expressed by ABO3 on a substrate according to the present invention includes a first step of sequentially and alternately supplying an A-site layer element material and a B-site layer element material to grow an atomic layer on the substrate to form an early layer or early core, at a first substrate temperature, and a second step of raising the temperature to a second substrate temperature that is higher than the first substrate temperature to crystallize the early layer or early core formed in the first step and simultaneously supplying both the A-site layer element material and the B-site layer element material to form an ABO3 film.Type: GrantFiled: April 22, 2003Date of Patent: March 8, 2005Assignee: NEC Electronics CorporationInventor: Takashi Hase
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Patent number: 6860138Abstract: A method of preventing the scrapping of semiconductor substrates due to improper deposition of thin films in a thin film vaporization system is disclosed. This is accomplished by providing a method of self-calibrating and testing the flow of liquid precursors in the vaporization system prior to the start of the deposition process. The vaporization of the liquid precursor in the deposition chamber and the concomitant pressure change in the chamber are correlated. This correlation is then used as a real time monitoring mechanism for self-calibrating and testing the flow of liquid precursors through the vaporization system. That the pressure change due to vaporization in the chamber is used as the key parameter, the thin film deposition is hence monitored by that parameter which directly predicts the film deposition characteristics. Consequently, each thin film run is assured of a successful run.Type: GrantFiled: February 21, 2002Date of Patent: March 1, 2005Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chung-Ju Hsieh, Hsi-Wen Liao, Kai-Hsin Liu, Tsu-Kuang Hou
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Patent number: 6860943Abstract: Disclosed is a method for producing a Group III nitride compound semiconductor including a pit formation step in which a portion of an uppermost layer of a first Group III nitride compound semiconductor layer containing one or more sub-layers, the portion containing lattice defects, is subjected to treatment by use of a solution or vapor which corrodes the portion more easily than it corrodes a portion of the uppermost layer containing no lattice defects, the first Group III nitride compound semiconductor layer not being accompanied by a substrate therefor as a result of removal therefrom, or being accompanied by a substrate such that the semiconductor layer is formed with or without intervention of a buffer layer provided on the substrate; and a lateral growth step of growing a second Group III nitride compound semiconductor layer through vertical and lateral epitaxial overgrowth around nuclei as seeds for crystal growth which are on flat portions of the uppermost layer of the first Group III nitride compounType: GrantFiled: October 11, 2002Date of Patent: March 1, 2005Assignee: Toyoda Gosei Co., Ltd.Inventors: Masayoshi Koike, Hiroshi Watanabe
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Patent number: 6841002Abstract: Carbon nanotubes are formed on a surface of a substrate using a plasma chemical deposition process. After the nanotubes have been grown, a post-treatment step is performed on the newly formed nanotube structures. The post-treatment removes graphite and other carbon particles from the walls of the grown nanotubes and controls the thickness of the nanotube layer. The post-treatment is performed with the plasma at the same substrate temperature. For the post-treatment, the hydrogen containing gas is used as a plasma source gas. During the transition from the nanotube growth step to the post-treatment step, the pressure in the plasma process chamber is stabilized with the aforementioned purifying gas without shutting off the plasma in the chamber. This eliminates the need to purge and evacuate the plasma process chamber.Type: GrantFiled: November 22, 2002Date of Patent: January 11, 2005Assignee: cDream Display CorporationInventors: Sung Gu Kang, Craig Bae
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Patent number: 6841003Abstract: Carbon nanotubes are formed on a surface of a substrate using a plasma chemical deposition process. After the nanotubes have been grown, a purification step is performed on the newly formed nanotube structures. The purification removes graphite and other carbon particles from the walls of the grown nanotubes and controls the thickness of the nanotube layer. The purification is performed with the plasma at the same substrate temperature. For the purification, the hydrogen containing gas added as an additive to the source gas for the plasma chemical deposition is used as the plasma source gas. Because the source gas for the purification plasma is added as an additive to the source gas for the chemical plasma deposition, the grown carbon nanotubes are purified by reacting with the continuous plasma which is sustained in the plasma process chamber. This eliminates the need to purge and evacuate the plasma process chamber as well as to stabilize the pressure with the purification plasma source gas.Type: GrantFiled: November 22, 2002Date of Patent: January 11, 2005Assignee: cDream Display CorporationInventors: Sung Gu Kang, Craig Bae
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Patent number: 6821340Abstract: To provide a method of manufacturing silicon carbide by forming silicon carbide on a substrate surface from an atmosphere containing a silicon carbide feedstock gas comprising at least a silicon source gas and a carbon source gas under condition 1 or 2 below: Condition 1: the partial pressure ps of silicon source gas is constant (with ps>0), the partial pressure of carbon source gas consists of a state pc1 and a state pc2 that are repeated in alternating fashion, wherein pc1 and pc2 denote partial pressures of carbon source gas, pc1>pc2, and pc1/ps falls within a range of 1-10 times the attachment coefficient ratio (Ss/Sc), pc2/ps falls within a range of less than one time Ss/Sc; Condition 2: the partial pressure pc of carbon source gas is constant (with pc>0), the partial pressure of silicon source gas consists of a state ps1 and a state ps2 that are repeated in alternating fashion, wherein ps1 and ps2 denote partial pressures of silicon source gas, ps1<ps2, and pc/ps1 falls within a range of 1Type: GrantFiled: May 31, 2001Date of Patent: November 23, 2004Assignee: Hoya CorporationInventors: Hiroyuki Nagasawa, Takamitsu Kawahara, Kuniaki Yagi
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Patent number: 6811611Abstract: A method and system for growing a crystalline layer on a substrate. Using an electrically-shielded RF (ESRF) source, a plasma is created and directed to a substrate inside the ESRF source. The plasma arrives at the substrate surface with a high mobility and enables its constituents to form a highly regular structure on the substrates.Type: GrantFiled: August 16, 2002Date of Patent: November 2, 2004Assignee: Tokyo Electron LimitedInventor: Wayne L. Johnson
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Patent number: 6810897Abstract: To provide a process gas supply mechanism for ALCVD systems that enables the high speed switching of process gases without accompanying particulate contamination of the treatment substrate. The ALCVD system is provided with a CVD treatment section and a process gas supply section. The process gas supply section contains a reactant gas line and a carrier gas line; these are combined to form a joint flow line. A vent line is connected to the reactant gas line upstream from the joint flow position. A stop valve SV and a needle valve NV are disposed in the vent line. This needle valve NV functions as a setting means in order to set the flow rate of the gas flowing in the vent line. The stop valve SV is driven through repetitive switching operations by a drive control element, thereby effecting supply and nonsupply of the reactant gas.Type: GrantFiled: May 17, 2002Date of Patent: November 2, 2004Assignee: L'Air Liquide, Societe Anonyme a Directoire et Conseil de Surveillance pour l'Etude et l'Exploitation des Procedes Georges ClaudeInventors: Jean-Marc Girard, Takako Kimura
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Patent number: 6808564Abstract: A process for forming an epitaxial layer on a semiconductor wafer substrate is provided. The process comprises providing a semiconductor wafer substrate and an area for forming an epitaxial layer on said semiconductor wafer substrate. The formation area consists essentially of an epitaxial layer process chamber. The semiconductor wafer substrate is introduced into the epitaxial layer process chamber and an epitaxial layer is formed on at least one surface of the semiconductor wafer substrate. At least one epitaxial layer surface is substantially hydrophobic. Then, a chemical reagent is introduced into said epitaxial layer process chamber. The chemical reagent reacts with the epitaxial layer surface in situ to form an outer layer.Type: GrantFiled: March 12, 2003Date of Patent: October 26, 2004Assignee: SEH America, Inc.Inventor: Gerald R. Dietze
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Patent number: 6803071Abstract: A method of deposition of a microwave frequency paraelectric BST-based thin film on a SiC substrate provides a resulting thin film-substrate structure which has no interfacial phases or element/chemical interdiffusion. For physical vapor deposition of the thin film, at least one of (i) thermally stable, refractory semiconductor substrate material is heat-treated during film deposition and (ii) the film-substrate structure is post-deposition heat treated, e.g., annealed, to achieve high quality film crystallinity with a fully developed film microstructure having desired microwave dielectric and insulating properties. For chemical solution deposition, the thin film is deposited onto a thermally stable, refractory semiconductor substrate material and is post-deposition heat treated to achieve a high quality film with a fully developed film microstructure having desired microwave dielectric and insulating properties.Type: GrantFiled: January 10, 2003Date of Patent: October 12, 2004Assignee: The United States of America as represented by the Secretary of the ArmyInventor: Melanie W. Cole
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Patent number: 6786968Abstract: A method for making photonic crystal structures using amorphous silicon that is temperature compatible with a wide variety of substrates. Both hydrogenated and non-hydrogenated amorphous silicon may be used.Type: GrantFiled: October 31, 2002Date of Patent: September 7, 2004Assignee: Agilent Technologies, Inc.Inventor: Jeremy A. Theil
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Patent number: 6780241Abstract: The present invention provides methods of manufacturing and integrating optical devices. In one embodiment, a method of integrating an optical device may include forming a first device over a substrate, and forming a second device over the substrate and adjacent the first device with a deposition gas having an etchant selective to a deposited component of the deposition gas.Type: GrantFiled: September 26, 2002Date of Patent: August 24, 2004Assignee: TriQuint Technology Holding Co.Inventors: Abdallah Ougazzaden, Justin Larry Peticolas, Jr., Andrei Sirenko
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Patent number: 6773507Abstract: Method and apparatus for depositing layers by atomic layer deposition. A virtual shower curtain is established between the substrate support and chamber to minimize the volume in which the reactants are distributed. A showerhead may be used to allow closer placement of the substrate thereto, further reducing the reaction volume. Zero dead space volume valves with close placement to the chamber lid and fast cycle times also improve the cycle times of the process.Type: GrantFiled: August 7, 2002Date of Patent: August 10, 2004Assignee: Applied Materials, Inc.Inventors: Ravi Jallepally, Shih-Hung Li, Alain Duboust, Jun Zhao, Liang-Yuh Chen, Daniel A. Carl
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Patent number: 6764546Abstract: An improved apparatus and method for substrate layer deposition in which substrate layers are grown by carrier gas delivery of sequential pulses of reactants to the substrate surface. At least one of the reactants comprises excited species, e.g., radicals. In a specific embodiment, the apparatus of this invention provides sequential repeated pulses of reactants in a flow of carrier gas for reaction at a substrate surface. The reactant pulses are delivered with sufficient intervening delay times to minimize undesirable reaction between reactants in adjacent pulses in the gas phase or undesired uncontrolled reactions on the substrate surface.Type: GrantFiled: December 10, 2002Date of Patent: July 20, 2004Assignee: ASM International N.V.Inventor: Ivo Raaijmakers
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Patent number: 6746941Abstract: It is an object of the invention to provide a semiconductor wafer obtained by forming a semiconductor thin film with uniform resistivity on a main surface of a semiconductor single crystal substrate of 300 mm or more in diameter. When a process gas is supplied to over a main surface of a silicon single crystal substrate 12 in rotation in almost parallel to the main surface thereof in one direction in a reaction chamber 10 through six inlet ports 18a to 18f disposed in width direction of the reaction chamber 10, H2 gas, a semiconductor raw material gas and a dopant gas are supplied onto an area in the vicinity of the center of the main surface of the silicon single crystal substrate 12 and an intermediate area thereof through the inner inlet ports 18a and 18b and the middle inlet ports 18c and 18d, and only H2 gas and the semiconductor raw material gas without the dopant gas are supplied onto an area in the vicinity of the outer periphery thereof from the outer inlet ports 18e and 18f.Type: GrantFiled: August 23, 2002Date of Patent: June 8, 2004Assignee: Shin-Etsu Handotai Co., Ltd.Inventor: Hiroki Ose
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Patent number: 6743291Abstract: A process of fabricating a CMOS device comprised with super-steep retrograde (SSR), twin well regions, has been developed. The process features the use of two, selective epitaxial growth (SEG), procedures, with the first SEG procedure resulting in the growth of bottom silicon shapes in the PMOS, as well as in the NMOS region of the CMOS device. After implantation of the ions needed for the twin well regions, into the bottom silicon shapes, a second SEG procedure is employed resulting in growth of top silicon shapes on the underlying, implanted bottom silicon shapes. An anneal procedure then distributes the implanted ions resulting in an SSR N well region in the composite silicon shape located in the PMOS region, and resulting in an SSR P well region in the composite silicon shape located in the NMOS region of the CMOS device.Type: GrantFiled: July 9, 2002Date of Patent: June 1, 2004Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Chew Hoe Ang, Wenhe Lin, Jia Zhen Zheng
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Patent number: 6726768Abstract: A mask and its application in sequential lateral solidification (SLS) crystallization of amorphous silicon. The mask includes a light absorptive portion that blocks a laser beam and a plurality of tier-shaped light-transmitting portions that pass a laser beam. Each light-transmitting portion has a plurality of adjacent rectangular sub-portions. Adjacent rectangular sub-portions form a step. In operation, the mask moves transversely relative to a amorphous silicon film while a laser performs SLS crystallization. The light portions control grain growth such that high quality polycrystalline silicon is formed.Type: GrantFiled: April 30, 2002Date of Patent: April 27, 2004Assignee: LG. Philips LCD Co., Ltd.Inventor: Jin-Mo Yoon
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Patent number: 6720260Abstract: Ion-induced, UV-induced, and electron-induced sequential chemical vapor deposition (CVD) processes are disclosed where an ion flux, a flux of ultra-violet radiation, or an electron flux, respectively, is used to induce the chemical reaction in the process. The process for depositing a thin film on a substrate includes introducing a flow of a first reactant gas in vapor phase into a process chamber where the gas forms an adsorbed saturated layer on the substrate and exposing the substrate to a flux of ions, a flux of ultra-violet radiation, or a flux of electrons for inducing a chemical reaction of the adsorbed layer of the first reactant gas to form the thin film. A second reactant gas can be used to form a compound thin film. The ion-induced, UV-induced, and electron-induced sequential CVD process of the present invention can be repeated to form a thin film of the desired thickness.Type: GrantFiled: June 20, 2003Date of Patent: April 13, 2004Assignee: Novellus Systems, Inc.Inventors: James A. Fair, Nerissa Taylor
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Publication number: 20040055530Abstract: A micro electron gun that is capable of extracting electrons from a semiconductor utilizing a quantum size effect and that can be mounted individually for each of pixels is disclosed, as well as a picture display apparatus using such electron guns which is high in quantum efficiency, of high brightness and thin, as well as methods of manufacture thereof. Conduction electrons from a n-type semiconductor substrate (2) are accelerated under an electric field through a layer or layers (4) of quantum size effect micro particles (3) formed on surfaces of the n-type semiconductor substrate (2) and passed therethrough without undergoing phonon scattering, so that they when arriving at an electrode (5) may possess an amount of energy not less than the work function of the electrode (5) and are thus allowed to spring out into a vacuum.Type: ApplicationFiled: September 23, 2003Publication date: March 25, 2004Applicant: JAPAN SCIENCE AND TECHNOLOGY CORPORATIONInventors: Shunri Oda, Xinwei Zhao, Katsuhiko Nishiguchi
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Patent number: 6706116Abstract: Methods of forming an electrically conductive line include providing a stress inducing material within or a compressive stress inducing layer, operatively adjacent a crystalline material of a first crystalline phase. In addition, such methods include annealing the crystalline material of the first crystalline phase under conditions effective to transform it to a second crystalline phase. Some methods also include providing stress inducing materials into a refractory metal layer. Example compressive stress inducing layers include SiO2 and Si3N4, while example stress inducing materials include Ge, W and Co. Where the compressive stress inducing material is provided on the same side of a wafer over which the crystalline phase material is provided, it is provided to have a thermal coefficient of expansion which is less than the first phase crystalline material. Example and preferred crystalline phase materials having two phases are refractory metal silicides, such as TiSix.Type: GrantFiled: May 29, 2002Date of Patent: March 16, 2004Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Sujit Sharan
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Patent number: 6689210Abstract: The invention relates to an apparatus for growing thin films onto the surface of a substrate by exposing the substrate to alternately repeated surface reactions of vapor-phase reactants. The apparatus comprises at least one process chamber having a tightly sealable structure, at least one reaction chamber having a structure suitable for adapting into the interior of said process chamber and comprising a reaction space of which at least a portion is movable, infeed means connectable to said reaction space for feeding said reactants into said reaction space, and outfeed means connectable to said reaction space for discharging excess reactants and reaction gases from said reaction space, and at least one substrate adapted into said reaction space.Type: GrantFiled: July 24, 2002Date of Patent: February 10, 2004Assignee: ASM Microchemistry OyInventors: Pekka T. Soininen, Vaino Kilpi
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Patent number: 6685774Abstract: A method of growing epitaxial layers on a wafer is provided and includes providing a wafer carrier having a surface for retaining the wafer; placing the wafer on the wafer-retaining surface of the wafer carrier while the wafer carrier is in a loading position separated from a spindle; transporting the wafer carrier toward the spindle; detachably mounting the wafer carrier on the upper end of the spindle for rotation therewith; and rotating the spindle and the wafer carrier while introducing one or more reactants into the reaction chamber. The invention also described several embodiments and variants of the method of the invention.Type: GrantFiled: October 10, 2002Date of Patent: February 3, 2004Assignee: Emcore CorporationInventors: Vadim Boguslavskiy, Alexander Gurary
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Patent number: 6645574Abstract: A noble method of forming thin films for producing semiconductor or flat panel display devices is disclosed. The method is a way of effectively forming thin films on a substrate even if reactants do not react readily in a time-divisional process gas supply sequence in a reactor by supplying reactant gases and a purge gas cyclically and sequentially in order to prevent gas-phase reactions between the reactant gases and also by generating plasma directly on a substrate synchronously with the process gas supply cycle. The method has advantages of effective thin film formation even if the reactant gases do not react readily, minimization of the purge gas supply time for reduction in process time, reduction of particle contamination during film formation process, as well as thin film formation at low temperatures.Type: GrantFiled: December 6, 2000Date of Patent: November 11, 2003Assignee: Genitech, Inc.Inventors: Chun-Soo Lee, Won-Gu Kang, Kyu-Hong Lee, Kyoung-Soo Yi
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Patent number: 6627268Abstract: Ion-induced, UV-induced, and electron-induced sequential chemical vapor deposition (CVD) processes are disclosed where an ion flux, a flux of ultra-violet radiation, or an electron flux, respectively, is used to induce the chemical reaction in the process. The process for depositing a thin film on a substrate includes introducing a flow of a first reactant gas in vapor phase into a process chamber where the gas forms an adsorbed saturated layer on the substrate and exposing the substrate to a flux of ions, a flux of ultra-violet radiation, or a flux of electrons for inducing a chemical reaction of the adsorbed layer of the first reactant gas to form the thin film. A second reactant gas can be used to form a compound thin film. The ion-induced, UV-induced, and electron-induced sequential CVD process of the present invention can be repeated to form a thin film of the desired thickness.Type: GrantFiled: May 3, 2001Date of Patent: September 30, 2003Assignee: Novellus Systems, Inc.Inventors: James A. Fair, Wilbert van den Hoek, Nerissa Taylor
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Patent number: 6616757Abstract: A method for growing bulk GaN and AlGaN single crystal boules, preferably using a modified HVPE process, is provided. The single crystal boules typically have a volume in excess of 4 cubic centimeters with a minimum dimension of approximately 1 centimeter. If desired, the bulk material can be doped during growth to achieve n-, i-, or p-type conductivity. In order to have growth cycles of sufficient duration, preferably an extended Ga source is used in which a portion of the Ga source is maintained at a relatively high temperature while most of the Ga source is maintained at a temperature close to, and just above, the melting temperature of Ga. To grow large boules of AlGaN, preferably multiple Al sources are used, the Al sources being sequentially activated to avoid Al source depletion and excessive degradation.Type: GrantFiled: July 11, 2001Date of Patent: September 9, 2003Assignee: Technologies and Devices International, Inc.Inventors: Yuri V. Melnik, Vitali Soukhoveev, Vladimir Ivantsov, Katie Tsvetkov, Vladimir A. Dmitriev
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Patent number: 6607595Abstract: Disclosed herein are (1) a light-emitting semiconductor device that uses a gallium nitride compound semiconductor (AlXGa1-xN) in which the n-layer of n-type gallium nitride compound semiconductor (AlxGa1-XN) is of double-layer structure including an n-layer of low carrier concentration and an n+-layer of high carrier concentration, the former being adjacent to the i-layer of insulating gallium nitride compound semiconductor (AlxGa1-xN); (2) a light-emitting semiconductor device of similar structure as above in which the i-layer is of double-layer structure including an iL-layer of low impurity concentration containing p-type impurities in comparatively low concentration and an iH-layer of high impurity concentration containing p-type impurities in comparatively high concentration, the former being adjacent to the n-layer; (3) a light-emitting semiconductor device having both of the above-mentioned features and (4) a method of producing a layer of an n-type gallium nitride compound semiconductor (AlxGa1-xType: GrantFiled: October 2, 2000Date of Patent: August 19, 2003Assignees: Toyoda Gosei Co., Ltd., Kabushiki Kaisha Toyota Chuo Kenkyu sho, Nagoya University, Japan Science and Technology CorporationInventors: Katsuhide Manabe, Akira Mabuchi, Hisaki Kato, Michinari Sassa, Norikatsu Koide, Shiro Yamazaki, Masafumi Hasimoto, Isamu Akasaki
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Publication number: 20030131787Abstract: Monocrystalline diamond, adapted for use as in applications such as semiconductor devices, optical waveguides, and industrial applications, in the form of a single crystalline diamond structure having one or more diamond layers, at least one of which is formed by a CVD process. The diamond layers are “lattice-matched” or “lattice-mismatched” to each other to provide a desired level of strain.Type: ApplicationFiled: December 24, 2002Publication date: July 17, 2003Inventors: Robert C. Linares, Patrick J. Doering
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Patent number: 6592664Abstract: A method for epitaxial deposition of atoms or molecules from a reactive gas on a deposition surface of a substrate is described. The method includes the following steps: a first amount of energy is supplied by heating at least the deposition surface; and an ionized inert gas is conducted, at least from time to time, onto the deposition surface in order to supply, at least from time to time, a second amount of energy through the effect of ions of the ionized inert gas on the deposition surface. The first amount of energy is less than the energy amount necessary for the epitaxial deposition of atoms or molecules of the reactive gas on the deposition surface. A sum of the first energy amount and the second energy equaling, at least from time to time, a total amount of energy that is sufficient for the epitaxial deposition of atoms or molecules of the reactive gas onto the deposition surface.Type: GrantFiled: September 6, 2000Date of Patent: July 15, 2003Assignee: Robert Bosch GmbHInventors: Wilhelm Frey, Franz Laermer, Klaus Heyers
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Patent number: 6582513Abstract: Synthetic monocrystalline diamond compositions having one or more monocrystalline diamond layers formed by chemical vapor deposition, the layers including one or more layers having an increased concentration of one or more impurities (such as boron and/or isotopes of carbon), as compared to other layers or comparable layers without such impurities. Such compositions provide an improved combination of properties, including color, strength, velocity of sound, electrical conductivity, and control of defects. A related method for preparing such a composition is also described, as well as a system for use in performing such a method, and articles incorporating such a composition.Type: GrantFiled: May 14, 1999Date of Patent: June 24, 2003Assignee: Apollo Diamond, Inc.Inventors: Robert C. Linares, Patrick J. Doering
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Patent number: 6576053Abstract: In a method of forming a thin film using an atomic layer deposition (ALD) method, a thin film is formed on a substrate in cycles. Each cycle includes injecting a first reactant including an atom that forms the thin film and a ligand into a reaction chamber that includes the substrate, purging the first reactant, injecting a second reactant into the reaction chamber, and purging the second reactant. The thin film is formed by a chemical reaction between the atom that forms the thin film and a second reactant whose binding energy with respect to the atom that forms the thin film is larger than the binding energy of the ligand with respect to the atom that forms the thin film and the generation of by-products is prevented. The generation of a hydroxide by-product in the thin film is suppressed by using a material that does not include a hydroxide as the second reactant, purging the second reactant, and reacting the second reactant with a third reactant that includes hydroxide.Type: GrantFiled: October 6, 2000Date of Patent: June 10, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Yeong-kwan Kim, Young-wook Park, Jae-soon Lim, Sung-je Choi, Sang-in Lee
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Patent number: 6565655Abstract: A high vacuum apparatus for fabricating a semiconductor device includes a reactive chamber provided with an inlet and an outlet for a reactive gas, a suscepter installed in the reactive chamber for mounting the semiconductor thereon and a vacuum pump connected with the outlet to make the inside of the reactive chamber to put in a high vacuum state, wherein a gas injector of the reactive gas inlet is directed downward of the semiconductor device so that the initial gas flowing of the reactive gas injected from the reactive gas inlet does not directly pass the upper portion of the semiconductor substrate mounted on the suscepter. Since the reactive gas is prevented from cooling and condensing at the upper surface of the semiconductor substrate, defective proportion of the semiconductor device can be remarkably reduced.Type: GrantFiled: March 12, 2001Date of Patent: May 20, 2003Assignee: Jusung Engineering Co., Ltd.Inventors: Chul-Ju Hwang, Sung-Ryul Kim, Jae-Kyun Park
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Patent number: 6528430Abstract: An atomic layer deposition (ALD) method employing Si2Cl6 and NH3, or Si2Cl6 and activated NH3 as reactants. In one embodiment, the invention includes the steps of (a) placing a substrate into a chamber, (b) injecting a first reactant containing Si2Cl6 into the chamber, (c) chemisorbing a first portion of the first reactant onto the substrate and physisorbing a second portion of the first reactant onto the substrate, d) removing the non-chemically absorbed portion of the first reactant from the chamber, (e) injecting a second reactant including NH3 into the chamber, (f) chemically reacting a first portion of the second reactant with the chemisorbed first portion of the first reactant to form a silicon-containing solid on the substrate, and (g) removing the unreacted portion of the second reactant from the chamber. In other embodiments, the first reactant can contain two or more compounds containing Si and Cl, such as Si2Cl6 and SiCl4.Type: GrantFiled: May 1, 2001Date of Patent: March 4, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Kim Yeong Kwan, Park Young Wook, Lee Joo Won, Kim Dong Chan
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Patent number: 6527855Abstract: Cobalt thin films were prepared by atomic layer deposition (ALD). The precursor cobalt(II) acetylacetonate [Co(C5H7O2)2] was used to selectively deposit films onto iridium substrates using hydrogen reduction. Cobalt growth was observed on SiO2, silicon, fluorinated silica glass (FSG), and tantalum when silane was used as a reducing agent.Type: GrantFiled: October 10, 2001Date of Patent: March 4, 2003Assignee: Rensselaer Polytechnic InstituteInventors: Mark J. DelaRosa, Toh-Ming Lu, Atul Kumar
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Publication number: 20030037723Abstract: A method and apparatus for the high throughput epitaxial growth of a layer on the surface of a substrate by chemical vapor deposition is provided. In one embodiment, the method of the present invention comprises placing the substrate within a reactor vessel and passing a horizontal flow of reactant gas comprising a precursor chemical through the reactor vessel. The flow of the reactant gas is defined as having a Reynolds number of at least about 5000. The substrate is heated to a temperature sufficient to thermally decompose the precursor chemical and deposit an epitaxial layer on the substrate. In accordance with a preferred embodiment of the present invention, the substrate is placed within the reactor vessel at a position such that the flow of the reactant gas is characterized as a fully developed turbulent flow.Type: ApplicationFiled: November 15, 2001Publication date: February 27, 2003Applicant: MEMC Electronic Materials, Inc.Inventors: Srikanth Kommu, Gregory M. Wilson
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Patent number: 6506667Abstract: A method of growing epitaxial semiconductor layers with reduced crystallographic defects. The method includes growing a first epitaxial semiconductor layer on a semiconductor substrate under conditions of relatively high temperature and low source gas flow to heal defects in or on the surface of the substrate. Subsequently, a second epitaxial semiconductor layer is grown on the first layer under conditions of relatively low temperature and high source gas flow. The first epi layer acts as a low-defect seed layer by preventing defects in the surface of the substrate from propagating into the second epi layer. Optionally, a hydrogen chloride etch may be employed during a portion of the first epi layer growth to increase the efficacy of the first layer.Type: GrantFiled: December 11, 2000Date of Patent: January 14, 2003Assignee: SEH America, Inc.Inventors: Mark R. Boydston, Gerald R. Dietze, Oleg V. Kononchuk
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Patent number: 6485564Abstract: In a thin film forming method of the invention, an atmosphere for a base as a thin film forming target is set to a high vacuum of, e.g., 0.01 Torr or less, and a gas of an organometallic compound and an oxidizing gas are introduced onto a base surface heated to about 450° C., to form a plurality of crystal nuclei, made of an oxide of a metal constituting the organometallic compound, on the base surface. The atmosphere for the base is then set to a lower vacuum than the first vacuum degree, and the gas of the organometallic compound and the oxidizing gas are subsequently introduced onto the base surface heated to about 45° C., to form a film made of the oxide of the metal there.Type: GrantFiled: November 13, 2000Date of Patent: November 26, 2002Assignee: Tokyo Electron LimitedInventors: Yijun Liu, Hiroshi Shinriki, Takashi Magara
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Patent number: 6464778Abstract: A tungsten deposition process. A crystal growth step is carried out in a reaction chamber to form a tungsten crystal layer over a substrate using tungsten hexafluoride, silane and nitrogen as reactive gases. An intermediate step is conducted such that the supply of tungsten hexafluoride to the reaction chamber is cut but the supply of silane is continued. Furthermore, nitrogen is passed into the reaction chamber selectively. A main deposition step is finally conducted to form a tungsten layer over the tungsten crystal layer using tungsten hexafluoride, hydrogen and nitrogen as reactive gases.Type: GrantFiled: January 17, 2001Date of Patent: October 15, 2002Assignee: Promos Technologies Inc.Inventor: Wen Pin Chiu
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Patent number: 6454854Abstract: It is an object of the invention to provide a semiconductor wafer obtained by forming a semiconductor thin film with uniform resistivity on a main surface of a semiconductor single crystal substrate of 300 mm or more in diameter. When a process gas is supplied to over a main surface of a silicon single crystal substrate 12 in rotation in almost parallel to the main surface thereof in one direction in a reaction chamber 10 through six inlet ports 18a to 18f disposed in width direction of the reaction chamber 10, H2 gas, a semiconductor raw material gas and a dopant gas are supplied onto an area in the vicinity of the center of the main surface of the silicon single crystal substrate 12 and an intermediate area thereof through the inner inlet ports 18a and 18b and the middle inlet ports 18c and 18d, and only H2 gas and the semiconductor raw material gas without the dopant gas are supplied onto an area in the vicinity of the outer periphery thereof from the outer inlet ports 18e and 18f.Type: GrantFiled: June 26, 2000Date of Patent: September 24, 2002Assignee: Shin-Etsu Handotai Co., Ltd.Inventor: Hiroki Ose
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Patent number: 6447604Abstract: A III-V nitride homoepitaxial microelectronic device structure comprising a III-V nitride homoepitaxial epi layer on a III-V nitride material substrate, e.g., of freestanding character. Various processing techniques are described, including a method of forming a III-V nitride homoepitaxial layer on a corresponding III-V nitride material substrate, by depositing the III-V nitride homoepitaxial layer by a VPE process using Group III source material and nitrogen source material under process conditions including V/III ratio in a range of from about 1 to about 105, nitrogen source material partial pressure in a range of from about 1 to about 103 torr, growth temperature in a range of from about 500 to about 1250 degrees Celsius, and growth rate in a range of from about 0.1 to about 500 microns per hour. The III-V nitride homoepitaxial microelectronic device structures are usefully employed in device applications such as UV LEDs, high electron mobility transistors, and the like.Type: GrantFiled: June 28, 2000Date of Patent: September 10, 2002Assignee: Advanced Technology Materials, Inc.Inventors: Jeffrey S. Flynn, George R. Brandes, Robert P. Vaudo, David M. Keogh, Xueping Xu, Barbara E. Landini
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Patent number: RE38937Abstract: It was an objective of the present invention to provide a susceptor which can prevent a increasing phenomenon of the dopant concentration of the epitaxial layer at the peripheral portion of the wafer. By providing a through-hole 7 passing through to a rear side at the outer peripheral side of the wafer inside the wafer pocket 6, a down flow of a reacting source gas from the upper surface of the susceptor 5 is formed, so that the unwanted flow of the dopant species being exhausted at the rear surface onto the wafer surface can be avoided. As a result, a raise in the dopant concentration at the outer peripheral portion of the epitaxial layer 9 can be controlled.Type: GrantFiled: September 4, 2002Date of Patent: January 24, 2006Assignee: Sumitomo Mitsubishi Silicon CorporationInventor: Osamu Nakamura