{zn,cd,hg}{s,se,te} Compound Containing {c30b 29/46} Patents (Class 117/956)
  • Patent number: 5580382
    Abstract: An process for efficient controlled N-type silicon doping of Group III-V materials. Through the present invention silicon may be introduced into Group III-V materials at incorporation efficiencies in excess of 10.sup.-4. In a preferred embodiment doping with silicon tetrabromide attains incorporation efficiencies of approximately 0.37. Silicon incorporation efficiencies of approximately 1 should be obtained using silicon tetraiodide. The silicon dopant sources of the present invention may be used to accurately selectively produce net electron concentrations varying from approximately 1.times.10.sup.16 to 1.2.times.10.sup.20 cm.sup.-3. Favorable room temperature vapor pressures of the dopants used in accordance with the present invention allow for production of abrupt doping profiles. Additionally, high photoluminescence peak values, and low contact and sheet resistances are obtained through the present invention.
    Type: Grant
    Filed: March 27, 1995
    Date of Patent: December 3, 1996
    Assignee: Board of Trustees of the University of Illinois
    Inventors: Steven L. Jackson, Gregory E. Stillman
  • Patent number: 5549747
    Abstract: A method of producing sheets of crystalline material is disclosed, as well as devices employing such sheets. In the method, a growth mask is formed upon a substrate and crystalline material is grown at areas of the substrate exposed through the mask and laterally over the surface of the mask to form a sheet of crystalline material. This sheet is optionally separated so that the substrate can be reused. The method has particular importance in forming sheets of crystalline semiconductor material for use in solid state devices.
    Type: Grant
    Filed: April 14, 1994
    Date of Patent: August 27, 1996
    Assignee: Massachusetts Institute of Technology
    Inventors: Carl O. Bozler, John C. C. Fan, Robert W. McClelland
  • Patent number: 5492080
    Abstract: A crystal-growth method includes a process of filling three materials separately, one being selected from a group consisting of elemental Mg, MgS and MgSe compounds, and the other two being ZnSe and ZnS compounds, in their respective effusion cells, and a crystal-growth process of a Zn.sub.1-Y Mg.sub.Y S.sub.Z Se.sub.1-Z (0<Y>1 and 0<Z>1) single-crystalline thin film on a heated substrate by controlling the temperatures of the effusion cells and the molecular beam intensities.
    Type: Grant
    Filed: December 21, 1994
    Date of Patent: February 20, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuhiro Ohkawa, Tsuneo Mitsuyu
  • Patent number: 5456207
    Abstract: Triisopropylindium diisopropyltelluride adduct, ((CH.sub.3).sub.2 CH).sub.3 In:Te(CH(CH.sub.3).sub.2).sub.2 is synthesized and is used as a universal n-type dopant for both II/VI semiconductor materials as well as III/V semiconductor materials is disclosed. This dopant precursor is particularly suited for indium doping of II/V semiconductor materials at low carrier concentrations down to 10.sup.14 cm.sup.-3 and does not exhibit an appreciable memory effect.
    Type: Grant
    Filed: May 16, 1994
    Date of Patent: October 10, 1995
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Robert W. Gedridge, Jr., Ralph Korenstein, Stuart J. C. Irvine
  • Patent number: 5394826
    Abstract: A group II-VI epitaxial layer grown on a (111) silicon substrate has a lattice mismatch which is minimized, as between the group II-VI epitaxial layer and the silicon substrate. The grown group II-VI epitaxial layer also has a (111) plane at the interface with the substrate, and a 30.degree. in-plane rotation slip is formed at the interface between the (111) silicon substrate and the group II-VI epitaxial layer. The above structure is produced by a metal organic chemical vapor deposition method (MOCVD), in which a mol ratio of a group VI gas source supply to a group II gas source supply is kept greater than 15 during the growth. The (111) silicon substrate is preferably mis-oriented toward the <110> direction of the silicon substrate. When a HgCdTe layer is grown on the epitaxial layer, the product thus formed has utility as a monolithic infrared detector in which a plurality of detector elements are formed in the HgCdTe layer and a signal processing circuit is formed in the silicon substrate.
    Type: Grant
    Filed: October 22, 1993
    Date of Patent: March 7, 1995
    Assignee: Fujitsu Limited
    Inventors: Hiroji Ebe, Akira Sawada
  • Patent number: 5312506
    Abstract: There is here provided a method for growing single crystals from a melt which comprises the steps of preparing a double structure crucible constituted of an inner tube and an outer tube; placing a raw material in the inner tube; hermetically sealing the outer tube; and heating/melting the raw material to perform crystal growth.According to the present invention, it is possible to hermetically confine and to crystallize the raw material even at a high temperature.
    Type: Grant
    Filed: September 21, 1992
    Date of Patent: May 17, 1994
    Assignee: Mitsui Mining Company, Limited
    Inventor: Akira Omino