Abstract: Disclosed is a method for producing a Group III nitride compound semiconductor including a pit formation step in which a portion of an uppermost layer of a first Group III nitride compound semiconductor layer containing one or more sub-layers, the portion containing lattice defects, is subjected to treatment by use of a solution or vapor which corrodes the portion more easily than it corrodes a portion of the uppermost layer containing no lattice defects, the first Group III nitride compound semiconductor layer not being accompanied by a substrate therefor as a result of removal therefrom, or being accompanied by a substrate such that the semiconductor layer is formed with or without intervention of a buffer layer provided on the substrate; and a lateral growth step of growing a second Group III nitride compound semiconductor layer through vertical and lateral epitaxial overgrowth around nuclei as seeds for crystal growth which are on flat portions of the uppermost layer of the first Group III nitride compoun

Abstract: Selected micro- and nanoscale, 1-dimensional and 2-dimensional periodic and random structures generated on silicon and other substrates are expected to perform as compliant, thin films for gettering defects and for accommodating lattice and thermal expansion mismatches during heteroepitaxial growth thereon, thereby leading to relatively defect-free, heteroepitaxial films of chosen thicknesses. The as-grown epilayers or completed electronic and optoelectronic devices can be bonded to a second substrate such as glass, or plastic following separation thereof from the substrate on which they were formed using preferential etching of a readily detachable, nanoporous silicon or silicon dioxide layer introduced between the generated structures and the substrate.

Abstract: An object of the present invention is to provide a semiconductor light-emitting device that reduces dislocation density and has a high luminous efficiency. A semiconductor light-emitting device 20 has an underlayer 13 made of nitride semiconductor containing Al and a dislocation density of 1011/cm2 or less. The device further has an n-type conductive layer 14 and p-type conductive layer 17 each composed of nitride semiconductor having an Al content smaller than that of the nitride semiconductor constituting the underlayer and having a dislocation density of 1×1010/cm2 or less. The device still further has a light emitting layer 15 composed of nitride semiconductor having an Al content smaller than that of the nitride semiconductor constituting the underlayer and having a dislocation density of 1×1010/m2 or less, as well.

Abstract: In a method for manufacturing a crystalline silicon film by utilizing a metal element that promotes the crystallization of silicon, an influence of this metal element can be suppressed. A nickel element 104 is retained in contact with a surface of an amorphous silicon film 103 patterned to form a predetermined pattern in such a manner that the metal element is brought into contact with the amorphous silicon film 103 patterned to form a predetermined pattern. Next, the crystalline silicon film 105 is formed by a heat treatment. At this time, the nickel element is segregated in the edge region of the pattern. Further, a crystalline silicon film 100 having no region to which the metal element concentrated by patterning using a mask 107. By using this crystalline silicon film 100 as an active layer, the thin film transistor is fabricated.

Abstract: A process for forming an epitaxial layer on a semiconductor wafer substrate is provided. The process comprises providing a semiconductor wafer substrate and an area for forming an epitaxial layer on said semiconductor wafer substrate. The formation area consists essentially of an epitaxial layer process chamber. The semiconductor wafer substrate is introduced into the epitaxial layer process chamber and an epitaxial layer is formed on at least one surface of the semiconductor wafer substrate. At least one epitaxial layer surface is substantially hydrophobic. Then, a chemical reagent is introduced into said epitaxial layer process chamber. The chemical reagent reacts with the epitaxial layer surface in situ to form an outer layer.

Abstract: A process for producing an epitaxial layer of gallium nitride (GaN). A film of a dielectric whose thickness is about one monolayer is formed on a surface of a substrate. A continuous gallium nitride layer is then deposited on the dielectric film at a temperature sufficiently low to suppress island formation of the gallium nitride. The deposited gallium nitride layer is annealed at a temperature sufficiently high to promote island formation of the gallium nitride. An epitaxial regrowth with gallium nitride at the end of a spontaneous in situ formation of islands of gallium nitride then takes place. This method makes it possible to avoid having to use ex situ etching of masks by photolitographiy or chemical ethching techniques.

Abstract: The present invention is related to a method that enables and improves wide bandgap homoepitaxial layers to be grown on axis single crystal substrates, particularly SiC. The lateral positions of the screw dislocations in epitaxial layers are predetermined instead of random, which allows devices to be reproducibly patterned to avoid performance degrading crystal defects normally created by screw dislocations.

Abstract: The present invention provides methods of manufacturing and integrating optical devices. In one embodiment, a method of integrating an optical device may include forming a first device over a substrate, and forming a second device over the substrate and adjacent the first device with a deposition gas having an etchant selective to a deposited component of the deposition gas.

Abstract: To provide a method of manufacturing compound semiconductor single crystals such as silicon carbide and gallium nitride by epitaxial growth methods, that is capable of yielding compound single crystals of comparatively low planar defect density. The method of manufacturing compound single crystals in which two or more compound single crystalline layers identical to or differing from a single crystalline substrate are sequentially epitaxially grown on the surface of said substrate. At least a portion of said substrate surface has plural undulations extending in a single direction and second and subsequent epitaxial growth is conducted after the formation of plural undulations extending in a single direction in at least a portion of the surface of the compound single crystalline layer formed proximately.

Abstract: A method of fabricating a high-density magnetic data-storage medium, the method comprising the steps of: (a) forming a plurality of nanodots of non-magnetic material in a regular array on a surface of a substrate, said array being notionally dividable into a plurality of clusters that each comprise a plurality of nanodots, wherein each nanodot of a said cluster overlaps with neighbouring nanodots of that cluster to form a well between them; (b) depositing magnetic material onto said substrate to at least partly fill the wells of each cluster; and (c) removing material to reveal a regular array of wells filled with magnetic material, each of said wells being separated from neighbouring wells by non-magnetic material.

Abstract: In a process for producing a substrate for use in a semiconductor element: a porous anodic alumina film having a great number of minute pores is formed on a surface of a base substrate; the surface of the base substrate is etched by using the porous anodic alumina film as a mask so as to form a great number of pits on the surface of the base substrate; the porous anodic alumina film is removed; and a GaN layer is formed on the surface of the base substrate by crystal growth.

Abstract: Methods for producing silicon carbide crystals, seed crystal holders and seed crystal for use in producing silicon carbide crystals and silicon carbide crystals are provided. Silicon carbide crystals are produced by forcing nucleation sites of a silicon carbide seed crystal to a predefined pattern and growing silicon carbide utilizing physical vapor transport (PVT) so as to provide selective preferential growth of silicon carbide corresponding to the predefined pattern. Seed holders and seed crystals are provided for such methods. Silicon carbide crystals having regions of higher and lower defect density are also provided.

Abstract: Methods of forming an electrically conductive line include providing a stress inducing material within or a compressive stress inducing layer, operatively adjacent a crystalline material of a first crystalline phase. In addition, such methods include annealing the crystalline material of the first crystalline phase under conditions effective to transform it to a second crystalline phase. Some methods also include providing stress inducing materials into a refractory metal layer. Example compressive stress inducing layers include SiO2 and Si3N4, while example stress inducing materials include Ge, W and Co. Where the compressive stress inducing material is provided on the same side of a wafer over which the crystalline phase material is provided, it is provided to have a thermal coefficient of expansion which is less than the first phase crystalline material. Example and preferred crystalline phase materials having two phases are refractory metal silicides, such as TiSix.

Abstract: A method utilizes sputter transport techniques to produce arrays or layers of self-forming, self-oriented columnar structures characterized as discrete, single-crystal Group III nitride posts or columns on various substrates. The columnar structure is formed in a single growth step, and therefore does not require processing steps for depositing, patterning, and etching growth masks. A Group III metal source vapor is produced by sputtering a target, for combination with nitrogen supplied from a nitrogen-containing source gas. The III/V ratio is adjusted or controlled to create a Group III metal-rich environment within the reaction chamber conducive to preferential column growth. The reactant vapor species are deposited on the growth surface to produce single-crystal MIIIN columns thereon. The columns can be employed as a strain-relieving platform for the growth of continuous, low defect-density, bulk materials.

Abstract: A SiGe monocrystalline etch-stop material system on a monocrystalline silicon substrate. The etch-stop material system can vary in exact composition, but is a doped or undoped Si1−xGex alloy with x generally between 0.2 and 0.5. Across its thickness, the etch-stop material itself is uniform in composition. The etch stop is used for micromachining by aqueous anisotropic etchants of silicon such as potassium hydroxide, sodium hydroxide, lithium hydroxide, ethylenediamine/pyrocatechol/pyrazine (EDP), TMAH, and hydrazine. These solutions generally etch any silicon containing less than 7×1019 cm−3 of boron or undoped Si1−xGex alloys with x less than approximately 18. Alloying silicon with moderate concentrations of germanium leads to excellent etch selectivities, i.e., differences in etch rate versus pure undoped silicon. This is attributed to the change in energy band structure by the addition of germanium.

Abstract: A device substrate is provided having: a Si(111) substrate; a buffer layer formed by epitaxial growth on the Si(111) substrate 11, and containing at least one of a rare earth metal oxide and an alkali earth metal oxide; and a semiconductor material layer formed by epitaxial growth on the buffer layer, and containing at least one of a group II-VI semiconductor material having a wurtzite structure and a group III-V semiconductor material having a wurtzite structure. The buffer layer preferably comprises a hexagonal crystal structure oriented in the (001) plane or a cubic crystal structure oriented in the (111) plane, and the semiconductor material layer preferably comprises a hexagonal crystal structure oriented in the (001) plane.

Abstract: A thick GaN layer is grown on sapphire through an Au layer at a temperature lower than the melting point of 1064° C. of the Au layer, and temperature of a sample is raised to reach and exceed the melting point of the Au layer so that the Au layer is dissolved. In this state, the sapphire and GaN layer are separated from each other.

Abstract: In the method of forming fine patterns of a semiconductor integrated circuit, a mask layer is formed over a semiconductor structure having a first region and a second region. A portion of the mask layer over the first region is removed to expose the semiconductor structure, and sacrificial layer patterns are formed over the exposed semiconductor structure. Then, spacers are formed on sidewalls of the sacrificial layer patterns and the mask layer, and portions of the spacers are removed to create fine mask patterns. The semiconductor structure is then patterned using the fine mask patterns to create fine patterns.

Abstract: A method of single crystal welding is provided for the production of a single crystal region (1) on a surface (2) of a moncrystalline substrate (3) by means of an energy beam (4). The method of single crystal welding includes the supply of a coating material (5), the formation of a melt (6) by melting the coating material (5) by means of the energy beam (4) and the melting of a surface layer (71, 72) of the single crystal substrate (3) by the energy beam (4). The characteristic (8) of the energy distribution in the energy beam (4) is set, in this connection, such that the lateral thermal flow (H1) from the melt into the single crystal substrate (3) is minimised.

Abstract: A method for the production of a semiconductor wafer having a front and a back and an epitaxial layer of semiconductor material deposited on the front, includes the following process steps: (a) preparing a substrate wafer having a polished front and a specific thickness; (b) pretreating the front of the substrate wafer in the presence of HCl gas and a silane source at a temperature of from 950 to 1250 degrees Celsius in an epitaxy reactor, the thickness of the substrate wafer remaining substantially unchanged; and (c) depositing the epitaxial layer on the front of the pretreated substrate wafer.

Abstract: A film (carbon and/or diamond) for a field emitter device, which may be utilized within a computer display, is produced by a process utilizing treatment of a substrate and then depositing the film. The treatment step creates nucleation and growth sites on the substrate for the film deposition process and promotes election emission of the deposited film. With this process, a patterned emission can be achieved without post-deposition processing of the film. A field emitter device can be manufactured with such a film.

Abstract: Selected micro- and nanoscale, 1-dimensional and 2-dimensional periodic and random structures generated on silicon and other substrates are expected to perform as compliant, thin films for gettering defects and for accommodating lattice and thermal expansion mismatches during heteroepitaxial growth thereon, thereby leading to relatively defect-free, heteroepitaxial films of chosen thicknesses. The as-grown epilayers or completed electronic and optoelectronic devices can be bonded to a second substrate such as glass, or plastic following separation thereof from the substrate on which they were formed using preferential etching of a readily detachable, nanoporous silicon or silicon dioxide layer introduced between the generated structures and the substrate.

Abstract: The present invention provides for a method of manufacturing a Group III-V compound semiconductor, which grows a nitrogen-contained Group III-V compound semiconductor of the p-type conductivity, without performing any particular post-processing after growing the compound semiconductor, and which prevents a deterioration in the yield of manufacturing light emitting elements due to post-processing. A first embodiment is directed to a method of manufacturing a Group III-V compound semiconductor which contains p-type impurities and which is expressed by a general formula InxGayAlzN (0≧x≧1,0≧z≧1, x+y+z=1), by thermal decomposition vapor phase method using metalorganics, the method being characterized in that carrier gas is inert gas in which the concentration of hydrogen is 0.5 % or smaller by volume.

Abstract: A process of growing a material on a substrate, particularly growing a Group II-VI or Group III-V material, by a vapor-phase growth technique where the growth process eliminates the need for utilization of a mask or removal of the substrate from the reactor at any time during the processing. A nucleation layer is first grown upon which a middle layer is grown to provide surfaces for subsequent lateral cantilever growth. The lateral growth rate is controlled by altering the reactor temperature, pressure, reactant concentrations or reactant flow rates. Semiconductor materials, such as GaN, can be produced with dislocation densities less than 107/cm2.

Abstract: A boule formed by high rate vapor phase growth of Group III-V nitride boules (ingots) on native nitride seeds, from which wafers may be derived for fabrication of microelectronic device structures. The boule is of microelectronic device quality, e.g., having a transverse dimension greater than 1 centimeter, a length greater than 1 millimeter, and a top surface defect density of less than 107 defects cm−2. The Group III-V nitride boule may be formed by growing a Group III-V nitride material on a corresponding native Group III-V nitride seed crystal by vapor phase epitaxy at a growth rate above 20 micrometers per hour.

Abstract: In a process of producing a SiC device, a Si layer is formed on the surface of a SiC substrate, and the Si layer is removed from the surface of the SiC substrate by supplying oxygen gas to the Si layer in a high ambient temperature and a low ambient pressure. The pressure is set at 1×10−2 to 1×10−6 Pa. Thus a cleaned surface of the SiC substrate, not contaminated by carbon and the like in atmospheric air, can be provided. Preferably, the oxygen pressure and temperature are set at about 10−6 Pa and 1000° C. for removing the Si layer. Thereafter, the oxygen is further supplied to raise the pressure to about 104 Pa to form an oxide film on the cleaned SiC substrate. Thus, the SiC substrate is cleaned and then formed with the oxide layer in the same chamber by changing the ambient pressure but without changing the ambient temperature.

Abstract: Provided is a compound semiconductor single crystal and a fabrication process for a compound semiconductor device capable of forming a prescribed pattern without requirement of many steps. A group V element component in a III-V compound semiconductor single crystal or a group VI element component in the II-VI compound semiconductor single crystal is reduced less than a composition ratio expressed by a chemical formula of a corresponding compound semiconductor single crystal in a pattern-shaped portion.

Abstract: A process for forming an epitaxial layer on a semiconductor wafer substrate is provided. The process comprises providing a semiconductor wafer substrate and an area for forming an epitaxial layer on said semiconductor wafer substrate. The formation area consists essentially of an epitaxial layer process chamber. The semiconductor wafer substrate is introduced into the epitaxial layer process chamber and an epitaxial layer is formed on at least one surface of the semiconductor wafer substrate. Then, a chemical reagent is introduced into the epitaxial layer process chamber. The chemical reagent reacts with the epitaxial layer surface in situ to form an outer protective oxide layer.

Abstract: An apparatus for depositing a semiconductor film on a wafer, which is held on a holder inside a reactor, with at least one source gas supplied onto the wafer. The apparatus includes a decontamination film made of a semiconductor that contains at least one constituent element of the semiconductor film to be deposited. The decontamination film covers inner walls of the reactor, which are located upstream with respect to the source gas supplied and/or over the holder.

Abstract: A method for making an array of thin single-crystal substrates on a handle substrate comprising the steps: attaching a plurality of single-crystal substrates to a face of a support wafer; polishing said plurality of attached single-crystal substrates so that said single-crystal substrates surfaces are coplanar on said support surface and to a selected surface roughness; implanting a hydrogen to a selected depth into said attached single-crystal substrates; bonding said polished and hydrogen implanted attached single-crystal substrates to a first handle substrate; and splitting said polished and hydrogen implanted attached single-crystal substrates at said selected depth thereby forming an array of thin single-crystal substrates on said first handle substrate and a support wafer having a remaining portion of said attached single-crystal substrates.

Abstract: A process for forming an epitaxial layer on a semiconductor wafer substrate is provided. The process comprises providing a semiconductor wafer substrate and an area for forming an epitaxial layer on said semiconductor wafer substrate. The formation area consists essentially of an epitaxial layer process chamber. The semiconductor wafer substrate is introduced into the epitaxial layer process chamber and an epitaxial layer is formed on at least one surface of the semiconductor wafer substrate. Then, a chemical reagent is introduced into the epitaxial layer process chamber. The chemical reagent reacts with the epitaxial layer surface in situ to form an outer protective oxide layer.

Abstract: The Group III-V compound semiconductor manufacturing method which pertains to the present invention is a semiconductor manufacturing method employing epitaxy which comprises (a) a step in which growing areas are produced using a mask patterned on a substrate surface and (b) a step in which a Group III-V compound semiconductor layer is grown in the growing areas while forming facet structures. As epitaxy is continued, adjacent facet structures come into contact so that the surface of the semiconductor layer becomes planarized. Since lattice defects extend towards the facet structures, they do not extend towards the surface of the semiconductor layer. Accordingly, the number of lattice defects in the vicinity of the semiconductor layer surface is reduced.

Abstract: A method of making a Schottky diode comprising the steps of: providing a single crystal diamond comprising a surface; placing the single crystal diamond in a CVD system; heating the diamond to a temperature of at least about 950° C.; providing a gas mixture capable of growing diamond film and comprising a sulfur compound through the CVD system; growing an epitaxial diamond film on the surface of the single crystal diamond; baking the diamond at a temperature of at least about 650° C. in air for a period of time that minimizes oxidation of the diamond; and fabricating a Schottky diode comprising the diamond film. A Schottky diode comprising an epitaxial diamond film and capable of blocking at least about 6 kV in a distance of no more than about 300 &mgr;m.

Abstract: The invention concerns a method which consists in: (a) stabilization of the monocrystalline silicon substrate temperature at a first predetermined temperature T1 of 400 to 500° C.; (b) chemical vapour deposition (CVD) of germanium at said first predetermined temperature T1 until a base germanium layer is formed on the substrate, with a predetermined thickness less than the desired final thickness; (c) increasing the CVD temperature from said first predetermined temperature T1 up to a second predetermined temperature T2 of 750 to 850° C.; and (d) carrying on with CVD of germanium at said second predetermined temperature T2 until the desired final thickness for the monocrystalline germanium final layer is obtained. The invention is useful for making semiconductor devices.

Abstract: A method for changing the surface termination of a perovskite substrate surface, an example of which is the conversion of B-site terminations of a single-crystal STO substrate to A-site terminations. The method generally comprises the steps of etching the substrate surface by applying a reactive plasma thereto in the presence of fluorine or another halogen, and then annealing the substrate at a temperature sufficient to regenerate a long range order of the surface, i.e., the surface termination contributes to a better long range order in a film epitaxially grown on the surface. More particularly, the resulting substrate surfaces predominantly contains A-site surface terminations, i.e., SrO for STO (100) substrates. As a result, disadvantages associated with B-site terminated perovskite substrate surfaces are avoided. A suitable etching treatment is a low power oxygen ashing in the presence of low halogen levels.

Abstract: A SiGe monocrystalline etch-stop material system on a monocrystalline silicon substrate. The etch-stop material system can vary in exact composition, but is a doped or undoped Si1−xGex alloy with x generally between 0.2 and 0.5. Across its thickness, the etch-stop material itself is uniform in composition. The etch stop is used for micromachining by aqueous anisotropic etchants of silicon such as potassium hydroxide, sodium hydroxide, lithium hydroxide, ethylenediamine/pyrocatechol/pyrazine (EDP), TMAH, and hydrazine. For example, a cantilever can be made of this etch-stop material system, then released from its substrate and surrounding material, i.e., “micromachined”, by exposure to one of these etchants. These solutions generally etch any silicon containing less than 7×1019 cm−3 of boron or undoped Si1−xGex alloys with x less than approximately 18. Alloying silicon with moderate concentrations of germanium leads to excellent etch selectivities, i.e.

Abstract: A method for making a free-standing, single crystal, gallium nitride (GaN) wafer includes forming a single crystal GaN layer directly on a single crystal LiAlO2 substrate using a gallium halide reactant gas, and removing the single crystal LiAlO2 substrate from the single crystal GaN layer to make the free-standing, single crystal GaN wafer. Forming the single crystal GaN layer may comprise depositing GaN by vapor phase epitaxy (VPE) using the gallium halide reactant gas and a nitrogen-containing reactant gas. Because gallium halide is used as a reactant gas rather than a metal organic reactant such as trimethygallium (TMG), the growth of the GaN layer can be performed using VPE which provides commercially acceptable rapid growth rates. In addition, the GaN layer is also devoid of carbon throughout. Because the GaN layer produced is high quality single crystal, it may have a defect density of less than about 107 cm−2.

Abstract: A thick GaN layer is grown on sapphire through an Au layer at a temperature lower than the melting point of 1064° C. of the Au layer, and temperature of a sample is raised to reach and exceed the melting point of the Au layer so that the Au layer is dissolved. In this state, the sapphire and GaN layer are separated from each other.

Abstract: An epitaxial semiconductor wafer having a wafer substrate made of semiconductor single crystal, an epitaxial layer deposited on a top surface of said wafer substrate and a polysilicon layer deposited on a back surface of said wafer substrate. The semiconductor single crystal is exposed in a region defined within a distance of at least 50 &mgr;m from a ridge line as a center, which is defined as an intersection line between said back surface and a bevel face interconnecting said top surface and said back surface of said wafer substrate. The polysilicon layer is 1.0 to 2.0 &mgr;m thick. The epitaxial layer is 1.0 to 20 &mgr;m thick. The wafer substrate is a silicon single crystal.

Abstract: Disclosed is a method for forming a contact plug using a two-step epitaxial silicon growth process in which a first portion of epitaxial silicon is grown as single crystal silicon and the remainder of the contact plug is grown as polycrystalline or amorphous silicon. Preferably, the epitaxial silicon is grown using a LPCVD process at a temperature of 550° C. to 700° C. on a portion of the silicon substrate exposed at the bottom of a contact hole formed in an insulating layer, after the exposed portion of the silicon substrate has been cleaned and baked under H2, with the epitaxial single crystal silicon covering the entire exposed portion of the silicon substrate, thereby reducing contact resistance and improving reliability.

Abstract: The method of the invention for producing a Group III nitride compound semiconductor, employing an etchable substrate which is produced from a material other than the Group III nitride compound semiconductor, includes stacking one or more layers of the Group III nitride compound semiconductor on one face of the substrate and etching the other face of the substrate while stacking one or more semiconductor layers or after completion of stacking one or more semiconductor layers, to thereby reduce the thickness of most of the substrate. The apparatus of present invention for producing a semiconductor through vapor phase growth, contains a substrate for vapor-phase-growing the semiconductor; a source-supplying system for supplying a source for vapor phase growth of the semiconductor; and an etchant-supplying system, wherein the source-supplying system and the etchant-supplying system are isolated through placement of the substrate.

Abstract: To economically and easily fabricate a single crystal silicon carbide thin film. The apparatus for fabricating a single crystal silicon carbide thin film comprises a film-formation chamber 200 adapted to receive a SOI substrate 100 for film-formation, a gas supply means 300 for supplying various gases G1 to G4 necessary to fabricate a single crystal silicon carbide thin film to the film-formation chamber 200, a gas treatment means 500 for treating argon gas as an inert gas G1, propane gas as a hydrocarbon-based gas G2, hydrogen gas as a carrier gas, and oxygen gas G4 supplied to the film-formation chamber 200, and a temperature control means 400 for controlling the temperature of the film-formation chamber 200.

Abstract: The invention provides a process for growing UV region <200 nm transmitting calcium fluoride monocrystals, which includes crystallization from the melt, the annealing of the crystals and subsequent cooling, in a vacuum furnace, and which is effected by the continuous transfer of the crucible containing the melt from the crystallization zone into the annealing zone, each of these two zones having its own independent control system for the process parameters, characterized in that there is a temperature drop of 250-450° C. from the crystallization zone to the annealing zone, with a gradient of 8-12° C./cm, the crucible containing the material to be crystallized is moved from the crystallization zone to the annealing zone at a speed of 1-3 mm/hour, it is first kept in the annealing zone at a holding temperature of 1100-1300° C. for 20-40 hours and is then cooled first to 950-900° C. at a rate of 2-40 C./hour and then to 300° C. at a rage of 5-8° C.

Abstract: A high quality wafer comprising AlxGayInzN, wherein 0<y≦1 and x+y+z=1, characterized by a root mean square surface roughness of less than 1 nm in a 10×10 &mgr;m2 area at its Ga-side. Such wafer is chemically mechanically polished (CMP) at its Ga-side, using a CMP slurry comprising abrasive particles, such as silica or alumina, and an acid or a base. The process of fabricating such high quality AlxGayInzN wafer may include steps of lapping, mechanical polishing, and reducing internal stress of said wafer by thermal annealing or chemical etching for further enhancement of its surface quality. The CMP process is usefully employed to highlight crystal defects on the Ga-side of the AlxGayInzN wafer.

Abstract: A thick GaN layer is grown on sapphire through an Au layer at a temperature lower than the melting point of 1064° C. of the Au layer, and temperature of a sample is raised to reach and exceed the melting point of the Au layer so that the Au layer is dissolved. In this state, the sapphire and GaN layer are separated from each other.

Abstract: A process for forming an epitaxial layer on a semiconductor wafer substrate is provided. The process comprises providing a semiconductor wafer substrate and an area for forming an epitaxial layer on said semiconductor wafer substrate. The formation area consists essentially of an epitaxial layer process chamber. The semiconductor wafer substrate is introduced into the epitaxial layer process chamber and an epitaxial layer is formed on at least one surface of the semiconductor wafer substrate. At least one epitaxial layer surface is substantially hydrophobic. Then, a chemical reagent is introduced into said epitaxial layer process chamber. The chemical reagent reacts with the epitaxial layer surface in situ to form an outer layer.

Abstract: A GaN single crystal is grown by synthesizing GaN in vapor phase, piling a GaN crystal on a substrate, producing a three-dimensional facet structure including facets in the GaN crystal without making a flat surface, maintaining the facet structure without burying the facet structure, and reducing dislocations in the growing GaN crystal. The facet structure reduces the EPD down to less than 106 cm−2.

Abstract: AFM/STM probes are based on whiskers grown by the vapor-liquid-solid (VLS) mechanism. Silicon cantilevers oriented along the crystallographic plane (111) are prepared from silicon-on-insulator structures that contain a thin layer (111) on a (100) substrate with SiO2 interposed layer. At removal of solidified alloy globules inherent in the growth mechanism sharpening of the whiskers takes place and, in such a way, the probes are formed. Cross-sections of the wiskers grown by the mechanism on the cantilevers can be controllably changed during the growth process so that step-shaped whiskers optimal for fabrication of the probes can be prepared. Also, whiskers with expansions/contractions can be formed that are important for fabrication of probes suitable for investigations in coarse surfaces, complicated cavitites, grooves typical for semiconductor microelectronics, etc.

Abstract: By forming a silicon single-crystal thin film direct on a chemically etched substrate, a time required for all the process can be effectively shortened, which largely contributes to reduction in production cost of a silicon epitaxial wafer and improvement on production efficiency thereof, with the result that a reduced wafer price at a user's end and a short delivery time are ensured. In a technical aspect, an etching removal in a chemical etching treatment is set to be 60 &mgr;m or more and thereby, a glossiness of a front main surface of a chemically etched substrate can be ensured to be 95% or higher. With such a glossiness of the front main surface of the substrate employed, a surface glossiness of a silicon single-crystal thin film formed on the front main surface of the chemically etched substrate can be increased to 95% or higher, thereby, enabling an auto-alignment treatment in a lithographic step coming later with no trouble.

Abstract: A nitride-based semiconductor element having superior mass productivity and excellent element characteristics is obtained. This nitride-based semiconductor element comprises a substrate comprising a surface having projection portions, a mask layer formed to be in contact with only the projection portions of the surface of the substrate, a first nitride-based semiconductor layer formed on recess portions of the substrate and the mask layer and a nitride-based semiconductor element layer, formed on the first nitride-based semiconductor layer, having an element region. Thus, the first nitride-based semiconductor layer having low dislocation density is readily formed on the projection portions of the substrate and the mask layer through the mask layer serving for selective growth.