With Contiguous Layer Doped To Degeneracy Patents (Class 148/33.1)
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Patent number: 9909058Abstract: Provided are a phosphor, a phosphor manufacturing method, and a white light emitting device. The phosphor is represented as a chemical formula of aMO-bAl2O3-cSi3N4, which uses light having a peak wavelength in a wavelength band of about 350 nm to about 480 nm as an excitation source to emit visible light having a peak wavelength in a wavelength band of about 480 nm to about 680 nm (where M is one kind or two kinds of elements selected from Mg, Ca, Sr, and Ba (0.2?a/(a+b)?0.9, 0.05?b/(b+c)?0.85, 0.4?c/(c+a)?0.9)).Type: GrantFiled: September 2, 2010Date of Patent: March 6, 2018Assignee: LG INNOTEK CO., LTD.Inventors: Jae Soo Yoo, Kyung Pil Kim, Hyun Ju Lee, Chang Soo Kim
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Patent number: 9530932Abstract: A nitride semiconductor light-emitting device has a first conductive-type nitride semiconductor layer, a superlattice layer provided on the first conductive-type nitride semiconductor layer, an active layer provided on the superlattice layer, and a second conductive-type nitride semiconductor layer provided on the active layer. An average carrier concentration of the superlattice layer is higher than an average carrier concentration of the active layer.Type: GrantFiled: May 26, 2015Date of Patent: December 27, 2016Assignee: Sharp Kabushiki KaishaInventors: Mayuko Fudeta, Satoshi Komada, Ryu Kaihara
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Patent number: 9401403Abstract: A nitride semiconductor structure of the present disclosure comprises a semiconductor substrate, and a layer formed over the semiconductor substrate and comprising plural nitride semiconductor layers. The semiconductor substrate has, from a side thereof near the layer comprising the plural nitride semiconductor layers, a surface region and an internal region in this order. The surface region has a resistivity of 0.1 ?cm or more, and the internal region has a resistivity of 1000 ?cm or more.Type: GrantFiled: March 2, 2015Date of Patent: July 26, 2016Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hidekazu Umeda, Masahiro Ishida, Tetsuzo Ueda, Daisuke Ueda
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Patent number: 9340871Abstract: Low scatter water clear zinc sulfide with reduced metal contamination is prepared by coating a chuck which holds zinc sulfide and machining the zinc sulfide with uncoated particles. An inert foil is cleaned with an acid cleaning method and also cleaning the zinc sulfide. The zinc sulfide is wrapped in the inert foil and then treated by a HIP process to provide a low scatter water-clear zinc sulfide. The low scatter water-clear zinc sulfide may be used in articles such as windows and domes.Type: GrantFiled: October 1, 2015Date of Patent: May 17, 2016Inventors: Jitendra Goela, Nathaniel Brese
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Patent number: 9070805Abstract: A nitride semiconductor light-emitting device has a first conductive-type nitride semiconductor layer, a superlattice layer provided on the first conductive-type nitride semiconductor layer, an active layer provided on the superlattice layer, and a second conductive-type nitride semiconductor layer provided on the active layer. An average carrier concentration of the superlattice layer is higher than an average carrier concentration of the active layer.Type: GrantFiled: June 26, 2012Date of Patent: June 30, 2015Assignee: Sharp Kabushiki KaishaInventors: Mayuko Fudeta, Satoshi Komada, Ryu Kaihara
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Patent number: 7534310Abstract: A low dislocation density GaN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing a GaN crystal on a facet-growth condition, forming repetitions of parallel facet hills and facet valleys rooted upon the mask stripes, maintaining the facet hills and facet valleys, producing voluminous defect accumulating regions (H) accompanying the valleys, yielding low dislocation single crystal regions (Z) following the facets, making C-plane growth regions (Y) following flat tops between the facets, gathering dislocations on the facets into the valleys by the action of the growing facets, reducing dislocations in the low dislocation single crystal regions (Z) and the C-plane growth regions (Y), and accumulating the dislocations in cores (S) or interfaces (K) of the voluminous defect accumulating regions (H).Type: GrantFiled: May 17, 2006Date of Patent: May 19, 2009Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kensaku Motoki, Ryu Hirota, Takuji Okahisa, Seiji Nakahata
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Patent number: 7097718Abstract: Epitaxial wafers comprising a single crystal silicon substrate comprising agglomerated vacancy defects and having an axially symmetric region in which silicon self-interstitials are the predominant intrinsic point defect and which is substantially free of agglomerated defects, and an epitaxial layer which is deposited upon a surface of the substrate and which is substantially free of grown-in defects caused by the presence of agglomerated intrinsic point defects on the substrate surface upon which the epitaxial layer is deposited.Type: GrantFiled: May 20, 2003Date of Patent: August 29, 2006Assignee: MEMC Electronic Materials, Inc.Inventors: Luciano Mule'Stagno, Lu Fei, Joseph C. Holzer, Harold W. Korb, Robert J. Falster
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Publication number: 20030176003Abstract: A wide bandgap semiconductor material is heavily doped to a degenerate level. Impurity densities approaching 1% of the volume of the semiconductor crystal are obtained to greatly increase conductivity. In one embodiment, a layer of AlGaN is formed on a wafer by first removing contaminants from a MBE machine. Wafers are then outgassed in the machine at very low pressures. A nitride is then formed on the wafer and an AlN layer is grown. The highly doped GaAlN layer is then formed having electron densities beyond 1×1020 cm−3 at Al mole fractions up to 65% are obtained.Type: ApplicationFiled: May 15, 2002Publication date: September 18, 2003Inventors: William J. Schaff, Jeonghyun Hwang
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Patent number: 6596095Abstract: A single crystal silicon wafer with a back surface free of an oxide seal and substantially free of a chemical vapor deposition process induced halo and an epitaxial silicon layer on the front surface, the epitaxial layer is characterized by an axially symmetric region extending radially outwardly from the central axis of the wafer toward the circumferential edge of the wafer having a substantially uniform resistivity, the radius of the axially symmetric region being at least about 80% of the length of the radius of the wafer.Type: GrantFiled: December 29, 2000Date of Patent: July 22, 2003Assignee: MEMC Electronic Materials, Inc.Inventors: Michael J. Ries, Charles Chiun-Chieh Yang, Robert W. Standley
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Patent number: 6565649Abstract: The present invention is directed to an epitaxial wafer comprising a single crystal silicon substrate having an axially symmetric region in which silicon self-interstitials are the predominant intrinsic point defect and which is substantially free of agglomerated defects, and an epitaxial layer which is deposited upon a surface of the substrate and which is substantially free of grown-in defects caused by the presence of agglomerated silicon self-interstitial defects on the substrate surface upon which the epitaxial layer is deposited.Type: GrantFiled: June 5, 2001Date of Patent: May 20, 2003Assignee: MEMC Electronic Materials, Inc.Inventors: Luciano Mule′Stagno, Lu Fei, Joseph C. Holzer, Harold W. Korb, Robert J. Falster
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Patent number: 6521041Abstract: A SiGe monocrystalline etch-stop material system on a monocrystalline silicon substrate. The etch-stop material system can vary in exact composition, but is a doped or undoped Si1−xGex alloy with x generally between 0.2 and 0.5. Across its thickness, the etch-stop material itself is uniform in composition. The etch stop is used for micromachining by aqueous anisotropic etchants of silicon such as potassium hydroxide, sodium hydroxide, lithium hydroxide, ethylenediamine/pyrocatechol/pyrazine (EDP), TMAH, and hydrazine. For example, a cantilever can be made of this etch-stop material system, then released from its substrate and surrounding material, i.e., “micromachined”, by exposure to one of these etchants. These solutions generally etch any silicon containing less than 7×1019 cm−3 of boron or undoped Si1−xGex alloys with x less than approximately 18. Alloying silicon with moderate concentrations of germanium leads to excellent etch selectivities, i.e.Type: GrantFiled: April 9, 1999Date of Patent: February 18, 2003Assignee: Massachusetts Institute of TechnologyInventors: Kenneth C. Wu, Eugene A. Fitzgerald, Jeffrey T. Borenstein
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Patent number: 6379472Abstract: The present invention comprises growing gallium nitride films in the presence of bismuth using MBE at temperatures of about 1000 K or less. The present invention further comprises the gallium nitride films fabricated using the inventive fabrication method. The inventive films may be doped with magnesium or other dopants. The gallium nitride films were grown on sapphire substrates using a hollow anode Constricted Glow Discharge nitrogen plasma source. When bismuth was used as a surfactant, two-dimensional gallium nitride crystal sizes ranging between 10 &mgr;m and 20 &mgr;m were observed. This is 20 to 40 times larger than crystal sizes observed when GaN films were grown under similar circumstances but without bismuth. It is thought that the observed increase in crystal size is due bismuth inducing an increased surface diffusion coefficient for gallium. The calculated value of 4.7×10−7 cm2/sec. reveals a virtual substrate temperature of 1258 K which is 260 degrees higher than the actual one.Type: GrantFiled: November 10, 2000Date of Patent: April 30, 2002Assignee: The Regents of the University of CaliforniaInventors: Christian K. Kisielowski, Michael Rubin
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Patent number: 6284039Abstract: The present invention is directed to a set of epitaxial silicon wafers assembled in a wafer cassette, boat or other wafer carrier. Each wafer comprises a single crystal silicon substrate having an axially symmetric region in which silicon self-interstitials are the predominant intrinsic point defect and which is substantially free of agglomerated defects, and an epitaxial layer which is deposited upon a surface of the substrate and which is substantially free of grown-in defects caused by the presence of agglomerated silicon self-interstitial defects on the substrate surface upon which the epitaxial layer is deposited.Type: GrantFiled: October 13, 1999Date of Patent: September 4, 2001Assignee: MEMC Electronic Materials, Inc.Inventors: Luciano Mule'Stagno, Lu Fei, Joseph C. Holzer, Harold W. Korb, Robert J. Falster
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Publication number: 20010014515Abstract: A method of preparing a semiconductor wafer includes the step of forming first and second layers of a first material on opposing respective first and second faces of the semiconductor wafer. The second layer of the first material is then removed from the second face of the semiconductor wafer. More particularly, the first material can be polysilicon. Warping of the semiconductor wafer can thus be reduced.Type: ApplicationFiled: November 29, 1999Publication date: August 16, 2001Inventors: MIN-SEOK HA, JIN-KEE CHOI, CHEOL JEONG
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Patent number: 6193813Abstract: A method of processing a substrate, such as a semiconductor wafer, in a vacuum processing chamber includes the steps of depositing a material on a surface of the substrate using a gas mixture, and purging the chamber of residual gases by flowing SiH4 into the chamber. Preferably, WSix is deposited on a semiconductor wafer using a mixture comprising WF6, dichlorosilane and a noble gas, and the chamber is subsequently purged of residual WF6 and dichlorosilane by flowing SiH4 into the chamber. A further method of processing a substrate in a vacuum processing chamber includes the step of conditioning the chamber by flowing SiH4 into the chamber prior to depositing a material on the surface of the substrate. Semiconductor wafers processed according to the inventive method are characterized by more uniform sheet resistance values and reduced film stress.Type: GrantFiled: September 28, 1998Date of Patent: February 27, 2001Assignee: Applied Materials, Inc.Inventors: Meng Chu Tseng, Mei Chang, Ramanujapuram A. Srinivas, Klaus-Dieter Rinnen, Moshe Eizenberg, Susan Telford