Abstract: A generally T-shaped gate is formed by electron beam irradiation of a multilevel resist structure on a substrate. The resist structure has an upper layer which is more sensitive to the electron beam than a lower layer thereof. A generally T-shaped opening is formed in the resist structure by etching of the irradiated areas. An electrically conductive metal is deposited to fill the opening and thereby form a T-shaped gate on the substrate. After the resist layer structure and metal deposited thereon is removed, a masking layer is formed on the substrate around the gate, having an opening therethrough which is aligned with and wider than the cross section of the gate, and defining first and second lateral spacings between opposite extremities of the cross section and adjacent edges of the opening. Deposition of an electrically conductive metal forms source and drain metallizations on the substrate on areas underlying the first and lateral spacings respectively.

Abstract: A production method of a semiconductor device includes a first process for producing a gate electrode pattern of double layer structure on a semiconductor substrate, which gate electrode pattern comprises a first layer and a second upper heat-resistant material layers each having different etching property, a second process for plating a resist film on the entire surface of the substrate and etching the same to expose the top portion of the second upper heat-resistant material layer, a third process for removing the second upper heat-resistant material layer, a fourth process for hardening the surface of the resist and conducting over development of the resist, and a fifth process for plating a low resistance metal material on the entire surface of the substrate and removing the low resistance metal material together with the resist film by lift-off method, thereby to produce a gate electrode comprising the first lower heat-resistant material layer and a low resistance metal layer which is produced thereon, w

Abstract: A method of isolating individual heterojunction bipolar transistors (HBTs) on a wafer increases the current gain which can be obtained when using proton implantation to isolate the transistor. The photoresist pattern which is used to cover the transistor location during isolation implantation is undercut when etching the cap layer. A dielectric is then deposited on the etched surface, including the undercut portion. The photoresist is lifted off and an HBT is fabricated on the wafer in the area which is not covered by the dielectric. The dielectric on the undercut portion confines the emitter current to a region slightly removed from the isolation implant and provides improved current gain.

Abstract: A method for manufacturing a semiconductor device, comprising the steps of forming a first resist layer, an intermediate layer and a second resist layer sequentially on a substrate; forming an aperture by removing a portion of the second resist layer where a T-shaped gate is to be later formed; over-etching a portion of the intermediate layer opposed to the aperture thereby forming in the intermediate layer an aperture larger than the first-mentioned aperture; and forming, in the first resist layer, an aperture which is smaller than the aperture in the second resist layer which is positioned inside thereof. Due to the combination of such successive steps, the lift-off process required to form a desires T-shaped gate can be substantially improved.

Abstract: Disclosed is a process for forming a pattern of metallization on a processed semiconductor substrate, under high temperature conditions, employing a polyimide precursor material as a lift-off layer. Advantageously, the material is photosensitive, and, after exposure and development, the portions of the layer remaining on the substrate can be completely and readily removed with conventional solvents.

Abstract: A process for formation of a GaAs MESFET for use in digital IC and MMIC is disclosed, the MESFET having a high operating speed and low noise characteristics. A multilayer resist comprising a nitride film, a photo resist, a titanium deposition layer, and a SiO layer made by SOG (spin-on-glass) is formed, and a gate which is formed in the length of 0.7-1 .mu.m by applying the photo transfer method is transcribed in the length of 0.3-0.5 .mu.m. The pattern of the gate is transcribed by etching it down to GaAs, and the place for the positioning of the T-shaped gate is defined by depositing tungsten silicide and by side-etching the photo resist. The T-shaped gate is manufactured by electroplating gold, and by lifting off the rest of the portions. The source and drain are then formed in a self-aligned manner by ion-implanting to a high concentration, and then a heat treatment is carried out to make active.

Abstract: Microfabrication and large scale integration of a device can be realized by using a planar heterojunction bipolar transistor formed by a process comprising successively growing semiconductor layers serving as a subcollector, a collector, a base, and an emitter, respectively, through epitaxial growth on a compound semiconductor substrate in such a manner that at least one of the emitter junction and collector junction is a heterojunction, wherein a collector drawing-out metal layer is formed by the selective CVD method.

Abstract: A semiconductor body (1) is provided by growing epitaxial layers of semiconductor material on a substrate placed within a processing chamber and forming a mesa structure (3) on an upper epitaxial layer (2). The mesa structure (3) is formed by epitaxially growing, with the semiconductor body (1) still within the processing chamber, a first layer (4) of a semiconductor material different from that of the upper layer (2) on the upper layer (2) and the opening a window (5) in the first layer (4) to expose an area (2a) of the upper layer (2). A further layer (6) of a semiconductor material different from that of the first layer (4) is then epitaxially grown on the first layer (4) and on the said area (2a) of the upper layer. The first layer (4) is then selectively etched so as to remove the first layer (4) and the part of the further layer (6) carried by the first layer ( 14) leaving the remainder (60a, 60b) of the further layer (6) in the window (5) to form the mesa structure (3).

Abstract: A lift-off method for forming regions of a first semiconductor such as GaAs (104) in recesses in a substrate of a second semiconductor such as silicon (102) with the surface of the first semiconductor region (104) coplanar with the surface of the second semiconductor layer (102). Also, interconnected devices in both regions. Preferred embodiment methods include growth by molecular beam epitaxy of a layer of the first semiconductor on a masked and recessed substrate of the second semiconductor followed by photolithographic removal of the grown layer outside of a neighborhood of the recesses and lift-off (by mask etching) of the remainder of the grown layer outside of the recesses.

Abstract: In a method of manufacturing a GaAsFET, an insulating film used as a mask for implanting ions to form a gate region is used as a mask for sputtering a material of a gate electrode. Consequently, the gate electrode is formed to be aligned with the gate region. A GaAsFET in which the gate electrode can be stably positioned with respect to the small gate region with a high degree of accuracy and which is suitable for high frequency applications can be manufactured.

Abstract: A method for manufacturing ohmic contacts having low transfer resistances on doped semiconductor material, whereby the doping is implanted self-aligning using mask technique and the metallization is applied and, after removal of the mask layer, a temperature-time cycle occurs for simultaneous annealing the doping and alloying in the metallization.

Abstract: A method of manufacturing a hetero-junction bipolar transistor, especially of gallium arsenide, comprising the step of forming superimposed epitaxial layers for forming a collector layer (1) of the n.sup.+ type, an emitter layer (3) of the n-type, the formation of localized implantations of the p.sup.+ type to obtain the base regions (31,30) or of the n.sup.+ type to obtain collector contact islands (20). This method also includes the formation by a controlled etching into a germanium layer (50) formed at the surface of these layers, of pads having a profile such that their tips define with a very high precision openings (E.sub.1), of which the distance (E.sub.0) between the edges defines the emitter contact region, while their edges have a concavity turned towards the exterior of the device.Application integrated circuits on gallium arsenide.

Abstract: A method of manufacturing a hetero-junction bipolar transistor especially of gallium arsenide comprising the formation of epitaxial layers superimposed to obtain a collector layer (1) of the n.sup.+ type, an emitter layer (3) of the n-type, the formation of localized implantations of the p.sup.+ type to obtain the base region (31, 30) or of the n.sup.+ type to form collector contact islands (20). This method also including the formation of base contacts B (70) having the dimensions B.sub.0 and located at a relative distance of E.sub.1, then covering the metallization (70) of pads (81) of silica (Si.sub.3 N.sub.4) having edges perpendicular to the plane of the layers on which bear spacers of silicon nitride (Si.sub.3 N.sub.4) (52) having dimensions h.sub.1 defining with a high precision the dimension E.sub.0 =B.sub.1 -2h of the emitter contact E and the distances between the different collector (90), base (70) and emitter (90) contacts C, B and E, respectively.

Abstract: A method of producing a Schottky gate field effect transistor includes depositing a dummy gate film on a semiconductor substrate, depositing a second thin film on the semiconductor substrate and on the first thin film pattern to the same thickness as the first thin film, applying a photoresist on the second thin film of sufficient thickness to obtain a flat surface, etching the photoresist and second film at the same etching speed to expose the dummy gate film, removing the dummy gate film, and depositing a gate metal in place of the dummy gate film.

Abstract: A ridge waveguide laser structure is manufactured by a method including providing a photoresist stripe (8) on an exposed area of a p cap layer (4) of a multilayer laser wafer; etching channels (9) through the cap layer (4) and a p passive layer (3) using the stripe (8) and an oxide layer window (FIG. 4) as a mask; evaporating a passivating and insulating oxide (11, 11a) over the wafer, there being breaks (C) in the oxide where the stripe (8) is undercut during channel etching; and removing the stripe (8) and the oxide (11a) on it by a lift-off technique.

Abstract: An improved method of lift-off processing semiconductor devices including ohmic electrodes, gate electrodes, metal wiring, and the like. The invention provides for the production of an access groove pattern in the surface of the substrate prior to the application of the resist by photolithography and the deposition of metallization. The access groove pattern increases the opportunity for the chemical stripper to dissolve the resist and lift away the unrequired portions of the metallization, thus improving the reliability of the lift-off.

Abstract: An aluminum liftoff masking process is effected on a prepared gallium arsenide wafer having a base thereon. Successive layers of silicon dioxide and aluminum are deposited on the wafer. The aluminum and silicon dioxide layers are successively etched, including undercutting of the aluminum layer. Base majority carriers are implanted through the windows to the base and refractory metal ohmic contacts are built up in the windows. After forming the base contacts, the base contact areas may be passivated. The aluminum layer and any overlaying layers thereon are removed by etching off the aluminum.

Abstract: A method for fabricating a thin-film transistor having a stagger structure, in which the inner portion of the amorphous silicon layer doped as an ohmic contact layer to source and drain areas is defined by an insulating layer interposed therebetween, a step for forming source and drain electrodes on said amorphous silicon layer, which comprises a film forming process for forming a metal layer; a thermal treatment process for heating so as to generate a surface reaction between said metal layer and said amorphous silicon layer in order to selectively form a reaction layer only on said amorphous silicon layer; and a patterning process for selectively removing said metal layer so as to form source and drain electrodes.

Abstract: The manufacture of a self-aligned gate contact having a very short gate length measuring, for example, 0.3 to 0.1 micron wherein photolithography is carried out together with isotropic deposition to produce a gate contact having an extremely low lead resistance, the method utilizing a masking element which is removed by a lift-off technique.

Abstract: An improved patterning process, useful for the metallization of highly efficient photovoltaic cells, the formation of X-ray lithography masks in the sub half-micron range, and in the fabrication of VLSI and MMIC devices, is disclosed. The improved patterning process includes the steps of providing a substrate with a photoactive layer, patterning the photoactive layer with an inclined profile, depositing on both the substrate and the patterned photoactive layer a layer of disjointed metal such that the thickness of the metal layer exceeds that of the patterned photoactive layer and that the metal layer deposited on the substrate is formed with walls normal to the surface of the substrate. Preferably, the deposition of the disjointed metal layer is effected by evaporative metallization in a direction normal to the surface of the substrate. The deposited metal layer on the substrate is characterized by a high aspect ratio, with a rectangular cross section.

Abstract: An improved process for manufacturing a thin film transistor uses two masks for etching and therefore one mask alignment. The technical effect of said process is to provide the thin film transistor with low cost and enhanced yield.

Abstract: Method of producing two-layer metal interconnections in a semiconductor integrated circuit structure coated with silicon dioxide. Masking material is deposited on the silicon dioxide. Openings are formed in the masking material and then in the silicon dioxide to expose contact areas on the integrated circuit structure. A first metal, tungsten, is deposited on the masking material and on the contact areas exposed at the openings. The masking material and the overlying tungsten are stripped off leaving tungsten only on the contact areas. A second metal, aluminum, is deposited over the silicon dioxide and the tungsten on the contact areas. Aluminum is selectively removed to form a pattern of conductive members of tungsten-aluminum on the contact areas and of aluminum over the silicon dioxide.

Abstract: A process for making a CMOS dual-well semiconductor structure with field isolation doping, wherein only a single lithographic masking step is required for providing self-alignment both of the wells to each other and also of the field isolation doping regions to the wells. The lithographic masking step forms a well mask and defines an oxidation barrier which acts as: an implant mask (absorber) during the ion-implantation of a field dopant of one type; an oxidation barrier over one well during the oxidation of the opposite-type well to form over the one well a sacrificial oxide layer which forms the alignment marks for subsequent formation of the field-doping regions; and a dopant-transmitter during the ion-implantation of an opposite-type field dopant which is simultaneously absorbed by the sacrificial oxide. As a result, there are formed field-doped oxide layers self-aligned to the wells so that, with a subsequent masking step, oxide field isolations are defined over the doped oxide layers.

Abstract: The present method discloses the steps to form metal device contact studs between regions of a semiconductor device, such as an NPN vertical bipolar transistor, and the first level metal, the studs overlapping both a contact region (such as the base or the collector) and an adjacent polyimide-filled trench. The method is comprised of the following steps:(a) applying a lift off mask exposing said contact region and adjacent trench without attacking the polyimide fill,(b) blanket depositing the stud forming metal onto the whole structure,(c) lifting off said mask and the overlying metal,(d) blanket depositing a second dielectric layer onto the whole structure, the thickness of said second layer being approximately the stud height,(e) removing said second dielectric layer until the top surface of the highest contact stud is exposed and(f) polishing both the metal and said second dielectric layer to leave a substantially planarized structure ready for further personalization.

Abstract: Disclosed herein is a method enabling the use of four or more levels of metal over silicon chips whereby increased wiring density, reduced wiring capacitances and improved interconnection reliability are achieved. Stud vertical wiring and special etching procedures to accommodate differences in stud elevation and in stud size, are features which provide substantial planarity in the successive levels.