Abstract: A carriage for fine movement includes a stationary stage, a movable stage slidably provided thereon, a moving mechanism, coupled to the stationary and movable stages, for moving the movable stage relative to the stationary stage, wherein at least one of the stationary stage, movable stage and moving mechanism is of a fine ceramic material to prevent distortion and variation with time to enhance the abrasion resistance.

Abstract: A method for accurate front-to-back alignment of patterns onto a wafer for fabrication of multiple Burrus LED's. The front surface of the wafer has on it epitaxial layers, a dielectric layer and a metallization layer. The metallization layer includes perpendicular alignment indicia which intersect at metal contacts of the front surface of the wafer. The perimeter of the wafer is etched away to reveal the alignment indicia which when thus exposed are visible from the back side of the wafer. The exposed indicia is used to align holes in the backside metal contact to the metal contacts on the front surface.

Abstract: An aligner for aligning a mask and a wafer during photolithography of a semiconductor chip uses detection of the differential capacitance between two sets of conductive fingers on the mask and ridges on the wafer. An A.C. signal is coupled between the ridges and the fingers and the phase or amplitude of the signals is detected. An aligner utilizing multiple groups of ridges and fingers allows rotational alignment or two axis lateral alignment. An aligner having reference ledges to which the mask and the wafer are capacitively coupled allows alignment when the distance between the mask and the wafer is too great to permit meaningful capacitive coupling between the mask and the wafer to occur.

Abstract: An integrated circuit for measuring conductor misalignment comprises: a set of 2n+1 conductor pairs where n is a predetermined positive integer; each conductor pair includes a U-shaped conductor having a central axis; each conductor pair also includes a rectangular shaped conductor having a central axis and which is narrow enough to fit between the legs of the U-shaped conductor provided their central axis are aligned; and the rectangular shaped conductor of each conductor pair has its central axis a distance .delta.+k.DELTA.d from the central axis of the U-shaped conductor where .DELTA.d is a fixed increment, k is an integer between +n and -n that differs for each conductor pair, and .delta.is a misalignment between the central axis of each conductor pair.

Abstract: In a rectangular, square or other shaped single-crystal wafer of a III-V group compound semiconductor, one corner of the wafer is cut off, provided with a marking, or the wafer has a part of the original shape of the grown single-crystal ingot left intact on one side of the wafer. With the wafers thus formed, it can be distinguished between the front and back sides of the wafer, or also the direction in which a V groove etch is to occur can be identified.

Abstract: An aligner for aligning a mask and a wafer during photolithography of a semiconductor chip uses detection of the differential capacitance between two sets of conductive fingers on the mask and ridges on the wafer. An A.C. signal is applied to the ridges and the phase or amplitude of the signals coupled to the two sets of fingers is detected and compared. A shield is positioned between the ridges and the fingers to ensure that coupling occurs only between desired portions of the ridges and the fingers.

Abstract: A poly layer on a substrate is covered with nitride. A reverse tone load implant mask and etch opens an area, which is then boron implanted. Controlled oxidation follows to grow oxide on the boron-doped region only, thereby thinning the poly there. Strip the nitride and then dope the poly layer. The oxide shields the boron-doped region from further substantial doping. Next, apply a poly definition photoresist mask. Etch the exposed oxide and poly to define a poly line having a boron-doped resistor therein. The difference in etch rates between heavily doped and lightly doped poly is compensated for by the adjustment of thickness of the boron-doped region. Hence, the etch for both types of poly concludes at about the same time, leaving the underlying layers substantially intact. Sources and drains may be implanted thereafter without an additional load implant mask.

Abstract: A process is described for fabricating self-aligned buried doped regions in semiconductor devices and integrated circuits which avoids any need for delineation of the buried doped regions in the active portions of the device. Avoiding delineation improves the quality of the epitaxial layer used to cover the buried doped regions thereby improving overall performance and yield. Multiple mask layers are used in connection with a single mask pattern to achieve self-alignment. One mask layer consists of a material with a modifiable etch rate, e.g. polysilicon. A portion of the single crystal substrate is rendered non-single crystal and used as an alignment key which is propagated through the epitaxial layer grown over the undelineated buried doped regions. The dimensions and separations of the self-aligned buried doped regions can be precisely controlled.

Abstract: A novel method and device for accurately aligning a substrate comprising a silicon wafer in the fabrication of a silicon vertical junction solar cell are described which comprise a base plate having a recess therein defining an opening for snugly receiving the wafer, the recess including a substantially straight portion for mating with a cleaved edge of known crystallographic orientation provided on the wafer, and a mask plate for covering the base plate and wafer, the mask including a pattern in predetermined configuration through which the wafer may be exposed in the fabrication process for the solar cell.