Orientation Patents (Class 148/DIG115)
  • Patent number: 5399901
    Abstract: A semiconductor rectifier device includes a mesa structure formed on a surface of a monocrystalline silicon wafer, the mesa having four side walls meeting at rounded corner walls. The slope of the mesa side walls is 45 degrees and the slope of each corner wall varies between 45 and 54 degrees. The mesa is fabricated by providing a square etchant mask having rounded corners on a <100> crystal plane of a silicon wafer with the straight sides of the mask disposed at an angle of 45 degrees with <111> directions on the wafer surface. The mask corners are symmetrical and comprise, from a mid point of the corners, oppositely extending short straight lines forming an angle of 150 degrees or less therebetween. The rear end of each short line is connected by a series of end to end straight lines angled relative to one another to form a generally smooth line merging with straight sides of the mask.
    Type: Grant
    Filed: April 20, 1994
    Date of Patent: March 21, 1995
    Assignee: General Instrument Corp.
    Inventor: W. G. Einthoven
  • Patent number: 5171703
    Abstract: Methods of forming a semiconductor substrate and a device oriented substantially along a crystal direction other than a crystal direction that falls along a cleavage plane and the substrate and device formed by each method are disclosed. An ingot of monocrystalline material is formed and marked to denote a crystal direction other than a crystal direction that falls along a cleavage plane. The ingot is lapped to form a semiconductor substrate having a mark denoting a crystal direction other than a crystal direction that falls along a cleavage plane. A device is formed on the semiconductor substrate having a monocrystalline layer, such that a field oxide-active area edge or a gate electrode lies substantially along a crystal direction other than a crystal direction that falls along a cleavage plane. The present invention may be used on any device where dislocation defects, a lateral diffusion, or a lateral oxidation is to be minimized.
    Type: Grant
    Filed: August 23, 1991
    Date of Patent: December 15, 1992
    Assignee: Intel Corporation
    Inventors: Yi-Ching Lin, Haiping Dun, Ragupathy V. Giridhar
  • Patent number: 5147824
    Abstract: A semiconductor wafer having a mark indicating a specified crystal orientation is disclosed. In a preferred embodiment, first and second notches are provided on a circular outer periphery of the semiconductor wafer. A line coupling the vertices of the first and second notches indicates the crystal orientation of the semiconductor wafer. By using such notches as marks for identifying the crystal orientation, the loss of useful area of the semiconductor wafer can be reduced. Generation of slip lines which are crystal defects can be suppressed. Such notches can be formed on the bar member before slicing. By providing the notches on the bar member before individual wafers are cut therefrom, it becomes unnecessary to provide notches on the individual semiconductor wafers one by one.
    Type: Grant
    Filed: August 16, 1991
    Date of Patent: September 15, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Takao Yasue
  • Patent number: 5032538
    Abstract: A permeable base transistor (30) including a metal base layer (34) embedded in a semiconductor crystal (32) to separate collector (38) and emitter (40) regions and form a Schottky barrier with each is disclosed. The metal base layer has at least one opening (37) through which the crystal semiconductor (32) joins the collector (38) and emitter (40) regions. Ohmic contacts (42,44) are made to the emitter (38) and collector (40) regions. The width of all openings (37) in the base layer (34) is of the order of the zero bias depletion width corresponding to the carrier concentration in the opening. The thickness of the metal layer (34) is in the order of 10% of this zero bias depletion width. As a result, a potential barrier in each opening limits current flow over the lower portion of the bias range.
    Type: Grant
    Filed: July 7, 1987
    Date of Patent: July 16, 1991
    Assignee: Massachusetts Institute of Technology
    Inventors: Carl O. Bozler, Gary D. Alley, William T. Lindley, R. Allen Murphy
  • Patent number: 4911882
    Abstract: The present invention relates to the preparation of permanent magnet materials of the Iron-Boron-Rare Earth type.
    Type: Grant
    Filed: February 8, 1989
    Date of Patent: March 27, 1990
    Assignee: SPS Technologies, Inc.
    Inventor: Frank S. Greenwald
  • Patent number: 4685198
    Abstract: Disclosed is a method of isolating a transistor perfectly by employing a selective oxidation technology (LOCOS technology). More particularly, vertical openings are formed in the surface of {100} silicon substrate, and oxidation resistant films are formed of this surface and in part of the side walls of these openings. In succession, by etching with an etchant having an orientation anisotropy, dents are formed at high precision in the side walls of the openings. By oxidizing using the oxidation resistant film as the mask, an oxide film growing out from a dent in the opening side wall is connected with another oxide film growing out from an adjacent dent. The transistor thus formed in the active region of the silicon electrically isolated from the substrate is small in parasitic capacitance and may be formed into a small size, so that it possesses the features suited to VLSI, that is, high speed, low power consumption, and processability to high density integration.
    Type: Grant
    Filed: July 25, 1985
    Date of Patent: August 11, 1987
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kenji Kawakita, Noboru Nomura, Toyoki Takemoto
  • Patent number: 4662059
    Abstract: A MOS/SOI field-effect transistor is made by applying a layer of a photoresist over the surface of a single-crystalline silicon layer which is on a substrate of an insulating material, such as sapphire. The surface of the silicon layer is along a (100) crystallographic plane. The photoresist layer is defined to provide an area of the photoresist layer over the area of the silicon layer where the transistor is to be formed with the edges of the photoresist area being along the edges of (100) crystallographic planes which are perpendicular to the surface of the silicon layer. The portion of the silicon layer around the photoresist layer is etched with an anisotropic plasma etch which etches the silicon layer along the (100) crystallographic planes which are perpendicular to the surface of the silicon layer to form an island of the silicon.
    Type: Grant
    Filed: September 19, 1985
    Date of Patent: May 5, 1987
    Assignee: RCA Corporation
    Inventors: Ronald K. Smeltzer, Wesley H. Morris