Abstract: A semiconductor device includes a first region, a well-shaped second region formed in the first region and a third region formed in the well-shaped second region, both the first region and the third region have a first conductive type, the well-shaped second region has a second conductive type. A gate electrode is formed on a channel of the well-shaped second region. The channel is sandwiched between the first region and the third region. According to the present invention, the depth of the third region is very deep in a portion near the channel and is very shallow in a portion far from the channel. A resistance of the well-shaped second region near a portion of the third region far from the channel is lower than near the portion of the third region near the channel.

Abstract: A semiconductor body (3) has a first region (4) of one conductivity type adjacent one major surface (5). A first masking layer (6) comprising at least one first mask window (6a) spaced from a second mask window (6b) is defined on the surface (5). Opposite conductivity type impurities are then introduced through the first masking layer (6) and a second masking layer (8) which is selectively removable with respect to the first masking layer (6) is subsequently provided on the first masking layer and patterned to leave a mask area (8a) covering the first mask window (6a). The semiconductor body (3) is then etched through the second mask window (6b) to define a recess (9) extending into the first region (4) while leaving the introduced impurities beneath the masked first mask window (6a) to form a relatively highly doped second region (7).

Abstract: For manufacturing vertical MOS transistors, doped regions for a drain (11), well (3), and source (4) are formed in a vertical sequence in a substrate (1). Using a Si.sub.3 N.sub.4 mask (5), trenches (6) are etched perpendicular to the surface of the substrate (1). The trenches isolate the source (4) and well (3) structure, and are filled with doped polysilicon and are closed in an upper region with an insulation structure (8) in self-aligned fashion on the basis of local oxidation. The insulation structure (8) projects laterally beyond the trenches (6). Using the insulation structure (8) as an etching mask, via contact holes (9), that are provided with a metallization for contacting the source (4) and the well (3), are opened down into the well (3) between neighboring trenches (6).

Abstract: A lateral DMOS (LDMOS) transistor 10 is disclosed herein. In one embodiment, an n doped silicon layer 14 is provided and a field oxide region 24 is formed therein. A p doped D-well region 20 is formed in the silicon layer 14 and includes a p doped shallow, extension region 22 which extends from the D-well region 20 to a first side of the field oxide region 24. A first n doped source/drain region 16 is formed in the D-well region 20 and is spaced from the field oxide region 24. Also, a second n doped source/drain region 18 formed in the silicon layer 14 on a second side of the field oxide region 24. A gate region 26 is formed over the surface of the silicon layer 14 and over a portion of the first source/drain region 16, the D-well region 20, and a portion of the field oxide region 24.

Abstract: The process provides first for the accomplishment of low-doping body regions at the sides and under a gate region and then the accomplishment of high-doping body regions inside said low-doping body regions and self-aligned with said gate region. There is thus obtained an MOS power transistor with vertical current flow which has high-doping body regions self-aligned with said gate region and with a reduced junction depth.

Abstract: An N.sup.+ buffer layer (2) and an N.sup.- layer (3) are provided on a P.sup.+ silicon substrate (1) in this order. On an upper portion of the N.sup.- layer (3), a P.sup.- layer (4b) is selectively formed, and on the P.sup.- layer (4b), a P.sup.+ layer (4a) is provided. On part of a top surface of the P.sup.+ layer (4a), a plurality of N.sup.+ layers (5a) are provided, and a trench (13) is formed extending through each of the N.sup.+ layers (5a) and P.sup.+ layer (4a) downwards to the P.sup.- layer (4b). In the P.sup.- layer (4b), an N.sup.+ floating layer (5b) is provided covering the bottom face of each trench (13). In the inner hollow of the trench (13), a gate electrode (8a) is provided through a gate oxidation film (7a), while an emitter electrode (9a) is provided extending between the top surfaces of the adjacent N.sup.+ layers (5a) with the surface of the P.sup.+ layer (4a) interposed so as to electrically short circuit them. A collector electrode (10) is provided on a lower major surface of the P.sup.

Abstract: A mask (4) defining at least one window (4a) is provided on one major surface (1a) of a semiconductor body (1). The semiconductor body (1) is etched to define a groove (5) into a first region (2) of one conductivity type through a second region (3) of the opposite conductivity type. A relatively thin layer of gate insulator (6) is provided on the surface (5a) of the groove (5). A gate conductive region (7) of an oxidizable conductive material is provided within the groove (5) to define with the gate insulator layer an insulated gate structure (8) bounded by a conduction channel-defining area (30) of the second region (3). A step (15) in the surface structure is then defined by causing the insulated gate structure (8) to extend beyond the surrounding surface by oxidizing the exposed (7a) gate conductive material to define an insulating capping region (9) on the gate conductive region (3).

Abstract: A method for manufacturing CMOS transistors for integrated circuits which have metal gates and heavily doped source and drain electrode regions, thereby improving their resisting capability to a high voltage while reducing cycle time for manufacture. As a result, the performance of the transistors is improved and the cost of manufacture is reduced.

Abstract: A method of forming a LDMOS transistor device 10 is disclosed herein. A semiconductor layer 14 is provided. The layer 14 may be an n-type RESURF region formed over a p-substrate 12. An insulating layer 24, such as a field oxide, is formed on the semiconductor layer 14. The insulating layer 24 is then patterned to expose source and drain windows. A D-well region 20 is then formed within the source window portion of the semiconductor layer. A sidewall region is formed adjacent a sidewall of the insulating layer around the source window. The source and drain regions 16 and 18 are then formed, for example by implanting arsenic or phosphorus ions. A gate electrode 26 is formed over a portion of the D-well region 20 between the source region 16 and the insulating layer 24. The gate electrode 26 is formed over a channel region within the D-well 20 between the source 16 and drain 18.

Abstract: A triple-diffused lateral RESURF transistor (55,57) uses a threshold voltage adjust implant (52, 54) in conjunction with a thinner gate oxide (64) to yield a device which is more compatible with CMOS VLSI manufacturing processes and which delivers better performance characteristics than more conventional double-diffused RESURF transistor devices.

Abstract: A vertical power MOSFET comprising a metal base on which is disposed a highly doped n+ silicon substrate. A lightly doped epitaxial layer is grown on the substrate to form a drain region for conducting electrical charge carriers to the metal base. A gate region is disposed above the drain region and has side walls forming an aperture. Disposed on each side wall and axially aligned with the gate region are doped oxide spacers. Embedded within the source region beneath the aperture is a body region comprising a heavily doped region embedded within a lightly doped region. A source region, formed by diffusion from the doped oxide spacers, is disposed below each space and embedded within the body region.

Abstract: In a method of preparing a diffused silicon device substrate for use in the fabrication of a MOS power device, a drive-in diffusion step is followed by a thermal donor formation heat treatment which is achieved by heating the silicon device substrate at a temperature from 400.degree. to 500.degree. C. for 1 to 20 hours and in a gas atmosphere containing oxygen gas, and subsequently a thermal donor formation retarding heat treatment is performed by heating the silicon device substrate at a temperature of from 600.degree. to 700.degree. C. for 8 to 24 hours in a gas atmosphere containing oxygen gas.

Abstract: An insulated gate field effect transistor having a stable threshold voltage controlled with a good accuracy and a method for manufacturing the same is disclosed. The method for manufacturing a field effect transistor is such that doping a gate electrode with a P-type dopant is carried out after introducing an N-type dopant to a base layer for forming a contact region. The field effect transistor has sources having an extended portion extending into an upper portion of the contact region.

Abstract: Construction and operation method for lightly doped drain MOSFET that has low or minimum drift on-state resistance and maintains high voltage blocking in the off-state. Temperature sensitivity of the electrical properties of the MOSFET are also reduced relative to MOSFETs produced by processes such as SIPOS. Voltage level shifting of p-channel and n-channel MOSFETs, produced according to the invention, relative to another voltage level is easily accomplished.

Abstract: A manufacturing method for a low-voltage power MISFET which utilizes only three masks (photosteps). In the first step, a polysilicon layer (3) is structured and a cell field and edge zones are produced. An oxide layer (2) is then applied, this being opened in the second photostep above the cells and the edge zones and between the edge (4) and the cells. A metal layer is then applied, this being interrupted between the cells and the edge (4) with the third photostep. Field plates and a channel stopper (9) are thus produced. As last step, a weakly conductive layer (20) is applied onto the entire surface.

Abstract: The invention relates to a process for forming a buried drain or collector region in monolithic semiconductor devices comprising an integrated control circuit and one or more power transistors with vertical current flow integrated in the same chip. The process allows optimization of the current-carrying capacity and the series drain resistance of the power stage and operating voltage by the implantation of a buried gate region in a first epitaxial layer after the formation of said epitaxial layer. These buried gate regions high dopant concentrations where the dopants have low diffusion coefficients. These low diffusive dopants permit more accurate and form defined buried gate regions than current formation techniques utilizing formation of buried gate regions implemented in the substrate where these gate regions contain highly diffusive dopants.

Abstract: Power MOSFET apparatus, and method for its production, that suppresses voltage breakdown near the gate, using a polygon-shaped trench in which the gate is positioned, using a shaped deep body junction that partly lies below the trench bottom, and using special procedures for growth of gate oxide at various trench corners.

Abstract: A process of fabricating an insulated-gate field effect transistor includes step for forming a silicon gate electrode 5 on a gate insulation film 4 deposited over one surface of a p-type semiconductor substrate 10; forming n-type base regions 7 extending beneath the silicon gate electrode by introducing an n-type impurity into specified areas of the surface of the semiconductor substrate using the silicon gate electrode 5 as a mask, and then laterally diffusing the introduced impurity; forming a mask layer 8 on the silicon gate electrode; forming p-type source regions in the base regions 7 by introducing p-type impurity, with the silicon gate electrode 5 masked with the mask layer 8, into the specified areas of the surface of the semiconductor substrate, thereby portions in the base regions 7 beneath the silicon gate electrode 5 being defined as channel regions 12; forming a drain electrode 14 on the other surface of the semiconductor substrate 10.

Abstract: The present invention provides a method of manufacturing a semiconductor device, comprising the steps of selectively diffusing an impurity of a first conductivity type and another impurity of a second conductivity type into a main surface region of a semiconductor substrate so as to form first semiconductor regions of the first conductivity type and second semiconductor regions of the second conductivity type, forming a first semiconductor layer of the second conductivity type on the semiconductor substrate, said first semiconductor layer being of at least a single layer structure, forming element regions of the first and second conductivity types by thermal diffusion of impurities into the first semiconductor layer, and polishing the opposite main surface of the semiconductor substrate to expose the first semiconductor regions of the first conductivity type and the second semiconductor regions of the second conductivity type.

Abstract: A power transistor comprises, on a layer of insulator, a layer of a semiconductor material comprising several zones with N+, N and N+ doping. The N doped zone corresponds to the gate zone. The N+ doped zones correspond to the drain and source zones. A method for the making of such a transistor is also disclosed. Application: the making of a field-effect transistor with improved heat dissipation.

Abstract: A DMOS device with field oxide formed in the channel between adjacent transistors and an impurity implanted through the same opening in which the field oxide is formed. The gate is deposited over the field oxide and spaced from the supporting epitaxial layer by the field oxide to reduce the gate-to-drain capacitance. The implanted impurity below the field oxide reduces ON resistance of the device.

Abstract: A conductivity modulation type MOSFET (IGBT) including an n-type high resistance layer, p-type base regions selectively formed in a first major surface of the high resistance layer, n-type source regions formed in the surface of each base region, a p.sup.+ well region formed in a central region of each of the base regions, a channel in the base region between one of the n-type source regions and the high resistance layer, a gate electrode formed above the channel, an emitter electrode formed in contact with the p.sup.+ well region and the n-type source region, a gate insulating film formed between the gate electrode and the channel, and a metal electrode formed in contact with a second major surface of the high resistance layer opposite the first major source, the electrode forming a Schottky barrier junction.

Abstract: A field effect transistor (147) is formed in a region of a second semiconductor layer (171), having a first conductivity type. A tank region (196) of a second conductivity type opposite the first conductivity type is formed in the semiconductor region (171), and defines a tank area on the face of the semiconductor layer (171). A first highly doped region (276) formed to be of the first conductivity type is formed within the region (171) and to be spaced from the tank region (196). A gate insulator layer (218) is formed on at least one selected portion of the face, this selected portion including a portion of the tank area (196). A conductive gate (246) is formed on the gate insulator layer over the selected portion of the face. At least one second highly doped region (278) is formed at the face within the tank area to be of the first conductivity type, and to have at least one lateral edge self-aligned to a corresponding one of the lateral edges of the gate (246 ).

Abstract: A conductivity modulation type MOSFET including a first region of a first conductivity type having a low impurity concentration, second regions of a second conductivity type selectively formed on the surface region of one side of the first region, third regions of the first conductivity type selectively formed on the surface region of the second regions, gate electrodes each formed above the surface region of the second region located between the first region and the third region, a plurality of gate insulating films interlayered between the gate electrodes and the surface region of the second regions, an emitter electrode in contact with both the second regions and the third regions, a fourth region of the second conductivity type having a high impurity concentration, formed adjoining to another side of the first region, fifth regions of the second conductivity type, selectively formed surrounding the fourth region, having a lower impurity concentration than that of the fourth region, and a collector electro

Abstract: A method for fabricating a dual gate thin film transistor using a power MOSFET process having a first gate area (22) made from a monocrystalline silicon. A dielectric layer (25) is formed over the monocrystalline silicon. A first gate electrode (58) contacts the first gate area (22). A thin film transistor is fabricated on a first island of polysilicon (29) over the dielectric layer (25). The thin film transistor has a second gate electrode (55), and drain and source electrodes (56, 57) wherein the drain and source electrodes (56, 57) contact different portions of the first island of polysilicon (29). Preferably, the first gate electrode (58) is coupled to the second gate electrode (55).

Abstract: A semiconductor device comprises a semiconductor substrate, a semiconductor layer of a first conductivity type formed on said semiconductor substrate, a first semiconductor well region of a second conductivity type and second semiconductor well regions of the second conductivity type, the latter two types of regions being formed in said semiconductor layer. The first semiconductor well region is located at the peripheral area of the semiconductor, and the well is deeper than the well of the second semiconductor well regions. Third semiconductor well regions of the first conductivity type are formed in the second semiconductor well regions. Gate electrodes and an emitter (source) electrode are formed at specified positions on the upper surface of the semiconductor device, and a collector (drain) electrode is formed on the bottom surface.

Abstract: The present invention has as an object the provision of a vertical type semiconductor device whereby miniaturization and lowered ON resistance of the cell can be achieved without impairing the functioning of the device.The line width of the gate electrode is made smaller to meet the demand for miniaturization of the cell, but the distance between the channel regions diffused into the portions below the gate at the time of double diffusion is kept to be virtually equal to that in the device of larger cell size having a low J.sub.FET resistance component. Here, the reason for making the line width of the gate electrode smaller is for securing an area for the source contact.The point is that, while the width of the gate electrode is set to be smaller, the mask members as the mask for double diffusion, having the width allowing the source region to diffuse to the portion under the gate, are attached to the side walls of the gate electrode.

Abstract: A process for fabricating a p-channel VDMOS transistor includes a high temperature, long diffusion subsequent to deposition of the polysilicon gate for forming body regions. The threshold voltage of the VDMOS devices is adjusted subsequent to both gate formation and the high temperature, long duration body diffusion by implanting a suitable p-type dopant into the VDMOS channel through the insulated gate, after formation thereof. Since the gate is formed prior to threshold adjust, high temperature processing and long duration diffusions requiring the presence of the gate may be completed prior to threshold adjust, without risk to the adjusted device threshold.

Abstract: The problems normally linked to the creation of a power stage using BJT transistors are overcome realizing the power stage with BMFET transistors.

Abstract: This is a DMOS transistor and a method of forming a DMOS transistor structure. The method comprises: forming a polycrystalline silicon central gate region; forming a drain region in the substrate self-aligned to the central gate region; forming polycrystalline silicon gate sidewalls adjacent to the gate region; and forming a source region in the substrate self-aligned to the edges of the sidewalls. It can provide a channel region which is significantly longer (Ld) than it is in depth (essentially Lj) can be produced between the source region and the drain region, and thus the method provides an optimization of the transistor for lower on-resistance and thus a DMOS device having a MOS channel length longer than its parasitic JFET channel length. Preferably channel regions are formed which are 0.25-0.75 um in depth and the channel regions have an Ld of 1.0-2.5 um.

Abstract: A thyristor of the present invention turns on by applying a specified voltage to a first control electrode and turns off by applying a specified voltage to a second control electrode. These first and second control electrodes are independent of each other, so that the turning-on and turning-off conditions can be determined independently. When a transistor having the second control electrode is turned on by applying the specified voltage to the second control electrode until just before the turning-on, a first main electrode and a first semiconductor region can be electrically connected, so that the back gate potential of the transistor having the first control electrode can be fixed at the potential of the first main electrode.

Abstract: A simplified process of making an insulated gate transistor entails forming the active regions in a single diffusion step. The method includes the steps of implanting and diffusing impurities of a first conductivity type (p for n-channel devices), implanting and diffusing a heavy dose of impurities of the same conductivity type (p+ for n-channel devices), and implanting and diffusing impurities of the other conductivity type (n+ for n-channel devices), wherein the three types of impurities are diffused at the same time in the same step. In a preferred embodiment of an n-channel process, the p-type dopant is boron and the n-type is arsenic.

Abstract: A process for improving the high voltage performances of a MOSFET transistor, and suppressing parasitic current induced snap-back behavior by placing a heavily doped P+ region around the grounded source. A first P+ region is placed adjacently to and in contact with the source and its metal lead, and a second P+ region may be placed under and in contact with the source and first P+ region, or form a layer under the entire transistor connected to the source by a P+ plug. Additional grounding of the source may be accomplished by a succession of alternating P+ region and N+ regions along the source edge.

Abstract: A method is provided for manufacturing a semiconductor device at a face of a semiconductor layer having a first conductivity type. Over the semiconductor layer and insulating therefrom a gate conductive layer is formed, which has a predetermined pattern defining an opening. A well of a second conductivity type is then implanted into the face of the semiconductor layer by self-aligning to the sidewall of the gate conductive layer. A first surface region of the first conductivity type is formed within the well and self-aligned to the sidewall of the gate conductive layer. A sacrificial sidewall layer is formed in the opening which defines a second narrower opening, so that a subsurface region of the second conductivity type may be formed within the well self-aligned to the sacrificial sidewall layer. A second surface region of the second conductivity type is then formed substantially within the first surface region and self-aligned to the sacrificial sidewall layer.

Abstract: A method for fabricating an insulated gate semiconductor device comprises the steps of forming insulated gates on an n.sup.- -layer surface, forming p-well layers in the n.sup.- -layer using the insulated gates as masks, forming phosphosilicate glass layers on the side walls of the insulated gates and diffusing the impurities from the phosphosilicate glass layers into the p-well layers to form n.sup.30 -source layer.

Abstract: Method and structure is disclosed for a high-density DMOS transistor with an improved body contact. The improvement comprises a self-aligned structure in combination with a body contact region which overdopes the source region in order to minimize the number of critical photoresist steps. The use of two dielectric spacers obviates the need for a separate contact mask.

Abstract: A process for the manufacture of power-MOS semiconductor devices achieves high cell density by the use of self-aligning techniques and photographic exposure equipment of the stepper type. The process calls for definition and formation of the source by a complementary spacer technique and metallization of the source and gate contact areas by silicides after formation of spacers on the gate wall.

Abstract: An insulated gate bipolar device is formed on a multiple conductivity substrate. The multiple conductivity substrate comprises interspersed regions of N+ and P+ semiconductor material. In a preferred embodiment, the N+ and P+ regions are arranged in a checkerboard, mosaic pattern on a bottom side of the substrate. The P+ region serves to conductivity modulate an N epitaxial layer in which the IGBT structure is formed while the N+ regions improve low current conductivity, reduce minority carrier recombination time, and make an integral drain source diode accessible from the drain and source electrodes.

Abstract: A method for manufacturing a MOS type semiconductor device includes the sequential introduction of base and source layer region impurities in a base layer of a second conductivity type, disposed in a semiconductor drain layer of a first conductivity type.

Abstract: Series resistance in the low impurity portion of a high breakdown PN junction of a three or four layer device is reduced by providing an increased inpurity region at the junction of the same conductivity type as the low impurity portion and having an impurity profile such that the increased impurity region is depleted under reverse biasing before critical field is reached therein. The three layer devices include insulated gate field effect transistors and bipolar devices and the four layer device is a semiconductor controlled rectifier (SCR).

Abstract: Disclosed is a method that comprises selective deposition of titanium nitride TiN.sub.x on III-V compound semiconductor material. The TiN.sub.x can advantageously be used as contact metal. Exemplarily, deposition is by rapid thermal low pressure (RT-LP) MOCVD using dimethylamidotitanium with H.sub.2 carrier gas.

Abstract: A manufacturing method for a low-voltage power MISFET which utilizes three maskes (photosteps) is provided. In the first step, a polysilicon layer is structured and a cell field and edge zones are manufactured. An oxide layer is then applied, this being opened in the second photostep above the cells and the edge zones and between the edge and the cells. A metal layer is then applied, this being interrupted between the cells and the edge zones with the third photostep. Field plates and a channel stopper are thus produced.

Abstract: Improved insulated gate field effect transistors and methods of manufacture are disclosed wherein a self aligned source region is formed in the sides of a groove or indentation in a semiconductor substrate. By eliminating photolithography steps, yield is improved and manufacturing cost is reduced while achieving fine tolerances. As a result, reduction in cell size of approximately a factor of 6 is possible and channel resistance is reduced, allowing for increased current capacity. Source regions (26) are formed by dopant outdiffusion from insulating portions (24C).

Abstract: The present invention relates to a method of producing an insulated gate bipolar transistor, of a vertical insulated gate field effect transistor. In the present invention a window portion is formed on a low-temperature oxide film and a polysilicon layer deposited on a polysilicon layer, which serves as a gate, and the ions of impurities are implanted while using these as a mask, thereby forming a P-base layer. The ions of impurities are then again implanted using this mask to form a P.sup.++ layer instead of using a conventional resist mask. Accordingly, in the present invention, the P.sup.++ layer is formed in self alignment with the edge of the polysilicon gate. Since there is no positional deviation due to inaccurate mask positioning which may be produced when a mask such as a resist is used, positional accuracy is enhanced which hereby eliminates latchup.

Abstract: A method for fabricating an insulated gate semiconductor device comprises the steps of forming insulated gates on an n.sup.- -layer surface, forming p-well layers in the n.sup.- -layer using the insulated gates as masks, forming phosphosilicate glass layers on the side walls of the insulated gates and diffusing the impurities from the phosphosilicate glass layers into the p-well layers to form n.sup.+ -source layer.

Abstract: The present invention relates to a method of producing a metal-oxide semiconductor device with improved capacity for preventing an actuation of a parasitic bipolar transistor. In the present invention, a metal-oxide seminconductor device is produced through a process in which a single conductive semiconductor region with low-impurity density, on top of which region a gate electrode is provided via a gate-insulating film, consists of two sub-layers with different specific resistance. The upper sub-layer of the region has a significantly lower specific resistance than the lower sub-layer of the region. When a lifetime-reducing agent for reducing the reverse-recovery time of a built-in diode is diffused into the single conductive semiconductor region with low-impurity density, the lifetime-reducing agent concentrates in the upper sub-layer of the region, thereby increasing the specific resistance of the upper sub-layer.

Abstract: A process for fabricating a vertical DMOS transistor is set forth. The starting material is a heavily doped silicon wafer which has an epitaxial layer thereon. A DMOS body region is diffused into the epitaxial layer and a deep body contact region created. The source is a refractory metal Schottky barrier located on top of the body region. A trench is etched into the epitaxial layer so as to fully penetrate the body region and the trench surfaces oxidized to form a gate oxide. The trench is then filled with doped polysilicon to create a gate electrode. The resulting DMOS has a relatively short channel and the parallel bipolar parasitic transistor cannot be turned on.

Abstract: A voltage-stable sub-.mu.m-MOS transistor for VLSI circuits consist of a low-resistant silicon substrate of a first conductivity type with a high-resistant, thin, epitaxial layer of the first conductivity type situated thereon and on which a gate electrode consisting of polysilicon is disposed. Highly doped source/drain zones of the second conductivity type form a channel region of the first conductivity type. A doping substance concentration, rising in the direction of the substrate, is generated by means of double implantation, whereby the concentration maximum extends to behind the source/drain zones. A method for manufacturing same incorporates steps of forming the several layers, applying a mask, executing a double implantation in the channel region, and forming the gate electrode.

Abstract: An improved method for making a self-aligned vertical field effect transistor is provided wherein a nitride sidewall spacer is formed around a polysilicon gate, and an oxide sidewall spacer, which may be heavily doped with an n-type dopant, is formed covering the silicon nitride sidewall spacer. The silicon nitride sidewall spacer allows the oxide sidewall spacer of a conventional self-aligned vertical field effect transistor process to be removed partially or completely before making ohmic contact to the source thus increasing the contact area between the source and the source electrode and eliminating reliability problems related to n-type doped oxide in contact with aluminum electrodes.

Abstract: An oxide sidewall spacer is formed on the sidewalls of a gate prior to forming the body region of a DMOS transistor. An ion implantation or diffusion process is then conducted to form the body region, where the gate and the oxide sidewall spacer together act as a mask for self-alignment of the body region. After a drive-in step to diffuse the impurities, the body region will extend only a relatively short distance under the gate due to its initial spacing from the edge of the gate. After the body region is formed, the oxide sidewall spacer is removed, and impurities to form the source region are implanted or diffused into the body region and driven in. Since the extension of the body region under the gate is limited by the oxide sidewall spacer, the channel region between the edge of the source region and the body region under the gate may be made shorter resulting in the channel on-resistance of the transistor being reduced.