Bonding E.g., Electrostatic For Strain Gauges Patents (Class 148/DIG12)
  • Patent number: 4810672
    Abstract: In order to secure electronic components, and particularly large-area power semiconductors, to a substrate, first a paste formed of metal powder and a solvent is applied in the form of a layer to a contacting layer of the component and/or a contact surface of the substrate. The layer of paste is then dried. When the paste has dried, the component is placed onto the substrate, whereupon the entire arrangement is heated to a relatively low sintering temperature preferably between 180.degree. C. and 250.degree. C., and with simultaneous application of a mechanical pressure of at least 900 N/cm.sup.2. A connection which is thus achieved by such a pressure sintering at relatively low sintering temperatures is particularly suitable for securing power semiconductors produced in MOS-technology to a substrate.
    Type: Grant
    Filed: March 25, 1987
    Date of Patent: March 7, 1989
    Assignee: Siemens Aktiengesellschaft
    Inventor: Herbert Schwarzbauer
  • Patent number: 4810671
    Abstract: An improved method for eutectically bonding a silicon wafer onto a gold preform is described. A gold/silicon seed is placed on a pure gold preform. Then a die is placed onto the pure gold preform and the gold/silicon seed, wherein the seed acts as a catalyst to form an eutectic bond.
    Type: Grant
    Filed: March 14, 1988
    Date of Patent: March 7, 1989
    Assignee: Intel Corporation
    Inventors: Bidyut K. Bhattacharyya, Eric S. Tosaya
  • Patent number: 4808549
    Abstract: A silicon substrate having {100} nominal crystalline planes is anisotropically etched to form a pair of V-shaped grooves along the top planar surface and a first plate between the grooves. The top planar surface is then doped to form a conductor region including the first plate. A substantially uniform layer of a selectively etchable material, such as silicon oxide, is then grown over the grooved top planar surface. A layer of doped silicon is grown over the silicon oxide layer to define a pair of V-shaped members opposite the pair of grooves. The silicon layer is then partially etched to form a second plate connected to the silicon layer through a pair of V-shaped members. Both the second plate and the pair of V-shaped members are then suspended over the first capacitive plate by sacrificially etching a portion of the selectively etchable layer.
    Type: Grant
    Filed: May 27, 1988
    Date of Patent: February 28, 1989
    Assignee: Ford Motor Company
    Inventors: Mati Mikkor, Edward N. Sickafus
  • Patent number: 4773972
    Abstract: A method of bonding two silicon wafers each having a capacitive plate. Two highly-doped electrically semiconductive feedthrough paths are formed through one wafer, each path contacting one of the capacitive plates. A glass layer is formed on one of the silicon wafers where bonding is desired between the two wafers. The glass layer is anodically bonded to the other of the silicon layers.
    Type: Grant
    Filed: October 30, 1986
    Date of Patent: September 27, 1988
    Assignee: Ford Motor Company
    Inventor: Mati Mikkor
  • Patent number: 4771018
    Abstract: An improved method for eutectically bonding a silicon wafer onto a gold preform is described. A gold/silicon seed is placed on a pure gold preform. Then a die is placed onto the pure gold preform and the gold/silicon seed, wherein the seed acts as a catalyst to form an eutectic bond.
    Type: Grant
    Filed: March 19, 1987
    Date of Patent: September 13, 1988
    Assignee: Intel Corporation
    Inventors: Bidyut K. Bhattacharyya, Eric S. Tosaya
  • Patent number: 4771013
    Abstract: A three dimensional, bipolar wafer process for integrating high voltage, high power, analog, and digital circuitry, and structure formed thereby includes a wafer of non-compensated epitaxial strata on a heavily donor doped monocrystalline silicon substrate of <100> crystal orientation, which is etched and with three dimensional transistors formed in it. Passivation for and contacts to said circuits are established, and the circuits are interconnected. The high voltage and high power transistors include transistors of an H-bridge circuit, including at least one set of cascode double heterojunction transistors, the analog transistors include a bipolar transistor, and the digital transistors include transistors of a I.sup.2 L circuit. One method for constructing the wafer is by sequentially epitaxially depositing each strata in an UHV silicon-based MBE apparatus.
    Type: Grant
    Filed: August 1, 1986
    Date of Patent: September 13, 1988
    Assignee: Texas Instruments Incorporated
    Inventor: Patrick A. Curran
  • Patent number: 4738935
    Abstract: A method of manufacturing a compound semiconductor device has the steps of mirror-polishing a surface of each of two compound semiconductor substrates, bringing the mirror-polished surfaces of the two compound semiconductor substrates in contact with each other in a clean atmosphere and in a state wherein substantially no foreign substances are present therebetween, and annealing the compound semiconductor substrates which are in contact with each other so as to provide a bonded structure having a junction with excellent electrical characteristics at the interface.
    Type: Grant
    Filed: December 16, 1985
    Date of Patent: April 19, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Shimbo, Hiromichi Ohashi, Kazuyoshi Furukawa, Kiyoshi Fukuda
  • Patent number: 4701424
    Abstract: A method of forming a hermetic seal between two silicon wafers includes forming opposing troughs in each of the two wafers. In each trough are formed an isolation layer, a diffusion barrier and a tub of polysilicon. A gold strip is put on one polysilicon tub and the two silicon wafers are brought together and heated in a thermal gradient oven. A silicon gold eutectic is formed which migrates to the diffusion barrier of the silicon wafer.
    Type: Grant
    Filed: October 30, 1986
    Date of Patent: October 20, 1987
    Assignee: Ford Motor Company
    Inventor: Mati Mikkor
  • Patent number: 4670969
    Abstract: A method of making a silicon diaphragm pressure sensor includes forming an oxide film on one surface of a monocrystalline silicon substrate. A polycrystalline silicon layer is formed on the oxide film. The oxide film may be partly removed before the formation of the polycrystalline silicon layer. The polycrystalline silicon layer is heated and melt to recrystallize the same, thereby converting the polycrystalline silicon layer into a monocrystalline silicon layer. On the monocrystalline silicon layer may be epitaxially grown an additional monocrystalline silicon layer. By using the oxide film as an etching stopper, a predetermined portion of the substrate is etched over a range from the other surface of the substrate to the oxide film, thereby providing a diaphragm of the pressure sensor.
    Type: Grant
    Filed: January 25, 1985
    Date of Patent: June 9, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Kazuji Yamada, Yutaka Kobayashi, Kanji Kawakami, Satoshi Shimada, Masanori Tanabe, Shigeyuki Kobori
  • Patent number: 4638552
    Abstract: A method of manufacturing a semiconductor substrate having a modified layer therein comprises the steps of mirror-polishing one surface of each of first and second semiconductor plates, forming a modified layer on at least one of the polished surfaces of the first and second semiconductor plates, and bonding the polished surfaces of the first and second semiconductor plates with each other in a clean atmosphere.
    Type: Grant
    Filed: February 14, 1985
    Date of Patent: January 27, 1987
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Shimbo, Kiyoshi Fukuda, Yoshiaki Ohwada
  • Patent number: 4523964
    Abstract: The invention relates to a process for producing silicon diaphragm pressure transducers, and to pressure transducers so produced, which will operate in high temperature applications above 150.degree. C. by properly insulating the strain gauges from the diaphragm. This is achieved by utilizing two properly oriented silicon wafers which are joined together by a two-step diffusion technique, which includes the diffusion bonding of one boron doped wafer surface into the other wafer surface previously oxide coated, at greatly reduced pressures and temperatures than heretofore used. This simultaneous diffusion takes place because of prior contouring or the forming of relief channels into one of the bonded surfaces, and because only one joined surface is oxide coated, thus reducing process times substantially. That is, there is a continuous diffusion of boron into the boron oxide coated surface resulting in a boron rich layer of great uniformity.
    Type: Grant
    Filed: March 30, 1983
    Date of Patent: June 18, 1985
    Assignee: Becton, Dickinson and Company
    Inventors: L. Bruce Wilner, Herbert V. Wong
  • Patent number: H557
    Abstract: An epitaxial layer is used to place the surface of a crystal in compression o as to greatly increase the durability of the crystal such as a laser medium crystal.
    Type: Grant
    Filed: November 7, 1986
    Date of Patent: December 6, 1988
    Assignee: The United States of America as represented by the Department of Energy
    Inventors: Robert C. Morris, John E. Marion, II, Devlin M. Gaultieri