Abstract: A heterejunction bipolar transistor and a method for fabricating an HBT with self-aligned base metal contacts using a double photoresist, which requires fewer process steps than known methods, while minimizing damage to the active emitter contact region. In particular, a photoresist is used to form the emitter mesa. The emitter mesa photoresist is left on and a double polymethylmethacrylate (PMMA) and photoresist layer is then applied. The triple photoresist combination is patterned to create a non-critical lateral alignment for the base metal contacts to the emitter mesa, which permits selective base ohmic metal deposition and lift-off. By utilizing the double photoresist as opposed to a metal or dielectric for masking, an additional photolithography step and etching step is eliminated. By eliminating the need for an additional etching step, active regions of the semiconductors are prevented from being exposed to the etching step and possibly damaged.

Abstract: The present invention discloses a structure of a transistor in a semiconductor device and a method of manufacturing the same.The present invention manufactures a high voltage transistor by etching a silicon substrate to a depth deeper than that of the field oxide film by a self-aligned wet etching process using the field oxide film as a mask and, thereafter, by forming the first gate electrode which electrically switches ON and OFF between the source region and the drain region by using a gate electrode mask and simultaneously forming a second gate electrode to prevent a junction breakdown below the bird's beak of the field oxide film.Accordingly, the present invention can improve the degree of integration of the device by forming a gate electrode to prevent a junction breakdown below the bird's beak of the field oxide film.

Abstract: A method for producing a semiconductor laser device includes the steps of: forming window layers on either one of a top surface of an internal structure or a reverse surface of a substrate and on light-emitting end facets of the internal structure; forming a reflection film on the light-emitting end facets; removing the window layer formed on either one of the top surface or the reverse surface by using an etchant which hardly etches the reflection film; and forming electrodes on the surface from which the window layer is removed by etching and on the other surface. Another method for producing a semiconductor laser device includes the steps of: forming window layers on light-emitting end facets of the bars; inserting the bars into an apparatus having openings for forming electrodes and a supporting portion for preventing a positional shift between the bars and the openings, and forming the electrodes on the top surfaces and the reverse surfaces of the bars; and cutting the bars into the chips.

Abstract: The present invention discloses a structure of a transistor in a semiconductor device and a method of manufacturing the same. The present invention manufactures a high voltage transistor by etching a silicon substrate to a depth deeper than that of the field oxide film by a self-aligned wet etching process using the field oxide film as a mask and, thereafter, by forming the first gate electrode which electrically switches ON and OFF between the source region and the drain region by using a gate electrode mask and simultaneously forming a second gate electrode to prevent a junction breakdown below the bird's beak of the field oxide film. Accordingly, the present invention can improve the degree of integration of the device by forming a gate electrode to prevent a junction breakdown below the bird's beak of the field oxide film.

Abstract: A method for producing a semiconductor laser device includes the steps of: forming window layers on either one of a top surface of an internal structure or a reverse surface of a substrate and on light-emitting end facets of the internal structure; forming a reflection film on the light-emitting end facets; removing the window layer formed on either one of the top surface or the reverse surface by using an etchant which hardly etches the reflection film; and forming electrodes on the surface from which the window layer is removed by etching and on the other surface. Another method for producing a semiconductor laser device includes the steps of: forming window layers on light-emitting end facets of the bars; inserting the bars into an apparatus having openings for forming electrodes and a supporting portion for preventing a positional shift between the bars and the openings, and forming the electrodes on the top surfaces and the reverse surfaces of the bars; and cutting the bars into the chips.

Abstract: A semiconductor device structure (10) includes similar devices (30), (32), and (34) having different operating characteristics. Each similar device is formed on a semiconductor substrate layer (14) through openings (16), (18), and (20) in a mask layer (12). Each opening (16), (18), and (20) has a different feature size and spacing that allows for various thickness levels of layers within the similar devices (30), (32), and (34) due to desorption from the mask layer (12). The growth rate within each opening (16), (18), and (20) is inversely proportional to the feature size of the respective opening.

Abstract: A method for implanting diffusion regions during production of MOS transistors involves first patterning and etching a gate to produce a resist overhang covering at least one edge of the gate. Primary dopant is then implanted in the substrate to produce a first diffusion region having at least one boundary partially defined by the resist overhang covering the gate. By isotropically etching the resist on the gate, the gate itself is used as a mask during subsequent implantation of a halo diffusion region. The size of both the first diffusion region and the halo diffusion region is subsequently adjusted by annealing.

Abstract: A first semiconductor region is of a first conduction type and forms a transistor collector. A second semiconductor region is of a second conduction type and forms a transistor base. The second semiconductor region extends in the first semiconductor region. A third semiconductor region is of the first conduction type and forms a transistor emitter. The third semiconductor region extends in the second semiconductor region. A fourth semiconductor region is of the first conduction type and has a first portion and a second portion. The first portion extends in a part of the first semiconductor region below an edge of the third semiconductor region, and the second portion extends from the first semiconductor region into a part of the second semiconductor region outward of the edge of the third semiconductor region to limit a width of the transistor base.

Abstract: A method of forming metal contact terminals (35) of a determined size having an insulating substrate (17) with a metal land (18) formed thereon and a passivating layer (19) provided with an opening exposing a part of the metal land by forming intermediate metal contact pad (33') in the contact opening, applying and patterning a photoresist, delineating the intermediate metal contact pad (33') using pattern (31) as an in-situ mask, depositing a lead-tin solder layer (34') over a metal mask to form a solder bump (34') on the final metal contact pad, and reflowing the solder to form a solder ball (34). Thereby achieving the metal contact terminal (35) at the contact pad site. The above method has applicability to the fabrication of contact terminals for high density/high count I/O connections for advanced semiconductor chips that are appropriate for flip-chip (C4) or face-down bonding thereof on metallized ceramic (MC) substrates.

Abstract: A multilevel resist process for fine line e-beam lithography, or, alternatively, deep ultraviolet (DUV) optical lithography with a clear field mask involving the use of a plated transfer layer for image reversal. The process preferably uses a high brightness, quarter-micron diameter electron beam and a high speed negative resist to fabricate microwave MESFETs, MODFETs, and integrated circuits with gate lengths of 0.25 micron and below. This is achieved by producing a line of negative resist which can be developed to 0.25 micron or below. A plated transfer layer is then applied which provides image reversal, converting the line of resist into an opening suitable for conventional gate recess etching, gate metal deposition, and lift-off. A positive resist can be substituted for the negative e-beam resist and exposed with DUV through a clear field mask instead of an electron beam for the fabrication of MESFETs.

Abstract: A generally T-shaped gate is formed by electron beam irradiation of a multilevel resist structure on a substrate. The resist structure has an upper layer which is more sensitive to the electron beam than a lower layer thereof. A generally T-shaped opening is formed in the resist structure by etching of the irradiated areas. An electrically conductive metal is deposited to fill the opening and thereby form a T-shaped gate on the substrate. After the resist layer structure and metal deposited thereon is removed, a masking layer is formed on the substrate around the gate, having an opening therethrough which is aligned with and wider than the cross section of the gate, and defining first and second lateral spacings between opposite extremities of the cross section and adjacent edges of the opening. Deposition of an electrically conductive metal forms source and drain metallizations on the substrate on areas underlying the first and lateral spacings respectively.

Abstract: A shadow-masking process for manufacturing low dark current photodetectors with low noise characteristics is disclosed. The process includes shadow-masking a semiconductor wafer by positioning a patterned shadow-mask on a surface of the wafer. The shadow-mask is patterned with, for example, circular openings or stripe openings. Layers, such as metallization layers to form metallic contacts or anti-reflection layers are deposited onto the wafer through the patterned openings in the shadow-masks. This shadow-masking process may be used in the production of any semiconductor device requiring patterned layers.

Abstract: A method for manufacturing a semiconductor device, comprising the steps of forming a first resist layer, an intermediate layer and a second resist layer sequentially on a substrate; forming an aperture by removing a portion of the second resist layer where a T-shaped gate is to be later formed; over-etching a portion of the intermediate layer opposed to the aperture thereby forming in the intermediate layer an aperture larger than the first-mentioned aperture; and forming, in the first resist layer, an aperture which is smaller than the aperture in the second resist layer which is positioned inside thereof. Due to the combination of such successive steps, the lift-off process required to form a desires T-shaped gate can be substantially improved.

Abstract: The disclosed microcomponent has a surface oxidated type of Si substrate, at least one cathode with caesiated surface made of n type monocrystalline Si being formed on this substrate. It is surrounded by monocrystalline p tyep Si. A layer of SiO.sub.2, formed on the p type Si, has an aperture facing the cathode. This aperture is self-sealed by the anode material.

Abstract: Disclosed is a method of forming a uniform length gate electrode and contact for a microwave field-effect transistor where the gate electrode has a length of less than one micron. A photoresist plug is formed on the surface of a first photoresist layer, the plug functioning as a shadow mask in the subsequent deposition of a plasma-etch-resistant material (aluminum) over the surface of the plug and the first photoresist layer. A third photoresist layer is formed over the device structure whereby a contact region can be formed on the surface of the semiconductor sub-strate adjacent to the device region. Subsequently, the third photoresist layer is removed, and the previously shielded photoresist material over the gate electrode location is removed by plasma etch using the metal-covered plug and metal-covered first photoresist layer as a plasma-etch shield.

Abstract: Bars of integral laser diode devices cleaved from a wafer are placed with their p regions abutting and n regions abutting. A thin BeCu mask having alternate openings and strips of the same width as the end facets is used to mask the n region interfaces so that multiple bars can be partially coated over their exposed p regions with a reflective or partial reflective coating. The partial coating permits identification of the emitting facet from the fully coated back facet during a later device mounting procedure.

Abstract: A method for providing engineering changes to LSI PLAs. One or more additional input lines, output lines, and/or product terms are provided in the overall mask set, however, logically unconnected to the rest of the PLA, which is designed to provide the desired PLA function. The additional lines and terms are provided so as to be able to be connected to the PLA, and provide additional personalization by changes to the contact mask and masks for subsequent process steps to contact. The invention may be incorporated in an existing PLA macro assembler system. By simply redefining certain cells the additional devices may be incorporated through those redefined individual cells. Thus, the invention is relatively easy to retrofit to existing PLA macro assembler systems.

Abstract: The provision of an intermediately doped transition region between respective n+ implanted source and drain regions in a GaAs FET and the lightly doped channel region under the gate permits device optimizaiton for low source and drain resistance in EFET's while employing the same n+ implant for source and drain optimization in DFET's while also maintaining the same n+ to gate contact spacing in both device types. Additionally, in high frequency operation of an asymmetrically implanted FET, the tapered doping profile offered by the transition region on the drain side of the gate provides high transconductance without sacrificing high output resistance. The transition region can be provided in a self-aligned implant employing dielectric sidewall spacers and the n+ implant can be self-aligned with an etch mask employed in gate definition.

Abstract: For reduction in parasitic capacitance of a overlay gate structure, there is disclosed a process of fabricating a MES type field effect transistor comprising the steps of (a) preparing a semi-insulating substrate with a surface having a gate forming area and a remaining area, (b) forming a gate electrode on the gate forming area of the surface of the semi-insulating substrate, the gate electrode having an upper surface and side walls, (c) forming a protection film on the upper surface and the side walls of the gate electrode and the remaining area of the surface of the semi-insulating substrate, (d) covering the protection film with a material which is different in etching rate from the protection film, (e) forming a filling layer of the material for creating a generally smooth topography by removing a part of the material over the gate electrode and a part of the protection film on the upper surface of the gate electrode, the filling layer having an upper surface substantially coplanar to the upper surface o

Abstract: A method for producing a semiconductor laser comprising depositing a first semiconductor layer comprising n-type InP on an n-type InP substrate, depositing a diffraction grating of InGaAsP which includes or excludes doping impurities on the first semiconductor layer with irradiating interference fringes by a light excitation crystalline growth means, and burying a portion of the diffraction grating with InGaAsP including or excluding doping impurities with irradiating interference fringes reverse in light and darkness from said interference fringes used in depositing the diffraction grating.

Abstract: An improved patterning process, useful for the metallization of highly efficient photovoltaic cells, the formation of X-ray lithography masks in the sub half-micron range, and in the fabrication of VLSI and MMIC devices, is disclosed. The improved patterning process includes the steps of providing a substrate with a photoactive layer, patterning the photoactive layer with an inclined profile, depositing on both the substrate and the patterned photoactive layer a layer of disjointed metal such that the thickness of the metal layer exceeds that of the patterned photoactive layer and that the metal layer deposited on the substrate is formed with walls normal to the surface of the substrate. Preferably, the deposition of the disjointed metal layer is effected by evaporative metallization in a direction normal to the surface of the substrate. The deposited metal layer on the substrate is characterized by a high aspect ratio, with a rectangular cross section.

Abstract: A method of fabricating a self-aligned field-effect transistor having a T-shaped gate electrode and a sub-micron gate length. In the method of the present invention, a multi-layer gate structure is formed on an active region formed in a semiconductor substrate. A first aluminum layer of the gate structure, which is adjacent to the active region, is selectively etched to form a T-shaped gate electrode. The etching provides the first layer of the gate electrode with a gate length of less than 0.75 microns, and the T-shaped gate electrode is used as a shadow-mask to deposit self-aligned source and drain electrodes.

Abstract: Using the present invention, a gate for a MESFET may be fabricated having a minimum gate length while having a low resistance gate. In addition, the present invention provides a method for forming a gate and gate recess which are perfectly aligned which is the optimal structure for high frequency power MESFETs. A two layer masking layer is fabricated having a first layer which may be etched uniformly and a second layer of lithographic material which may be photolithographic material such as AZ resist. A gate opening is patterned in the photoresist material and a metal such as gold is deposited by evaporation from acute angles on opposite sides of the gate opening in the resist. The deposited metal serves as a mask which covers all but a very small portion of the opening in the photoresist. The silicon nitride layer is then etched to form a gate opening and gate recess.

Abstract: A one mask technique for making substrate contact from the top surface of an integrated circuit device. A thin ion implanted region of one conductivity type is formed over the entirety of a major surface of the semiconductor substrate. By lithography and etching, a shallow etched region is formed to a depth below the region of the first conductivity type at the substrate surface in an area designated for substitute contacting. A region of a second conductivity type is then formed at the central portion of the etched region. The substrate is then heated to form a buried collector region of the first conductivity type and a portion of the reach-through region of the second conductivity type in the substrate. An epitaxial layer is next formed on the major surface of the substrate. A base region of the second conductivity type for the integrated circuit is then formed.

Abstract: A method of fabricating MESFET devices having a submicron line gate electrode is disclosed. The method includes the formation of a single layer of resist material on a semiconductor surface; formation of a resist cavity through optical lithography, the cavity exposing a selected portion of the semiconductor surface; depositing by way of angled evaporation at least one gate wall within said resist cavity, the gate wall defining a shaped gate cavity; depositing gate electrode material within the gate cavity, and removing the resist material. In one embodiment of the invention the gate wall is removed from the gate electrode material, leaving a free-standing electrode. In another embodiment, the gate wall is a permanent part of the electrode structure.

Abstract: This specification discloses a self-aligned manufacturing method of a Schottky gate FET. This method comprises the steps: forming a gate metallic layer on a semiconductor substrate and a mask overhanged on the metallic layer; ion-implanting impurity ions into the semiconductor substrate using the mask to form a source/drain region; depositing an insulator on the gate metallic layer side surface and the other surface below the mask; directionally etching said deposited insulator using the mask to expose the source/drain region; depositing a source/drain electrode using the mask; and removing the mask.

Abstract: A method of fabricating MESFET devices having a T-shaped gate electrode is disclosed. The method includes the formation of a single layer of resist material on a semiconductor surface; formation of a resist cavity through optical lithography, the cavity exposing a selected portion of the semiconductor surface; depositing by way of dual-angle evaporation gate walls within said resist cavity, the gate walls defining a T-shaped gate cavity; depositing gate electrode material within the gate cavity, removing the resist material, and removing the gate walls from the gate electrode material.

Abstract: A method for forming a field effect transistor having a submicron gate length. A gate electrode is formed by angularly depositing metal through an aperture formed in a thick masking layer. A substrate upon which the gate electrode is to be formed is placed in an apparatus for depositing a stream of evaporated metal through the aperture onto portions of the substrate surface exposed by the aperture. The stream is directed at a selective oblique angle .theta. with respect to a normal to the surface of such substrate. Portions of the exposed surface of the substrate are shadowed from the obliquely directed stream of evaporated metal by an edge of the aperture formed in the thick masking layer. Thus, only selected portions of such obliquely directed stream of evaporated metal are deposited onto unshadowed portions of the substrate to thereby provide the gate electrode.