Abstract: A silicon-on-insulator (SOI) semiconductor device is made by forming a layer of single crystalline silicon on the surface of an insulating substrate. Portions of the silicon layer are removed, such as by etching, to form islands of the single crystalline silicon on the substrate with the islands having sharp corners between their side walls and their top surface. The silicon islands are then exposed to vapors of hydrogen chloride which etch the corners and form the islands with smooth, rounded corners between the side walls and the top surface.

Abstract: The present invention relates to a method of forming a single crystalline magnesia spinel film on a single crystalline silicon substrate by the use of the vapor-phase epitaxial method.According to the method of the present invention, at first a first single crystalline magnesia spinel layer having a compositional ratio of magnesium maintained at a nearly stoichiometric compositional ratio is epitaxially grown in a vapor-phase on the single crystalline silicon substrate, and then a second single crystalline magnesia spinel layer having a compositional ratio of magnesium which decreases upward is epitaxially grown in a vapor-phase on the first single crystalline magnesia spinel layer. In the event that a Si film is grown on the single crystalline magnesia spinel film formed by the method of the present invention, out of atoms of Mg and Al taken in the Si film in the initial growth stage of the Si film, a concentration of Mg atoms which react more actively upon Si can be reduced.

Abstract: An integrated circuit device uses a silicon chip having an epitaxial layer which has two portions of different thicknesses in which are formed separate junction transistors of different characteristics. In the growth of the epitaxial layer there is first formed on the front surface of the chip a localized sacrificial silicon dioxide layer removable in situ by baking in a reducing atmosphere. Then an epitaxial layer is grown by a first epitaxial deposition phase selectively over only the silicon dioxide free regions of the front surface of the chip. The sacrificial silicon dioxide layer is then removed in situ by baking in hydrogen. There is then resumed blanket growth of the epitaxial layer by a second epitaxial deposition phase.

Abstract: The described embodiments of the present invention provide a semiconductor on insulator structure providing a semiconductor layer less susceptible to single event upset errors (SEU) due to radiation. The semiconductor layer is formed by implanting ions which form an insulating layer beneath the surface of a crystalline semiconductor substrate. The remaining crystalline semiconductor layer above the insulating layer provides nucleation sites for forming a crystalline semiconductor layer above the insulating layer. The damage caused by implantation of the ions for forming an insulating layer is left unannealed before formation of the semiconductor layer by epitaxial growth. The epitaxial layer, thus formed, provides superior characteristics for prevention of SEU errors, in that the carrier lifetime within the epitaxial layer, thus formed, is less than the carrier lifetime in epitaxial layers formed on annealed material while providing adequate semiconductor characteristics.

Abstract: A semiconductor arrangement has a substrate which carries a partially filled array of semiconductor cells, and utilises the vacant sites in the array to position interconnecting tracks. A filled array is manufactured, and when the electrical function of the arrangement has been allocated, those semiconductor cells, each of which contains active semiconductor devices, which are not needed to perform the allocated function are removed. The vacant sites so formed are then occupied by electrically conductive tracks. The arrangement is suitable for silicon-on-sapphire gate arrays.

Abstract: A method for fabricating a thin-film transistor having a stagger structure, in which the inner portion of the amorphous silicon layer doped as an ohmic contact layer to source and drain areas is defined by an insulating layer interposed therebetween, a step for forming source and drain electrodes on said amorphous silicon layer, which comprises a film forming process for forming a metal layer; a thermal treatment process for heating so as to generate a surface reaction between said metal layer and said amorphous silicon layer in order to selectively form a reaction layer only on said amorphous silicon layer; and a patterning process for selectively removing said metal layer so as to form source and drain electrodes.

Abstract: A method of fusing two or more semiconductor wafers involves growing a silicon dioxide planar layer on each of two polished silicon wafer substrates, implanting positive ions in the silicon dioxide layers on one wafer and negative ions in the silicon dioxide layer on the other wafer. The source of positive ions is preferably cesium and the source of negative ions is preferably boron. The implanted grown oxide layers are brought into abutment so electrostatic attraction forces of the oppositely charged ions keep the wafers together while they are exposed to a relatively high temperature in an oxygen ambient to fuse the abutting surfaces together.

Abstract: There is disclosed a film field effect transistor which can be operated at fast switching rates for use, for example, in video display applications. The transistor includes a body of silicon semiconductor material having a structure more ordered than amorphous material and less ordered than single crystalline material. The source and drain of the transistor comprise rectifying contacts formed on the body of silicon semiconductor material. Also disclosed are a method of making the transistor and an electronically addressable array system utilizing the transistor to advantage.

Abstract: A method for forming a silicon dioxide layer on a silicon island on an insulating substrate includes the steps of initially providing an insulating substrate having a major surface on which a silicon island is disposed. The surface of the silicon island is then thermally oxidized and a silicon layer is deposited on the oxidized island and the portion of the substrate surface adjacent to the island. This entire silicon layer is then oxidized and a conductive polycrystalline silicon electrode is deposited thereon.

Abstract: A method is disclosed for the manufacture of a multilayered interconnect structure on an insulating substrate. First and second conductive layers are formed on one and on the other (reverse) surfaces, respectively, of the insulating substrate. An insulating layer is formed, by means of a plasma CVD method, on the surface of the insulating substrate, to electrical insulation between interconnect layers. This is followed by a reactive ion etching step. This results in the formation of the aforementioned layer of a uniform thickness and having a uniform etching rate. That is, with the conductive layer formed on the rear surface of the insulating substrate, the complete insulating substrate is placed at the same potential level, whereby a uniform electrochemical reaction occurs on the surface thereof, resulting in the formation of the layers having a uniform etching rate, and in the formation of these layers each having the same thickness.

Abstract: The invention relates to a method for the manufacture of field effect transistors of the coplanar and self-aligned type, obtained in thin film form on an insulating substrate.As a result of electrode self-alignment and ion implantation, the method makes it possible to use only three masking levels.The invention is applicable to the field of large surface microelectronics and particularly to the control and addressing of a flat liquid crystal screen or an image sensor.

Abstract: A process for manufacturing semiconductor devices, comprising steps for obtaining a multilayered structure consisting of semiconductors and insulating films, by forming a microbridge which consists of a semiconductor in the form of a connecting bar or a one-side supported bar, and by forming an insulating film by oxidizing the exposed surface of the microbridge. The semiconductor device manufactured by the process of the invention exhibits good interface properties between the insulating film and the semiconductor layer. The invention makes it possible to easily manufacture a variety of MOSFETs with the SOI structure, which exhibit excellent characteristics.

Abstract: The present invention accomplishes the thermal oxidation of the silicon side of the interface present in epitaxial silicon films grown on yttria-stabilized cubic zirconia, <Si>/<YSZ>, to form a dual-layer structure of <Si>/amorphous SiO.sub.2 /<YSZ>. The SiO.sub.2 films are formed in either dry oxygen (at 1100.degree. C.) or in pyrogenic steam (at 925.degree. C.) by the rapid diffusion of oxidizing species through a 425 .mu.m thick cubic zirconia substrate. For instance, a 0.17 .mu.m thick SiO.sub.2 layer is obtained after 100 min in pyrogenic steam at 925.degree. C. This relatively easy transport of oxidants is unique to YSZ and other insulators which are also superionic oxygen conductors, and cannot be achieved in other existing Si/insulator systems, such as silicon-on-sapphire.

Abstract: A method for forming a layer of silicon dioxide over a silicon island on an insulating surface wherein the layer on top of the island is thinner than on the sidewalls is disclosed. The silicon island is oxidized and a silicon layer is deposited thereover. A layer of planarizing material is deposited over the silicon layer. The planarizing layer is anisotropically etched until the surface of the silicon layer overlying the island is exposed. The silicon layer is in turn etched until the surface of the oxide layer overlying the island is exposed. The remaining planarizing material is removed and the remaining silicon layer is oxidized. The thickness of the gate oxide layer on top of the island may be controlled by again exposing the island surface and reoxidizing to a predetermined thickness. A conductive polycrystalline silicon electrode is deposited on the oxide-covered island. The disclosed method is particularly useful in the formation of MOSFETs.

Abstract: A method of fabricating a shared element semiconductor structure in which the insulating layer of a silicon-on-insulator structure is patterned to form a gate oxide. The bulk semiconductor underlying the insulating layer is defined into an FET (field-effect transistor) with its gate region below the gate oxide. The epitaxial layer above the insulating layer is defined into another FET with its drain region above the gate oxide, whereby the drain region also operates as the gate electrode for the bulk FET. Also described is a method of forming a silicon on insulator substrate with insulating layer usable as a gate oxide by means of bonding a silicon substrate to an oxidized epitaxial layer on another silicon seed substrate and then removing the seed substrate.

Abstract: Edge conduction in a silicon-on-sapphire transistor is minimized by a process which permits precise doping of the edge channel regions of the transistor. The silicon island (19) containing the transistor (24) is precisely doped around its edges by ion implanting an epitaxial silicon layer (13) on a sapphire substrate (11), with an oxide mask (29) covering, with the exception of a narrow peripheral edge (37), the portion of the silicon which is eventually to form the island (19') on which the transistor is to be constructed. The mask (29) is then expanded by the addition of a sleeve (43) to cover the additional peripheral edge region (37) in the silicon. When the silicon is subsequently etched using the expanded oxide pattern 45 as a mask, the periphery of the remaining silicon will be doped to a predetermined depth (37) corresponding to the width of the sleeve (43).

Abstract: Picosecond response photoconductors and photoresponsive elements can be provided that retain high carrier mobility and yet have short lifetime by providing on a crystal mismatched substrate a textured layer of domain regions wherein the domain size is such that the lifetime is proportional to the square of the size divided by the diffusion coefficient of the semiconductor material. The crystalline orientation in the domains with respect to the substrate is maintained. An embodiment is an approximately 0.1 micron thick textured layer of <111> GaAs grown on a <0001> hexagonal monocrystalline Al.sub.2 O.sub.3 having domains approximately 1.0 micron with a carrier lifetime about 5 picoseconds and a carrier mobility of about 80 cm.sup.2 volt.sup.-1 sec.sup.-1.

Abstract: The purity and perfection of a semiconductor is improved by depositing a patterned mask (12) of a material impervious to impurities of the semiconductor on a surface (14) of a blank (10). When a layer (40) of semiconductor is grown on the mask, the semiconductor will first grow from the surface portions exposed by the openings (16) in the mask (12) and will bridge the connecting portions of the mask to form a continuous layer (40) having improved purity, since only the portions (42) overlying the openings (16) are exposed to defects and impurities. The process can be reiterated and the mask translated to further improve the quality of grown layers.

Abstract: The invention provides a process comprising a step for depositing at least one intrinsic or doped monocrystalline silicon layer on a substrate, also monocrystalline, followed by a step for forming a thin silica layer at the level of the original substrate-silicon interface. The silica layer is obtained by oxidation through the substrate, followed by a heat treatment step during which the monocrystalline silicon is oxidized by the implanted oxygen ions. The first approach may take place according to two variants: thermal or plasma oxidation of the silicon-substrate interface. Oxidation takes place during the return to ambient temperature of the stack of layers after the deposit has been made.