Abstract: To provide a lateral MISFET that has a uniform and reliable gate insulation film, and exhibits low on-resistance and excellent balance between the breakdown voltage and on-resistance. The device of the invention has an n-type semiconductor substrate, in a part of the surface layer thereof is formed a trench. An n-drain region is formed in the bottom of the trench. A side wall oxide film is formed on the side face of the trench. The trench is filled with a conductive material, on which is formed a drain electrode. A p-base region and an n-source region are self-aligned on the portion of the substrate in which the trench is not formed. A MIS gate is disposed on the p-base region. Since the portion of the substrate along the side wall oxide film functions as a drain drift region, the unit cell dimension are greatly reduced, the on-resistance is reduced, and therefore the trade-off relation between the breakdown voltage and the on-resistance is improved.

Abstract: A semiconductor processing method of providing dopant impurity into a semiconductor substrate includes: a) providing a semiconductor substrate, the substrate comprising a first bulk region having a blanket doping of a first conductivity type dopant, the substrate comprising a second bulk region having a blanket doping of a second conductivity type dopant; b) defining field oxide regions and active area regions in each of the first and second bulk substrate regions; c) in the same masking step, masking active area regions of the first bulk substrate region while leaving field oxide regions of the first bulk substrate region unmasked and masking field oxide regions of the second bulk substrate region while leaving select active area regions of the second bulk substrate region unmasked; and d) in the same ion implanting step, ion implanting first conductivity type impurity through the unmasked portions of the first and second bulk substrate regions to simultaneously form channel stop isolation implants beneath t

Abstract: An embodiment of the present invention is a method of fabricating power and non-power devices on a semiconductor substrate, the method comprising: forming alignment marks in the substrate (100); introducing a dopant of a first conductivity type into the substrate to form high-voltage tank regions (103); annealing the dopants (105); introducing dopants of the first conductivity type and a second conductivity type in a region in the high-voltage tank region (109); annealing the dopants of the first and the second conductivity type to form a second region within a third region, both within the high-voltage tank region, due to the different rates of diffusion of the dopants (110); and forming gate structures after the annealing of the dopants of the first and second conductivity types (122).

Abstract: A bonded, SOI wafer which has stepped isolation trenches and sublayer interconnections first formed in a bulk silicon wafer. After these process steps are complete, a thin polysilicon layer is formed on the planarized upper surface of the bulk silicon wafer. This thin polysilicon layer is then bound to an oxide layer on the surface of a separate wafer to form a bonded silicon-on-oxide structure. The entire assembly is, in effect inverted, and what had been the lower surface of the bulk silicon wafer, is removed to the bottom of the deepest trench step. In this bonded SOI structure, regions between the trenches are deep and suitable for bipolar device fabrication, while the trench steps form shallow regions suitable for fabrication of CMOS devices.

Abstract: A process for fabricating transistors on a substrate is disclosed. In accordance with the process, stacks of material are formed on the surface of the substrate. Walls of silicon dioxide are created around the stacks in order to insulate the material within the stacks from the material deposited outside of the walls. A first layer of polycrystalline material is deposited over the substrate and selectively removed such that only those portions of the polycrystalline layer that surround the stacks of material remain. A layer of silicon nitride or silicon dioxide is then formed over the substrate surface. A first resist is then spun on the substrate surface. This resist aggregates near the stacks of material. An isolation mask is generated that leaves exposed only those areas of the substrate that correspond to the area of overlap between the first polycrystalline area and the stacks of material, which also contain a layer of polycrystalline material.

Abstract: A field-effect, power-MOS transistor wherein a region under the gate contact pad is specially doped with a dopant that is electrically compatible with that in the transistor's channel to obviate problems of electrical breakdown in that region.

Abstract: An embodiment of the present invention is a method of fabricating power and non-power devices on a semiconductor substrate, the method comprising: forming alignment marks in the substrate (100); introducing a dopant of a first conductivity type into the substrate to form high-voltage tank regions ( 103); annealing the dopants (105); introducing dopants of the first conductivity type and a second conductivity type in a region in the high-voltage tank region (109); annealing the dopants of the first and the second conductivity type to form a second region within a third region, both within the high-voltage tank region, due to the different rates of diffusion of the dopants (110); and forming gate structures after the annealing of the dopants of the first and second conductivity types (122).

Abstract: A method for forming a first doped region (24) and a second doped region (26) within a substrate (12). A masking layer (14) overlies the substrate (12). A first region (20) of the masking layer (14) is etched to form a first plurality of openings. A second region (22) of the masking layer (14) is etched to form a single opening or a second plurality of openings different in geometry from the first plurality of openings. A single ion implant step or an equivalent doping step is used to dope exposed portions of the substrate (12). The geometric differences in the masking layer (14) between region (20) and region (22) results in the formation of the first and second doped regions (24 and 26) wherein the first and second doped regions (24 and 26) vary in doping uniformity, doping concentration, and doping junction depth.

Abstract: An embodiment of the present invention is a method of fabricating power and non-power devices on a semiconductor substrate, the method comprising: forming alignment marks in the substrate (100); introducing a dopant of a first conductivity type into the substrate to form high-voltage tank regions (103); annealing the dopants (105); introducing dopants of the first conductivity type and a second conductivity type in a region in the high-voltage tank region (109); annealing the dopants of the first and the second conductivity type to form a second region within a third region, both within the high-voltage tank region, due to the different rates of diffusion of the dopants (110); and forming gate structures after the annealing of the dopants of the first and second conductivity types (122).

Abstract: A trench isolation process for bipolar and/or MOS circuits employs trench isolation with the trenches extending from an isolation region just below the surface down to and through a buried layer having the same dopant polarity as the isolation regions, so that inversion along the sidewalls of the trench is prevented.

Abstract: In a semiconductor IC, a vertical pnp or npn transistor of a uniform characteristic and a high breakdown voltage is made by forming, for example, a p.sup.- -collector region (39) in an n-type epitaxial region, an n-well base region (41) formed in the p.sup.- -collector region (39) and a p-emitter region (42) formed in the n-well base region (41); and furthermore, for example as shown in FIG. 9, p.sup.- -regions (40) and (49) are formed simultaneously with the p.sup.- -collector region (39) and an n-region (53) is formed simultaneously with the n-well base region (41), thereby constituting IIL of superior characteristics and a high resistance device at the same time as forming of the vertical transistor without substantial increase of manufacturing steps; and in the similar way, by combining the p.sup.- -region and n-region formed in the above-mentioned simultaneous steps with other region formed simultaneously with the forming of the vertical transistor, high h.sub.

Abstract: A bipolar transistor and method of making the same is disclosed. The transistor has an emitter region which is diffused from polysilicon into the intrinsic base region, where the polysilicon is doped with two dopant species of different diffusivity. The impurity concentration of the higher diffusivity species, for example phosphorous, can be selected to define the emitter junction depth, which is preferably shallow, while the impurity concentration of the lower diffusivity species, for example arsenic, can be selected to provide a high conductivity emitter electrode, as well as reduce the sensitivity of the emitter electrode to counterdoping from the implantation of the extrinsic base region. The structure is compatible with BiCMOS processing, as the same anneal can be used to diffuse the emitter and the source/drains of the MOS transistors, with the emitter junction depth optimized via the implant conditions of the higher diffusivity species.

Abstract: A method of producing a semiconductor laser including deposition a first film as a source of n type impurities on a portion of a semiconductor structure produced by growing at least a p type lower cladding layer, a quantum well active layer, and an n type upper cladding layer successively on a substrate, depositing a second film as a source of p type impurities at least on the surface of the semiconductor structure on both sides of and on the first film and annealing to diffuse p and n type impurities at the same time, thereby disordering portions of the quantum well except for the portion becoming an active region with p type impurities reaching at least the p type lower cladding layer, n type impurities reverting the portions of the n type cladding layer to which p type impurities have diffused to n type, and the n type impurities reaching the n type cladding layer but not reaching the active layer.

Abstract: In a method of manufacturing a semiconductor device according to the present invention, regions of first conductivity type buried layers formed on a first conductivity type substrate are retracted with respect to regions of second conductivity type buried layers. Thus, in formation of second conductivity type epitaxial layer, first conductivity type impurity contained in the first conductivity type buried layers is prevented from floating diffusion up to element regions of the second conductivity type epitaxial layers. At the same time, the semiconductor device can be implemented with high density of integration.

Abstract: A process for creating bipolar and CMOS transistors on a p-type silicon substrate is disclosed. The silicon substrate has a typical n+ buried wells and field oxide regions to isolate the individual transistor devices. In accordance with the process, stacks of material are created over the gate elements of the CMOS devices and over the emitter elements of the bipolar transistors. The stacks of material over the gate elements have a silicon dioxide gate layer in contact with the epitaxial layer of the substrate, and the stacks of material over the emitter elements have a polycrystalline silicon layer in contact with the epitaxial layer. Walls of silicon dioxide are created around the stacks in order to insulate the material within the stacks from the material deposited outside of the walls. Polycrystalline silicon in contact with the epitaxial layer is deposited outside the walls surrounding the stacks.

Abstract: A method of manufacturing a compound semiconductor device has the steps of mirror-polishing a surface of each of two compound semiconductor substrates, bringing the mirror-polished surfaces of the two compound semiconductor substrates in contact with each other in a clean atmosphere and in a state wherein substantially no foreign substances are present therebetween, and annealing the compound semiconductor substrates which are in contact with each other so as to provide a bonded structure having a junction with excellent electrical characteristics at the interface.

Abstract: Manufacturing of a graft-base transistor is characterized by: first, forming a layer (8) of oxide of silicon with opening on an n-semiconductor layer (2), at a part to become a base region (3, 4, 3) (FIG. 2a)); then, forming a polycrystalline silicon layer (9) and an overriding silicon nitride layer (10) with an opening (11) thereon (FIG. 2(b)); selectively diffusing P or As to form an n-emitter region (5) (FIG. 2(c)); forming a second silicon oxide layers (12, 13) only on the emitter region (5) and on peripheral regions thereabout, and removing the polycrystalline layer (9) and the silicon nitride layer (10), (FIG. 2(d)) (FIG. 2(e)); and implanting B.sup.+ ions, thereby to form deeper and higher concentration base contact regions (3, 3) and shallower and lower concentration active base region (4).

Abstract: Apart from the base fingers (10), this transistor includes a titanium silicide coating, from which the base diffusions have been formed, and a silicon nitride coating (4). The edges of sandwiches made up of bands (3) and (4) are bordered by a silica bank (7) formed automatically by deposit and anisotropic attack, without additional masking. The emitter fingers (9) are overhung by a polycrystalline silicon layer (8) from which doping of these fingers has been obtained.The possibility is also obtained, automatically and without masks alignment, of having the emitter and base fingers brought firmly together with minimum protection distances.

Abstract: A method for manufacturing semiconductor devices is presented. The method comprises the steps of opening two windows on an insulating layer covering a semiconductor substrate, and forming a polysilicon layer over the entire surface of the insulating layer and the windows. Donor and acceptor impurities are respectively implanted into the portions of the polysilicon layer corresponding to the two opening windows through the appropriate photoresists. The doped impurities are thereafter subjected to annealing to form two different conduction type regions under the two opening windows. Thereafter, a metal layer and a photoresist are deposited in order to make the metal electrodes for each conduction region. Thus, the patterning of the polysilicon can be made in self-alignment with the etching mask, and the formation of two different conduction type semiconductor regions are simultaneously attained.

Abstract: An integrated circuit wherein the base and surface collector regions of the I.sup.2 L vertical transistor are formed by the same steps used to form the collector and base, respectively, of complementary bipolar transistors. Thus, a high voltage bipolar transistor of the same type as the vertical I.sup.2 L transistor may be formed using separate process steps, thereby optimizing the design of both devices.