Solid Solubility Patents (Class 148/DIG155)
  • Patent number: 5270224
    Abstract: A bipolar transistor includes a base region made of silicon crystal doped with a first impurity to a first level so as to establish a first carrier concentration in the base region and an emitter region made of silicon crystal doped with a second impurity to a second level substantially larger than the first level by a predetermined factor so as to establish a second carrier concentration in the emitter region, in which the second impurity exceeds the solubility limit of the second impurity in silicon crystal. The first and second levels are chosen in such a range that a difference in the carrier concentrations between the emitter region and the base region decreases substantially with increasing impurity level in the base region.
    Type: Grant
    Filed: January 17, 1992
    Date of Patent: December 14, 1993
    Assignee: Fujitsu Limited
    Inventors: Yuji Furumura, Fumitake Mieno, Tsutomu Nakazawa, Takashi Eshita, Mamoru Maeda, Tsunenori Yamauchi
  • Patent number: 5212101
    Abstract: The invention provides a method of producing silicon with about 100% substitutionality of very high concentrations of carbon up to about 10.sup.21 cm.sup.-3, which has good quality recrystallized layers containing low levels of residual damage, and which avoids precipitation of mobile carbon. This method, compatible with current state-of-the-art VLSI silicon technology, comprises the sequential steps of: implanting a silicon wafer with carbon ions, and two step annealing of the implanted silicon wafer.
    Type: Grant
    Filed: November 6, 1991
    Date of Patent: May 18, 1993
    Assignee: Secretary of State for Defence in her Britannic Majesty's Government of the United Kingdom
    Inventors: Leigh T. Canham, Keith G. Barraclough, Mark R. Dyball
  • Patent number: 5063166
    Abstract: A low dislocation density semiconductor device includes a first semiconductor layer of a III-V or II-VI semiconductor compound and alloying atoms on a non-metal substrate. The semiconductor compound usually has a large dislocation density. A predetermined position of the alloying atoms in the compound lattice structure can substantially reduce the compound dislocation density. Energy is applied to the alloying atoms so they are at the predetermined positions. The number of alloying atoms causes the semiconductor compound solubility limit to be exceeded. The layer is formed on a substrate of the III-V or II-VI semiconductor, such as gallium arsenide or another semiconductor, such as silicon or on an insulator such as sapphire. In the latter cases, the layer is formed on an intermediate layer having a lattice constant between that of the substrate and semiconductor compound.
    Type: Grant
    Filed: April 9, 1990
    Date of Patent: November 5, 1991
    Assignee: SRI International
    Inventors: John B. Mooney, Arden Sher