Abstract: A resonant tunneling diode (400) made of a germanium quantum well (406) with silicon oxide tunneling barriers (404, 408). The silicon oxide tunneling barriers (404, 408) plus germanium quantum well (406) may be fabricated by oxygen segregation from germanium oxides to silicon oxides.

Abstract: High speed Group III-Sb materials are n-doped in a molecular beam epitaxy process by forming a superlattice with n-doped strained layers of a Group III-V compound upon Group III-Sb base layers. The base layers have lower conduction band energy levels than the strained layers, and allow doping electrons from the strained layers to flow into the base layers. The base layers preferably comprise Al.sub.x Ga.sub.1-x Sb, while the strained layers preferably comprise a binary or ternary compound such as Al.sub.y Ga.sub.1-y As having a single Group V component, where x and y are each from 0 to 1.0. The strained layers can be n-doped with silicon or tin, which would produce p-type doping if added directly to the base layers.

Abstract: A quantum dot logic unit (8) is provided which comprises a row of quantum dots (14, 16, and 18), with each quantum dot separated by vertical heterojunction tunneling barriers (20, 22, 24, and 26). Electric potentials placed on inputs (32, 34, and 36) are operable to modulate quantum states within the quantum dots, thus controlling electron tunneling through the tunneling barriers.

Abstract: A heterojunction device including a first semiconductive layer on a substrate, a barrier layer on the first layer, a second semiconductive layer on the barrier layer and a multi-layer cap, on the second semiconductive layer. First and second gates positioned on layers of the cap to define first and second transistors, with the cap layers being selected and etched to pin the Fermi level in a first transistor conduction channel in the second semiconductive layer such that the number of carriers in the first conduction channel are substantially less than the number of carriers in surrounding portions of the second semiconductive layer and the Fermi level in a second transistor conduction channel in the first semiconductive layer such that the number of carriers in the second conduction channel are substantially less than the number of carriers in surrounding portions of the first semiconductive layer.

Abstract: A superheterojunction Field Effect Transistor (FET) with a multi-region channel on a Silicon (Si) substrate. The FET is a Metal Semiconductor FET (MESFET) or, alternatively, a Junction FET (JFET). The multi-region channel has: A first region of Si extending from the FET's source to a point under the FET's gate, beyond the gate's midpoint; a second region extending from the first region to the FET's drain, comprised of a superlattice of alternating Si and SiGe layers; and, a third region of Si extending under the first two regions from the source to the drain. The first region has a laterally graded dopant that creates an accelerating electric field. The superlattice structure increases electron mobility and transit velocity.

Abstract: An FET thin film transistor is formed with a channel formed of a Si/Si.sub.1-x Ge.sub.x /Si three layer sandwich which serves as the carrier transfer channel. The percentage of germanium is preferably less than 30% and should be less than about 50%. The TFT can be structured as top gate, bottom gate or twin gate structure. The Si/Si.sub.1-x Ge/Si sandwich layer is processed in a continuous process under computer control.

Abstract: A method of producing a thin film field effect transistor. An insulating thin film layer is formed on a gate electrode subsequent to the gate electrode being formed on a substrate. A multilayer structure is formed on the insulating thin film layer subsequent to the insulating thin film layer being formed on the gate electrode by alternately laminating a number of non-monocrystalline semiconductor material layers and a number of non-monocrystalline material layers.

Abstract: A strain-compensated III-V quantum well device is grown by vapor phase epitaxy using the same relative atomic proportions of indium and gallium in both the quantum well layers (20) and the barrier layers (21). The top and bottom barrier layers of the quantum well stack are half the thickness of the other barrier layers of the stack.

Abstract: Disclosed herein is a novel process for the manufacture of optical bistable switching device including multiple quantum wells. The process is carried out by: supplying a first organo-metallic compound as the source of a first metallic element and a reaction gas continuously while supplying a second organo-metallic compound as the source of a second metallic element in a discrete mode into a reactor and cultivating a semiconductor multiple quantum wells region having multiple pairs of intrinsic semiconductor-layer/semiconductor-layer(GaAs/AlGaAs), one of the layer containing said second metallic element(Al), while controlling the mole fraction of said second metallic element(Al) to be in the range of 0.01 to 0.25 of the total first and second metal contents existing in the layer containing the second metallic element, thereby lowering the impurity concentration and optimizing the negative resistance.

Abstract: A method for the making of an optoelectronic device comprising at least one quantum well, the barriers of which are made of GaInP and the well of which is made of GaAs, is carried out by the interdiffusion of elements between barriers and quantum wells in such a way that there is a migration of at least indium elements from a barrier to the quantum well. The method can be applied to the making of quantum well lasers, photodetectors and optical guides.

Abstract: A method of forming gallium arsenide on silicon heterostructure including the use of strained layer superlattices in combination with rapid thermal annealing to achieve a reduced threading dislocation density in the epilayers. Strain energy within the superlattices causes threading dislocations to bend, preventing propagation through the superlattices to the epilayer. Rapid thermal annealing causes extensive realignment and annihilation of dislocations of opposite Burgers vectors and a further reduction of threading dislocations in the epilayer.

Abstract: A method for diffusing n type impurities from a solid phase source into a III-V compound semiconductor includes depositing an amorphous or polycrystalline selenium or sulfur film on the III-V compound semiconductor and diffusing selenium or sulfur from the film into the compound semiconductor by annealing. Highly controllable diffusion of n type impurities in a high concentration is achieved.

Abstract: A semiconductor growth process wherein a plurality of layers, each consisting of a different king of semiconductor material, are grown, includes the steps of: heating a substrate to a first growth starting temperature at which a growth of a first semiconductor layer can be started, supplying a first material gas to the surface of the substrate to cause a growth of the first semiconductor layer, lowering the temperature of the substrate to below first growth starting temperature, and at the same time, stopping the supply of the first material gas, to stop the growth of the first semiconductor layer, heating the substrate to a second growth starting temperature at which a growth of a second semiconductor layer can be started, and supplying a second material gas to the surface of the substrate to cause a growth of the semiconductor layer.

Abstract: A method of fabricating a semiconductor laser device includes disposing a lower cladding layer, a superlattice active layer, an upper cladding layer, and a contact layer in the named order on a substrate, forming resonator end surfaces, disposing, on the resonator end surfaces, films containing a material that disorders the semiconductor superlattice structure when diffused into the superlattice structure, and passing a current between the substrate and the contact layer to cause laser oscillations. The laser oscillations produce laser light that is absorbed at the resonator end surfaces. The resonator end surfaces are locally heated due to absorption of laser light whereby the disorder-causing material is diffused from the films into the resonator end surfaces and the semiconductor superlattice structure in the vicinity of the resonator end surfaces is thereby disordered to form window regions.

Abstract: A photovoltaic cell that includes a transparent substrate, a front conductive layer formed on the substrate, a p-type layer formed on the front conductive layer, an i-layer of amorphous silicon formed on the p-layer, a wide bandgap n-type layer formed on the i-layer and a back contact layer formed on the n-type structure. The wide bandgap n-type layer may be an n-type sandwich structure which includes first, second, and third n-layers successively formed on one another. The first n-layer is formed on the i-layer, the second n-layer is formed on the first n-layer, and the n-layer is formed on the second n-layer. The second n-layer has an optical bandgap wider than the optical bandgap of the first and second n-type layers.

Abstract: A method of fabricating a semiconductor heterostructure includes the growth of a quantum well active region that is highly lattice-mismatched relative to a substrate. A buffer layer having a thickness above a critical value is grown on the substrate whereby the stress due to a lattice constant mismatch between the buffer layer and substrate is relieved through the formation of misfit dislocations. A strained superlattice structure is grown on the buffer layer in order to terminate any upwardly-propagating dislocations. An unstrained barrier layer is subsequently grown on the superlattice structure. The fabrication method concludes with the growth of a quantum well structure on the unstrained layer wherein a lattice constant mismatch between the quantum well structure and the unstrained barrier layer is smaller than the lattice constant mismatch between the quantum well structure and the substrate.

Abstract: A method for growing a superlattice structure on a substrate. First, a periodic array of monoatomic surface steps are created on the surface of the substrate at an area to have the superlattice structure grown thereon. There is apparatus for creating a beam of a material being input thereto and for selectively including or not including respective ones of a plurality of materials within the beam. The beam is directed at the steps of the substrate. Finally, logic causes control apparatus to include and not include respective ones of the materials within the beam in a pre-established pattern of time periods which will cause the materials to be deposited on the steps in a series of stacked monolayers. Tilted Superlattices (TSLs) and Coherent Tilted Superlattices (CTSLs) are created. The method can create pseudo ternary semiconductor alloys as part of a CTSL by employing at least two binary compound semiconductor alloys in the deposition process.

Abstract: An improved FET is disclosed. The transistor is characterized in that its channel is constituted in the form of a super lattice. The super lattice structure provides a number of square well potential areas through which carriers can pass with little interaction with the gate insulating film.

Abstract: An improved FET is disclosed. The transistor is characterized in that its channel is constituted in the form of a super lattice. The super lattice structure provides a number of square well potential areas through which carriers can pass with little interaction with the gate insulating film.

Abstract: An ion beam (113) focused into a diameter of at most 0.1 .mu.m bombards substantially perpendicularly to the superlattice layers of a one-dimensional superlattice structure and is scanned rectilinearly in a direction of the superlattice layers so as to form at least two parallel grooves (108, 109, 110, 111) or at least two parallel impurity-implanted parts (2109) as potential barrier layers, whereby a device of two-dimensional superlattice structure can be manufactured. At least two parallel grooves (114, 115, 116, 117) or impurity-implanted parts are further formed orthogonally to the potential barrier layers of the two-dimensional superlattice structure, whereby a device of three-dimensional superlattice structure can be manufactured. In addition, deposition parts (2403, 2404, 2405) may well be provided by further depositing an insulator into the grooves (108, 109, 110, 111, 114, 115, 116, 117) which are formed by the scanning of the ion beam.

Abstract: A method of producing a semiconductor laser including deposition a first film as a source of n type impurities on a portion of a semiconductor structure produced by growing at least a p type lower cladding layer, a quantum well active layer, and an n type upper cladding layer successively on a substrate, depositing a second film as a source of p type impurities at least on the surface of the semiconductor structure on both sides of and on the first film and annealing to diffuse p and n type impurities at the same time, thereby disordering portions of the quantum well except for the portion becoming an active region with p type impurities reaching at least the p type lower cladding layer, n type impurities reverting the portions of the n type cladding layer to which p type impurities have diffused to n type, and the n type impurities reaching the n type cladding layer but not reaching the active layer.

Abstract: A semiconductor wafer having an epitaxial GaAs layer, including a monocrystalline Si substrate having a major surface which is inclined at an off angle between 0.5.degree. and 5.degree. with respect to (100); and at least one intermediate layer epitaxially grown on the major surface of the monocrystalline Si substrate, as a buffer layer for accommodating a lattice mismatch between the Si substrate and the epitaxial GaAs layer which is epitaxially grown on a major surface of the top layer of the at least one intermediate layer. The at least one intermediate layer may comprise one or mor GaP/GaAsP, GaAsP/GaAs superlattice layers. the wafer may be used to produce a seimconductor light emitting element which has a plurality of crystalline gaAs layers including a light emitting layer epitaxially grown on the GaAs layer on the intermediate layer.

Abstract: A buried heterojunction semiconductor laser appropriate for integration with other electronic circuitry and method of producing same, in which the width of a central stripe of the active region can be reduced beyond the physical size limitations of the connecting electrode so as to allow the semiconductor laser to oscillate in a stable manner and with low threshold current. The semiconductor laser is provided with a portion of the surface of the upper cladding layer located above the disordered active layer regions electrically connected with the upper cladding layer located above the nondisordered central stripe. As a result, the central stripe electrode can be of a width larger than that of the central stripe itself.

Abstract: A composite buffer layer is formed with a layer of GaAs on a semi-insulating GaAs substrate. Next a short period superlattice is formed followed by another GaAs layer, whereon is formed a first AlGaAs layer having a first mole fraction of Al and a second AlGaAs layer having a second mole fraction of Al higher than the first mole fraction. As intrinsic GaAs channel layer is formed on the second AlGaAs layer.

Abstract: A semiconductor apparatus is disclosed, in which the entire or part of an electron active region is formed by a superlattice structure semiconductor layer in which a plurality of different semiconductor layers, less than 8 monolayers, and containing a fraction or a binary compound semiconductor layers are alternately and epitaxially grown and a main current direction is selected to be in the direction perpendicular to the laminae of said superlattice layers.

Abstract: A molecular beam epitaxy (MBE) process in which some portions of the substrate are shadowed by a shadow mask from receiving at least one of the molecular beams used in the MBE process. This process is capable of producing NIPI superlattices that have selective contacts that are far superior to those which can be produced at present. This technique can also produce a wide variety of NIPI devices as well as other types of IC structures.

Abstract: Different diffusion rates can be made operative relative to diffusion disordering in designated areas of a thin active layer or of quantum well feature compared to thermal disordering in other areas thereof where disordering is not desired by the selective placement of migratory defects in a semiconductor support means, such as a semiconductor substrate or semiconductor support layer for supporting subsequently epitaxially deposited semiconductor layers. Such migratory defects as used herein are intended to include impurities and/or other lattice defects initially introduced into the semiconductor support means prior to epitaxial deposition of semiconductor layers constituting the semiconductor structure, wherein at least one of such layers comprises a thin active layer (i.e.

Abstract: In a method for producing a spatially periodic semiconductor layer structure in the form of a superlattice composed of an alternating arrangement of strained semicondutor layers of at least two different semiconductor compositions forming at least one heterojunction, at least one of the semiconductor layers is provided with a doped layer which extends essentially parallel to the heterojunction and whose layer thickness is no greater than the thickness of the semiconductor layer in which it is produced.

Abstract: A semiconductor optical element having a layer which exhibits a function of diffraction grating between a first cladding layer and a second cladding layer, wherein the layer which exhibits the function of diffraction grating consists of a superlattice layer in which crystal layers are periodically mixed to constitute a semiconductor grating layer.

Abstract: Group III-V multi-alloy semiconductors, such as ternary, quaternary, and pentanary semiconductors, grown on a binary group III-V compound semiconductor substrate, are used as an active layer in opto-devices, high electron mobility transistors, etc. A method of growing multilayers, lattice-matched to the binary substrate and having specific energy band gaps, includes a molecular beam epitaxy (MBE) process. The present invention includes growing a quaternary or pentanary semiconductor layer using a minimum number of effusion cells and eliminating readjustment of molecular beam intensities from one layer to another layer during a series of epitaxial growth steps. As an example of quaternary growth, four effusion cells are utilized and two combinations of three effusion cells are alternately operated, one including an Al effusion cell and the other including a Ga effusion cell. Each of the three effusion cells is capable of growing a ternary semiconductor lattice-matched to the substrate.

Abstract: A method of forming a III-V semiconductor on the surface of a substrate which is placed in a vacuum chamber and is heated, by supplying one element of Group III and one element of Group V of the periodic table in the form of atoms or molecules to the surface of the substrate. The supply of the element of Group V is decreased to a small quantity insufficient to form a III-V compound semiconductor at least at one period of the growth of the III-V compound, and the element of Group V in the small quantity and the element of Group III are supplied to the surface of the substrate. This method makes it possible to grow III-V compound epitaxial layers which have a high degree of purity and fewer crystal defects and in which surfaces and the interfaces of the heterojunctions are flat on an atomic scale, at a wide temperature range. The present invention can be used for the fabrication of various optical devices and super-high-speed electronic devices.

Abstract: A component of semiconductor material deposited by epitaxial growth on a substrate having a predetermined and different lattice parameter consists of an alternate succession of layers of a first type and layers of a second type deposited on the substrate. The lattice parameter of the first type of layers is substantially matched with the lattice parameter of the substrate. In the case of the second type of layers, the lattice parameter is matched and even equal to that of the first type of layers. A component having a lattice parameter equal to that of the second type of layers is formed on the last layer of the second type. Moreover, the energy gaps of the two types of layers are different.

Abstract: A three dimensional, bipolar wafer process for integrating high voltage, high power, analog, and digital circuitry, and structure formed thereby includes a wafer of non-compensated epitaxial strata on a heavily donor doped monocrystalline silicon substrate of <100> crystal orientation, which is etched and with three dimensional transistors formed in it. Passivation for and contacts to said circuits are established, and the circuits are interconnected. The high voltage and high power transistors include transistors of an H-bridge circuit, including at least one set of cascode double heterojunction transistors, the analog transistors include a bipolar transistor, and the digital transistors include transistors of a I.sup.2 L circuit. One method for constructing the wafer is by sequentially epitaxially depositing each strata in an UHV silicon-based MBE apparatus.

Abstract: A semiconductor device comprising an epitaxially grown tin and Group IV compound semiconductor region on which at least one other semiconductor is grown lattice matched to the adjacent portion of the tin containing region. A large number of semiconductors may thus be grown.

Abstract: A process for fabricating a semiconductor-metal-semiconductor electronic device and the device formed thereby from a semiconductor substrate is described. The substrate forms a first active region of the device. A porous layer of conductive material is deposited on the substrate preferably by molecular beam epitaxy forming a control region. A layer of a semiconductor material epitaxially matched to the substrate is then grown on the layer of conductive material so that the layer of semiconductor material forms a second active region of an electronic device.

Abstract: A solar cell including at least a thin film formed of an amorphous silicon material and having p-type conductivity. The thin film comprises a multi-layer structure including at least one non-doped layer formed of a material of an amorphous silicon material and having a thickness of 10 to 300 .ANG. and at least one p-type doped amorphous silicon layer of a given thickness. The p-type doped amorphous silicon layer is stacked such that at least one face thereof is in contact with said at least one non-doped layer of amorphous silicon material so that the thin film of multi-layer structure exhibits in effect p-type conductivity.

Abstract: This absorbant is of the type formed by superlattice constituted by a stack of films of two different semiconductor materials having gaps of different heights. Thus, a potential well is produced in each film corresponding to the semiconductor with the smallest gap and a potential barrier in each film corresponding to the semiconductor with the largest gap. This saturatable absorbant is characterized in that the films corresponding to the semiconductor with the smallest gap have a thickness, which can assume two values, one small and the other large.Application in optics to the production of mode locking lasers and all optical logic gates.

Abstract: Superlattice doped layers for amorphous silicon photovoltaic cells comprise a plurality of first and second lattices of amorphous silicon alternatingly formed on one another. Each of the first lattices has a first optical bandgap and each of the second lattices has a second optical bandgap different from the first optical bandgap. A method of fabricating the superlattice doped layers also is disclosed.

Abstract: A photovoltaic device has a semiconductive multilayer of one conductivity type, which includes a plurality of amorphous thin constituent layers of different kinds stacked periodically to form at least one quantum well. A semiconductor layer of an i-type, which is contiguous to the multilayer so that light may be applied to the i-type layer through the multilayer.

Abstract: The superlattice type semiconductor material has a multilayered structure of first layers of semiconductor containing impurities and having a thickness thinner than electron or hole wavelength and second layers of semiconductor free from impurities or insulator having such a thickness that electrons or holes may penetrate by tunneling effect, the first and second layers being alternately piled. Electrons or holes distribute uniformly over the entire of the multilayered structure to show a property of uniform semiconductor material.

Abstract: A high surface area substrate with controlled pore size and slot geometry is used in an adsorbing process. The material is made by depositing at least two materials in alternating layers. The film is then broken up and one of the materials is etched away to produce a slotted surface structure. These slots can add size and shape selectivity to separations and catalytic processes which because of the uniform and controllable dimensions (>5A) would be superior to that obtainable from zeolites and clays.

Abstract: A semiconductor quantized layered structure comprising first and second different semiconductor materials comprising compound semiconductors from both the Group III and Group V elements and forming a plurality of alternate layers, each interfaced to its adjacent layer in a semiconductor homojunction or heterojunction. The bottom of the conduction bands of the first and second materials are at different energy levels and the tops of the valence bands of the first and second materials are at different energy levels. The bottoms of the conduction bands of the first and second materials form a plurality of serially arranged potential wells and barriers due to differences in the band structures of the different materials forming alternate layers and the interfacing of the layers forming heterojunctions so that the thinness of the layers will spatially localize electrons to obtain quantized electron states in one dimension transverse to the longitudinal extent of said layers.

Abstract: A semiconductor device which includes an active region including a superlattice amorphous material wherein the energy gap has a predetermined value. A preferred embodiment of the device is a solar cell. In another embodiment of the present invention, the device is a tandem solar cell which includes a first active region including a superlattice material wherein the bandgap has a first predetermined value; a second active region including a second superlattice material wherein the bandgap has a second predetermined value different from said first predetermined value; a means for electrically interconnecting said first and second active regions such that current may flow between said first and second active regions.

Abstract: The present invention teaches a process for fabrication of quantum-well devices, in which the quantum-wells are configured as small islands of GaAs in an AlGaAs matrix. Typically these islands are roughly cubic, with dimensions of about 100 Angstroms per side. To fabricate these, an n- on n+ epitaxial GaAs structure is grown, and then is etched to an e-beam defined patterned twice, and AlGaAs is epitaxially regrown each time. This defines the quantum wells of GaAs in an AlGaAs matrix, and output contacts are then easily formed.

Abstract: A layer of Cd.sub.x Hg.sub.1-x Te is grown on a substrate by growing layers of HgTe t.sub.1 thick, and CdTe t.sub.2 thick alternately. The thicknesses t.sub.1 and t.sub.2 combined are less than 0.5 .mu.m so that interdiffusion occurs during growth to give a single layer of Cd.sub.x Hg.sub.1-x Te. The HgTe layers are grown by flowing a Te alkyl into a vessel containing the substrate and filled with an Hg atmosphere by an Hg bath. The CdTe layers are grown by flowing of Cd alkyl into the vessel where it combines preferentially with the Te on the substrate. Varying the ratio of t.sub.1 to t.sub.2 varies the value of x. Dopants such as alkyls or hydrides of Al, Ga, As and P, or Si, Ge, As and P respectively may be introduced to dope the growing layer.

Abstract: A method for the growth of a compound semiconductor comprises growing on a silicon substrate a polycrystalline layer of a desired Group III-V compound semiconductor or a crystal layer of the desired Group III-V compound semiconductor having inferior crystallinity, growing on the formed layer at least one layer of the same semiconductor as the desired Group III-V compound semiconductor and at least one layer of a Group III-V compound semiconductor having a lattice constant approximating the lattice constant of the desired Group III-V compound semiconductor, which layers are alternately disposed, and growing on the alternately disposed layers a layer of the desired Group III-V compound semiconductor.

Abstract: A method is disclosed for growing an epitaxial layer composed of semiconductor material belonging to the cubic crystal system on a substrate, where the lattice constant of the epitaxial layer is graded from an initial lattice constant adjacent to the substrate to a final lattice constant on the surface of the epitaxial layer. Growth surfaces are formed on the substrate, and the epitaxial layer is grown as its lattice constant changes from the initial lattice constant to the final lattice constant.

Abstract: The mobility of a relatively narrow bandgap semiconductor material can be significantly enhanced by incorporating it into a multilayered structure (10) comprising a first plurality of relatively narrow bandgap layers (12) of the material and a second plurality of wider bandgap semiconductor layers (14) interleaved with and contiguous with the first plurality. The wide bandgap and narrow bandgap layers are substantially lattice-matched to one another, and the wide bandgap layers are doped such that the impurity concentration-thickness product therein is greater than the same product in the narrow bandgap layers. The fabrication of the structure by MBE to enhance the mobility of GaAs is specifically described. In this case, the narrow bandgap layers (12) comprise GaAs and are unintentionally doped to about 10.sup.14 /cm.sup.3, whereas the wide bandgap layers (14) comprise AlGaAs doped n-type to about 10.sup.16 to 10.sup.18 /cm.sup.3. The incorporation of this structure in an FET is also described.