Abstract: A method for producing a bipolar semiconductor device having a first layer doped according to a first doping type, the first layer being adapted to have minority charge carriers injected thereinto from a second layer of the device of a doping type opposite to that of the first layer in a forward conducting state of the device, comprises the steps of a) epitaxially growing the first layer and b) providing at least one region of the first layer with the minority charge carriers having a lifetime lower than in other parts of the first layer, the lower lifetime region of the first layer being formed directly during the epitaxial growth of this region by changing composition of substances fed to the first layer for the growth thereof when the region is grown.

Abstract: In a method of manufacturing a bipolar transistor by forming emitter regions of PNP and NPN transistors with diffusion of impurity from the polycrystalline silicon film into the substrate, the B-doped polycrystalline silicon film is deposited on the interlayer insulating film in which the emitter holes of the PNP and NPN transistors are made. Further, the interlayer insulating film is deposited on this film, and the portion of the insulating film which situated on the NPN transistor region is removed. Then, the thermal treatment is carried out in a high-concentration P atmosphere, so as to change the portion of the film which is located on the NPN transistor region to a P-doped polycrystalline silicon film. With this thermal treatment, the P-type and N-type emitter diffusion regions are formed on the base regions of the PNP and NPN transistors.

Abstract: The punchthrough capacity of a p-type semiconductor device is significantly improved by nonuniformly doping the p-channel with n-type implants such as phosphorus. The n-type dopants are implanted at large angles to form pocket implants within the channel region. The dose of the implants, angle of the implants and the thermal cycle annealing of the implants will be optimized for maximum punchthrough capability without substantially detracting from the performance of the semiconductor device.

Abstract: A method for making a NMOS self-aligned contact in CMOS circuits without an extra mask is described. The maskless contact technique makes use of the fact that the blanket N-type implant, self-aligned to exposed field-oxide edge, will not change the P+ diffusion to N-type. The net P+ concentration in the contact region is reduced slightly but does not degrade the PMOS device performance.

Abstract: A process for producing a semiconductor device having a structure in which a silicide film is in contact with an impurity diffusion layer inside a semiconductor substrate through a contact hole, in that, after the formation of the silicide film, an element of the same conductivity type as that of the impurity diffusion layer is implanted by ion implantation in the vicinity of the interface between the silicide film and the impurity diffusion layer through the silicide film.

Abstract: Disclosed is a method for forming a silicon dioxide layer on a substrate by radio-frequency deposition from a plasma comprising oxygen, argon, and tetraethyl orthosilicate (TEOS) or tetramethyl cyclotetrasiloxane (TMCTS). A negative bias is imparted to the substrate. The resulting ion bombardment induces surface migration. Because TEOS and TMCTS have a relatively high mean free path for surface migration, the filling of soft spots and key holes is promoted.

Abstract: III-V films are grown on large automatically perfect terraces of III-V substrates which have a different lattice constant, with temperature and Group II and V arrival rates chosen to give a Group III element stable surface. The growth is pulsed to inhibit Group III metal accumulation to low temperature, and to permit the film to relax to equilibrium. The method of the invention 1) minimizes starting step density on sample surface; 2) deposits InAs and GaAs using an interrupted growth mode (0.25 to 2 mono-layers at a time); 3) maintains the instantaneous surface stoichiometry during growth (As-stable for GaAs, In-stable for InAs); and 4) uses time-resolved RHEED to achieve aspects (1)-14 (3).

Abstract: A method for manufacture of a semiconductor wafer in a manner to attain a high uniformity in the thickness of a semiconductor layer, by first forming hardly polishable stoppers of mutually different thicknesses in the semiconductor, then polishing the semiconductor until the thicker stopper is exposed on one main surface of the semiconductor, subsequently removing the thicker stopper to attain a thickness less than that of the thinner stopper, and thereafter polishing the aforesaid one main surface of the semiconductor until the thinner stopper is exposed. There is also disclosed a semiconductor device of a quantum well wire structure comprising a semiconductor layer formed on an insulator substrate, a thermally oxidized film of the semiconductor layer formed on such layer, and a gate electrode fromed on one side of the semiconductor layer, wherein the channel width is determined by the thickness of the semiconductor layer.

Abstract: A TFT is fabricated by providing on a substrate (10), and over a gate (12), a sequentially formed multi-layer structure consisting of a gate insulator layer (14), an intrinsic semiconductor, e.g. a-Si or polysilicon, layer (16) for the channel, a doped semiconductor, e.g. n type a-Si or polysilicon, layer (18) for source and drain contact regions and a passivating layer (20). The layer (18) extends completely over and covers the channel region of the layer (16). Thereafter, the portion (30) of layer (18) overlying the channel region is converted by a compensating doping implant to a highly resistive form separating the source and drain contact regions, and windows (22, 24) are defined in the passivating layer (20) into which source and drain contacts (26, 28) are deposited. In this way critical interfaces are protected from contamination. The TFT is suitable for use as a switching element in active matrix display devices, e.g. LC-TVs.

Abstract: A blanket boron implant that functions as both a punchthrough and field-isolation implant for sub-micron N-channel CMOS devices. The boron impurity is implanted with high energy subsequent to field oxide growth in order to position the impurity below the field oxide regions and below the future channel region of the N-channel devices. In order to avoid significant counter-doping of the substrate in the N-well regions, the phosphorus dosage during the N-well implant is at a much higher dosage level than the dosage level used for the punchthrough/field isolation implant.

Abstract: The present invention relates to a method of producing a metal-oxide semiconductor device with improved capacity for preventing an actuation of a parasitic bipolar transistor. In the present invention, a metal-oxide seminconductor device is produced through a process in which a single conductive semiconductor region with low-impurity density, on top of which region a gate electrode is provided via a gate-insulating film, consists of two sub-layers with different specific resistance. The upper sub-layer of the region has a significantly lower specific resistance than the lower sub-layer of the region. When a lifetime-reducing agent for reducing the reverse-recovery time of a built-in diode is diffused into the single conductive semiconductor region with low-impurity density, the lifetime-reducing agent concentrates in the upper sub-layer of the region, thereby increasing the specific resistance of the upper sub-layer.

Abstract: A first semiconductor layer of a P.sup.+ type is formed on a semiconductor substrate of a P.sup.- type and a mask layer is formed on a portion of the first semiconductor layer other than that area where a capacitor is to be formed. A hole is formed in a direction of a thickness of the first semiconductor layer, using the mask layer. An N.sup.+ is formed on the inner surface of the hole with the mask layer as a mask. An insulating film for capacitor formation is formed on the inner surface of the resultant hole and on that atea of the first semiconductor layer where the resultant dynamic memory cell is electrically separated from an adjacent dynamic memory cell. A conductive layer acting as a capacitor electrode is formed on the capacitor formation insulating film. With the conductive layer as a mask, an impurity of an N type is doped into the first semiconductor layer to form a second semiconductor layer of a P.sup.- type in the surface portion of the first semiconductor layer.

Abstract: Method of counteracting the effects of undesired contaminants in an amorphous semiconductor, and the resulting semiconductor product. An overcompensating agent is incorporated in the semiconductor in a restricted or limited region which is less than the entirety of the semiconductor body. The semiconductor is desirably of amorphous silicon. The undesired contaminant is a p acceptor and the compensating dopant is an n donor. Alternatively, the undesired contaminant can be an n donor and the compensating dopant can be a p acceptor. Typical p acceptors are residual boron and typical n donors are phosphorous. The compensation takes place over the range from about 1 to about 25% of the maximum thickness of the region of compensation. The compensating dopant is present in a limited amount ranging from about 1 part to about 50 parts per million.

Abstract: In a method of electrically altering the characteristics of a semiconductor device, a lateral polysilicon zener diode's zener knee voltage may be shifted either to a higher or lower voltage. An electrical potential may be applied in the forward direction to shift the zener knee to a higher voltage level. An electrical potential may be applied in the reverse bias direction to shift the zener knee to a lower voltage. In the limit, the zener may be changed into a forward diode of reverse polarity with respect to the original zener. The electrical potential used should be of appropriate magnitude to melt the polysilicon without damage to the zener's terminals. This induces migration of the impurities causing a rediffusion of impurities thereby altering the characteristics of the diode. This method may be used to program a PROM by either converting the zener to a diode or not to program each binary bit.

Abstract: A method of producing II-V compound semiconductors with greatly reduced intrinsic defect levels comprises the step of causing atoms or ions of at least one member selected from the group consisting of hydrogen and the halogens to be injected into and diffused through II-V compound semiconductors during or after the production thereof.

Abstract: The surface of the channel and top gates of N channel IGFETS and JFETS respectively are compensated after a high temperature processing by ion implanting boron through a protective layer. The peak impurity concentration is to occur in a sacrificial gate pad oxide layer to ensure a predictable dopant concentration in the substrate.