Abstract: Form a butted contact in an SRAM memory device by exposing a contact region on the surface of a doped semiconductor substrate and a conductor stack above a field oxide region on the surface of the substrate. Form an interpolysilicon silicon oxide dielectric layer over the device with an opening framing the contact region and the butt end of the conductor stack near the contact region. Form an undoped upper polysilicon layer on the surface of the SRAM device covering the dielectric layer, the contact region, and the butt end of the conductor stack and then patterned into interconnect and load resistance parts. Form a Vcc mask on the surface of the undoped upper polysilicon layer with a window framing the dielectric layer, the contact region, and the butt end of the conductor stack, leaving an exposed region of the undoped upper polysilicon layer.

Abstract: A removable oxide spacer is used to reduce the size of a contact opening in a memory cell between polysilicon word lines below a lithographic minimum. The removable spacer is deposited before the buried contact patterning and etching. Since word lines diverge at a cell location, the removable spacer retains a lesser thickness over the divergent area contact opening and a greater thickness elsewhere between word lines due to the more narrow gap therebetween and the spacer being deposited such that it fills the gap. The removable spacer reduces the buried contact size since the actual self-aligned contact area is defined by the spacer sidewall. The removable spacer is formed of materials having higher etching selectivity relative to materials forming underlying structures. Etching of the spacer creates a buried contact opening smaller than a lithographic minimum because silicon oxide surrounding the buried contact area is protected by the removable spacer.

Abstract: A technique to form a structure with a rough topography (415) in a planarized semiconductor process. The rough topography (415) is formed by creating cored contacts (433). Subsequent process layers may be further stacked on top of the cored contacts in order to augment the nonplanar characteristics of the cored contacts. This rough topography structure may be used to align integrated circuits and wafers. An integrated circuit may be laser aligned using this alignment structure.

Abstract: A method for forming an SRAM cell, on a semiconductor substrate, comprised of MOSFET devices, and polysilicon load resistors, has been developed. The process for forming the SRAM cell features the use of two, self-aligned contact, (SAC), structures, a polycide SAC structure, used for contact to a source region of a MOSFET pull down transistor, and a tungsten SAC structure, used for contact to a source region of a MOSFET pass gate transistor. A buried contact region is also featured in this SRAM design and fabrication procedure, used to connect underlying active device regions, of MOSFET pull down transistors, and MOSFET pass gate transistors.

Abstract: A relatively easy manufacturing method of a semiconductor device enabling a contact hole 25 to be formed reliably by self alignment without exposing a gate 11, wherein a plug 20 is adopted to protect an etching stopper film 16 from an etching gas when a preliminary opening 24 is formed by etching an insulating film 22 having an electrical insulating etching stopper film 16 embedded therein.

Abstract: A semiconductor device capable of stably operating even at a low voltage, incudes: a semiconductor substrate having a surface region of a first conductivity type; a conductive film directly formed on a surface of the surface region at an area thereof, the conductive film containing impurities of a second conductivity type opposite to the first conductivity type; an oozed diffusion region of the second conductivity type formed by diffusion of the impurities in the conductive film into the substrate, the oozed diffusion region being formed at an area contiguous to the conductive film in the surface region; a low resistivity region of the second conductivity type extending from an area adjacent to the conductive film in the surface region and overlapping the conductive film; and a DDD structure transistor formed on another region of the surface region, wherein a length of a portion of the low resistivity region overlapping the conductive film is substantially the same as a length of a portion of the deep source

Abstract: A new method of forming an improved buried contact junction is described. Word lines are provided over the surface of a semiconductor substrate. A first insulating layer is deposited overlying the word lines. The first insulating layer is etched away where it is not covered by a buried contact mask to provide an opening to the semiconductor substrate. A layer of tetraethoxysilane (TEOS) silicon oxide is deposited over the first insulating layer and over the semiconductor substrate within the opening. The TEOS layer is anisotropically etched to leave spacers on the sidewalls of the word lines and of the first insulating layer. A first layer of polysilicon is deposited overlying the first insulating layer and within the opening. The first polysilicon layer is doped with dopant which is driven in to form a buried contact junction within the semiconductor substrate under the opening.

Abstract: A method of fabricating flat-cell mask ROM devices having buried bit-lines that will not be subject to punch-through between neighboring bit lines as a result of heating in subsequent steps after the buried bit-lines are formed. In the method, the first step is to prepare a semiconductor substrate with a gate oxide layer formed thereon. Thereafter, a first polysilicon layer is formed over the gate oxide layer, and a plurality of trenches at predetermined positions, with these trenches extending through the gate oxide and first polysilicon layer and into the substrate to a predetermined depth. Then, trenches are filled with tungsten to form a plurality of source/drain regions. A second polysilicon layer is then formed over the first polysilicon layer, and an insulating layers is formed over each of the source/drain regions.

Abstract: In a method for manufacturing a contact structure, a first insulating layer, a first conductive layer and a silicon nitride layer are sequentially formed on a semiconductor substrate. The silicon nitride layer and the first conductive layer are anistropically etched with a first pattern mask. A sidewall of the first conductive layer is oxidized. A second insulating layer is formed on the entire surface, and a contact hole is perforated in the first and second insulating layers. Finally, a second conductive layer is buried in the contact hole.

Abstract: A shared contact structure (30) is formed to electrically connect three coupling layers (59,60,46) to each other and to an active region (33) in a semiconductor substrate (31). A first coupling layer (59) and a second coupling layer (60) are formed such that they are physically isolated from each other. The second coupling layer (60) is formed such that it is in physical contact with the active region (33). A contact opening (45) is formed, which exposes a portion of coupling layers (59, 60). The third coupling layer (46) is then formed so that it is in electrical contact with the second coupling layer (60) and the first coupling layer (59).

Abstract: A removable oxide spacer is used to reduce the size of a contact opening in a DRAM cell between polysilicon word lines below a lithographic minimum. The removable spacer is deposited before the buried contact patterning and etching. Since word lines diverge at a cell location, the removable spacer retains a lesser thickness over the divergent area contact opening and a greater thickness elsewhere between word lines due to the more narrow gap therebetween and the spacer being deposited such that if fills the gap. The removable spacer reduces the buried contact size since the actual self-aligned contact area is defined by the spacer sidewall. Etching of the spacer creates a buried contact opening smaller than lithographic minimum because silicon oxide surrounding the buried contact area is protected by the removable spacer. The removable spacer is removed after resist strip leaving a sublithographic buried contact opening.

Abstract: A method of forming a local interconnect in an SRAM, simultaneously with the formation of a salicide in logic devices on the same semiconductor substrate, is described. A semiconductor substrate on which MOS (Metal Oxide Semiconductor) transistors have been formed is provided. The transistors are separated by field isolation regions, and each transistor has a gate overlying a gate oxide and has source and drain regions in the substrate. Spacers are provided on the sidewalls of the gates, and some of the field oxide regions in the SRAM have polysilicon interconnects, with sidewall spacers. The sidewall spacers are removed from the polysilicon interconnects. A layer of titanium is deposited over the semiconductor substrate. A salicide is formed over the gates, the source and drain regions, and the polysilicon interconnects, so that the local interconnect is formed connecting the polysilicon interconnects to one of the source regions.

Abstract: A method for reducing the contact resistance of an overlying metal bit line structure, to underlying polycide gate structure, has been developed. A borderless, or non-fully landed contact hole, is opened in an insulator layer, to expose the top surface of the underlying polycide gate structure. The anisotropic, dry etching of the insulator is then continued, resulting in the exposure of a portion of the sides of the polycide gate structure. A subsequent bit line metal structure, now contacts both the top surface, as well as a portion of the sides, of the polycide gate structure, resulting in a contact resistance reduction, due to the increased contact area.

Abstract: A method of forming an FET device starts by forming a sacrificial layer over a semiconductor substrate and an outer buried contact region is produced by ion implantation into the substrate, followed by stripping the sacrificial layer, forming a gate oxide layer, and depositing polysilicon over the gate oxide layer. Then, etch an inner buried contact opening through the polysilicon and the gate oxide layer down to the substrate over the outer buried contact region forming an etched buried contact opening. Implant dopant into the substrate through the inner buried contact opening in the second mask to dope the substrate forming the inner buried contact region within the outer buried contact region self-aligned with the etched buried contact opening. Form a blanket, second polysilicon layer over the gate oxide layer reaching down through the etched buried contact opening into electrical and mechanical contact with the inner buried contact region.

Abstract: An SRAM transistor cell on a doped semiconductor substrate comprises two access FET transistors and two storage FET transistors. A first load capacitor has a plate connected to a first node with the other plate connected to the power supply. A second load capacitor has a plate connected to the second node with the other plate connected to the power supply, a bit line and a bit line bar. The first storage transistor drain connects to the first node. The second storage transistor drain connects to the second node. The storage transistors have interconnected sources. The first node connects via a first interconnection line to the second transistor gate. The second node connects via a second interconnection line to the first transistor gate. First and second access transistor gates connect to a wordline. The first access transistor drain connects to the first node. The second access transistor drain connects to the second node. The first access transistor source connects to the bit line.

Abstract: A semiconductor device, wherein an electrode wiring, which is in contact with semiconductor layers of mutually different conductive types and serves to connect at least he layers of mutually different conductive types, comprises a first portion principally composed of a component same as the principal component of the semiconductor layers, and a second portion consisting of a metal.

Abstract: A trench isolation region (32) is fabricated to include a trench liner (28) comprised of aluminum nitride. The aluminum nitride trench liner is useful in borderless contact applications wherein a contact opening (56) is etched in an interlayer dielectric (54) and overlies both an active region. (e.g. doped region 52) and the trench isolation region. During formation of opening using etch chemistry which is selective to aluminum nitride, the trench liner protects a P-N junction at a corner region (58) of the trench to prevent exposing the junction. By protecting the junction, subsequent formation of a conductive plug (60) will not electrically short circuit the junction, and will keep diode leakage to within acceptable levels.

Abstract: A method is provided for fabricating totally self-aligned contacts on semiconductor substrates. The method is particularly applicable to dynamic random access memory for reducing the cell area. The method involves patterning the silicon nitride layer for the local oxidation of silicon (LOCOS) process to provide wide device areas for the gate electrode of the FETs, and narrow device areas adjacent and contiguous to the wide device areas on and in which are formed portions of the source/drain areas and the totally self-aligned contacts. The lateral encroachment of the field oxide (bird's beak) into the narrow device areas during the LOCOS process reduce the width of the area to about 0.20 um, and thereby extend the resolution limit of the current lithography (about 0.40 um) used to define the nitride layer.

Abstract: A new method of forming improved buried contact junctions is described. A buried contact is formed within a semiconductor substrate by dopant diffusion from an overlying polysilicon layer. The second polysilicon layer is patterned to form a polysilicon contact overlying the buried contact junction wherein a portion of the buried contact within said semiconductor substrate is exposed. The polysilicon layer is overetched whereby a trench is etched into the exposed semiconductor substrate. An extra implant is implanted into the semiconductor substrate around the trench. Source and drain regions are formed wherein the buried contact connects to one of the source and drain regions through the extra implant around the trench completing the formation of the buried contact in the fabrication of an integrated circuit.

Abstract: A removable oxide spacer is used to reduce the size of a contact opening in a DRAM cell between polysilicon word lines below a lithographic minimum. The removable spacer is deposited before the buried contact patterning and etching. Since word lines diverge at a cell location, the removable spacer retains a lesser thickness over the divergent area contact opening and a greater thickness elsewhere between word lines due to the more narrow gap therebetween and the spacer being deposited such that if fills the gap. The removable spacer reduces the buried contact size since the actual self-aligned contact area is defined by the spacer sidewall. Etching of the spacer creates a buried contact opening smaller than lithographic minimum because silicon oxide surrounding the buried contact area is protected by the removable spacer. The removable spacer is removed after resist strip leaving a sublithographic buried contact opening.

Abstract: A semiconductor processing method of forming a stacked container capacitor includes, a) providing a pair of spaced conductive runners relative to a substrate, the conductive runners respectively having electrically insulative sidewall spacers and an electrically insulative cap, the caps having respective outer surfaces; b) providing a node between the runners to which electrical connection to a capacitor is to be made; c) providing an electrically conductive pillar in electrical connection with the node, the pillar projecting outwardly relative to the node between the runners and having a first outer surface positioned outwardly of both runner caps, the pillar completely filling the space between the pair of runners at the location where the pillar is located; d) providing an insulating dielectric layer outwardly of the caps and the conductive pillar; e) etching a container opening through the insulating dielectric layer to outwardly expose the conductive pillar first outer surface; f) etching the exposed con

Abstract: A method for fabrication of polysilicon buried contacts is described which overcomes the problems of current leakage which occur at sub-micron spacings between these contacts. The failure of the conventional channel stop protection at these spacings is compensated for by performing the buried contact anti-punchthrough ion-implant using large-angle-tilt (LAT) implantation. This provides adequate dopant under the edge of the field oxide to eliminate excessive current leakages between buried contacts at sub-micron spacings. The method is particularly effective in the manufacture of static random access memories (SRAMs) where such sub-micron spacings occur to a large degree.

Abstract: A method for fabricating a novel plug structure for low resistance ohmic stacked contacts and at the same time forming metal contacts to devices on a SRAM cell was achieved. The method involved forming electrically conductive plugs in the stacked contact openings to form ohmic connections between a P+ doped polysilicon layer and a N+ doped polysilicon layer and thereby increasing the on current (I.sub.on) of the SRAM cell. The electrical conductive plugs are also simultaneously formed in metal contact openings to devices areas elsewhere on the substrate. The process for the plug structure also reduces the mask set by one masking level over the prior art process.

Abstract: An SRAM cell includes a semiconductor substrate doped with a dopant of a first type, a highly doped region in the substrate implanted with a dopant of opposite type, a gate oxide layer on the substrate, a first conductive layer formed upon the gate oxide layer, a dielectric layer deposited over the first conductive layer, an opening in the gate oxide layer, the first conductive layer, and the dielectric layer, and a second conductive layer deposited upon the dielectric layer.

Abstract: A method of forming a metal plug, including a step of flattening by polishing the surface of a contact plug which is formed by etching back a metal layer, for example, a deposited layer of Blk-W on a substrate. It also makes it possible to print a wiring metal layer by a lithographic process which has thus far been considered difficult to apply to Blk-W. In the method of the invention, a contact hole 3 is opened in an insulation film layer 2 on a substrate 1, and, after coating an adhesion layer 4, a metal layer 5 is deposited on the entire surface. Thereafter, the surface of the metal layer 5 is flattened by a polishing operation, and etched back to form a metal plug 7.

Abstract: A semiconductor integrated circuit, and process for its manufacture, are disclosed which contains both n.sup.+ and p.sup.+ gates that do not pose a risk of dopant interdiffusion. Both n.sup.+ and p.sup.+ gates may be fabricated by conventional means. The gate structures are severed over the tub boundaries. A titanium nitride interconnective layer is deposited and patterned over the gates. The interconnective layer preserves connectivity between the n.sup.+ and p.sup.+ gates without risk of deleterious dopant interdiffusion.

Abstract: In a method of forming an adhesive layer for a blanket layer filling a contact hole in a semiconductor device, a Ti film, Ti-rich TiN film or a TiSi.sub.x (x being 1.1 to 1.8) film is formed, and then a TiN (stoichiometric) film is formed. The Ti film, Ti-rich TiN film or TiSi.sub.x is annealed to be converted into TiSi.sub.2 film. The formation of the Ti film, Ti-rich TiN film or a TiSi.sub.x is performed by a continuous CVD process.

Abstract: The back contact of a silicon die consists of a pure aluminum contact, alloyed into the back surface of the silicon. The back surface need not be subjected to a grinding operation. The aluminum is deposited by an E-beam deposition process. The aluminum is alloyed into the silicon at a temperature lower than the melting point of pure aluminum, but higher than the melting point of a silicon-aluminum eutectic. Aluminum, nickel and silver are thereafter E-beam deposited, in sequence, on the aluminum surface and are sintered.

Abstract: The present invention encompasses a method for providing the same ohmic material contact (120, 122, 124) to N-type and P-type regions (70, 80) of a III-V semiconductor device. Specifically, an N-type region (70) extending through a semiconductor structure is formed. Additionally, a P-type region (80) extending through the substrate is formed. The P-type region (80) may be heavily doped with P-type impurities (81). A first ohmic region (117) is formed, contacting the N-type region (70). The first ohmic region may comprise an ohmic material including metal and an N-type dopant. A second ohmic region (119) is formed, contacting the P-type region (80, 81). The second ohmic region comprises the same ohmic material as the first ohmic region. One ohmic material that may be used is nickel-germanium-tungsten.

Abstract: A method for making a contact hole during manufacture of a semiconductor device.

Abstract: A method for forming contact of a semiconductor device which prevents residues of a conductive material due to high steps on an insulating layer between metal lines, and minimizes contact area, includes the steps of forming an impurity diffusion region on a predetermined portion of an isolation region on a substrate, forming a first insulating layer on the surface of the substrate, forming a first conductive pattern and a second insulating pattern on the upper portion of the first insulating layer, forming a barrier pattern on the upper portion of the second insulating pattern, forming a third insulating layer on the upper portion of the barrier pattern and the first insulating layer, and etching the third insulating layer to expose the upper portion of the barrier pattern, forming a photoresist pattern for contact mask on the surfaces of the barrier pattern and third insulating layer, etching the third insulating layer and first insulating layer exposed by the photoresist pattern to form a contact hole havin

Abstract: In forming a semiconductor integrated circuit device, a field insulation film is formed on a substrate using a selective thermal oxidation process whereby openings are formed in the insulation film thereby exposing the substrate at certain predetermined active regions. A patterned insulation film is formed on the field insulation film so as to present contact holes corresponding to the openings in the field insulation film. Each of the contact holes has a first pair of opposed edges extending in a first direction and defined by interior edges of the field insulation film and a second pair of opposed edges extending in a second direction and defined by edges of the patterned insulation film. The resultant structure provides a reduced pitch of the contact holes in the second direction.

Abstract: A method of forming a self-aligned trenched contact in the fabrication of an integrated circuit is described. Semiconductor device regions are formed in and on a semiconductor substrate wherein the semiconductor device regions include gate electrodes on the surface of the semiconductor substrate and source/drain regions within the semiconductor substrate. Spacers are formed on the sidewalls of the gate electrodes. A layer of silicon oxide is deposited over the surface of the substrate wherein the silicon oxide contacts the source/drain regions within the substrate between the gate electrodes. The substrate is covered with a layer of photoresist which is patterned to provide an opening over the planned self-aligned trenched contact between the gate electrodes. The silicon oxide is etched away to provide an opening to the silicon substrate using the patterned photoresist and the sidewall spacers as a mask.

Abstract: The present invention provides a III-V semiconductor FET (10, 30, 40) having etched ohmic contacts (19, 20, 36, 37, 43, 44). A gate (16) of the FET (10, 30, 40) is formed in contact with a surface of a III-V substrate (11). An ohmic contact (19, 20, 36, 37, 43, 44) is created to include an alloy in contact with the surface of the substrate (11). The ohmic contact (19, 20, 36, 37, 43, 44) is formed to abut the gate structure (16, 17, 18) by covering a portion of the gate structure (16, 17, 18) and the substrate (11) with the ohmic contact (19, 20, 36, 37, 43, 44), then, removing portions of the ohmic contact from the gate structure (16, 17, 18) by etching. The ohmic contact (19, 20, 36, 37, 43, 44) is formed to be substantially devoid of gold.

Abstract: The present invention includes forming an etched ohmic contact (10, 9) by applying a layer of an etch susceptible contact material (14) to a III-V semiconductor substrate (11). A portion of the contact layer (14A) is alloyed with the substrate (11) to form are etch resistant area (14A) of the contact layer. The contact layer (14) is selectively etched to remove etch susceptible portions of the contact layer while leaving the etch resistant area (14A) on the substrate (11). Another alloy operation is performed to form ohmic contact between the etch resistant area (14A) and the substrate (11). Consequently, an etch ohmic contact (10, 9) that is substantially devoid of gold is formed.

Abstract: A semiconductor connecting device and a method for making the same are disclosed. The semiconductor connecting device is comprised of a device separation insulating film, a source region and a drain region formed at predetermined portions of a semiconductor substrate; an interlayer insulating film formed on the device separation insulating film and on the drain region, having a contact hole through which a portion of the device separation film are exposed along with a portion of the drain region; a conductive plug formed on the exposed portion of the drain region and on the exposed portion of the drain region within the contact hole, the drain region-sided conductive plug being thinner than the device separation insulating film-sided one; and bit lines formed on the conductive material plug and the interlayer insulating film, coming into contact with them, respectively.

Abstract: A contact of a semiconductor device and its manufacturing process are disclosed. A first conducting line, a first insulating layer, and a second conducting line are formed sequentially on a semiconductor substrate. And then, a second insulating layer is deposited on the substrate and photomasking process for making a contact is proceeded. A contact hole is formed by etching sequentially portions of the second insulating layer, the second conducting line, and the first insulating layer in order to expose a portion of the first conducting line. Thereafter, conductive material for a contact plug is filled in the contact hole in order to connect the first conducting line to the second conducting line.

Abstract: A method of manufacturing a semiconductor device includes the steps of: forming a gate electrode and a wiring layer on a silicon oxide film formed on the surface of a semiconductor substrate, by using conductive material; forming a diffusion region on the surface of the semiconductor substrate by implanting impurities into the semiconductor substrate at an area other than the gate electrode and the wiring layer; and forming a film for electrically interconnecting the diffusion region and the wiring layer, using conductive material.

Abstract: An ohmic contact to a III-V semiconductor material is fabricated. First, a III-V semiconductor material is provided. Source/drain regions are then formed in the III-V semiconductor material. On the III-V semiconductor material, a contact system is formed which is dry etchable using reactive ions such as chlorine or fluorine and substantially free of arsenic. Subsequently, a portion of the contact system is dry etched using reactive ions such as chlorine or fluorine to leave a portion of the contact system remaining on the source/drain regions. Then, the III-V semiconductor material and the contact system are annealed in an atmosphere substantially free of arsenic at a temperature at which at least a part of the contact system is alloyed with the source/drain regions to form an ohmic contact with the source/drain regions of the III-V semiconductor material.

Abstract: Described herein is a method for forming a barrier metal structure in a minute contact hole in such a way as to ensure good coverage by the metal.The method of the invention comprises the steps of: opening a contact hole in an insulation film layer on a substrate in a diameter larger than an originally intended target value; forming a barrier metal layer over the entire surfaces of the insulation film layer; forming an oxidation film layer over the entire surfaces of the barrier metal layer until the diameter of the contact hole reaches the original target value; etching the oxidation film layer by anisotropic etching; and embedding a metal in the contact hole. Further, after forming a metal plug, the barrier metal layer may be selectively etched back in such a way as to leave a barrier metal layer only at the bottom of the contact hole.

Abstract: A method for dielectrically isolating a semiconductor integrated circuit is provided. Each integrated circuit is substantially surrounded by silicon oxide sidewalls which have been appropriately doped to be of an opposite conductivity type as the surrounding substrate. The doped silicon oxide sidewalls are formed prior to the growth of epitaxial silicon within the sidewalls. Upon deposition of the epitaxial silicon the dopant within the oxide sidewalls diffuses into the adjacent epitaxial silicon, thereby resulting in a heavily doped, low resistivity region of epitaxial silicon adjacent to and along the entire length of the oxide sidewall. This heavily doped region results in the substantial elimination of charge-depleting parasitic currents along the sidewalls during use of the integrated circuit. In addition, the heavily doped, low resistivity epitaxial region provides an electrically conductive contact to a buried layer within an integrated circuit having such a buried layer.

Abstract: A contact is formed in a semiconductor device (10), independent of underlying topography or pitch. In one method of the present invention, an insulating layer (18) is deposited over a semiconductor substrate (12). An etch stop layer (20) is deposited over the insulating layer. A frame structure (22) is formed on the etch stop material and defines at least one contact region (23 and/or 25) within which the etch stop material is exposed. The exposed portions of the etch stop material are removed from the contact region to expose a portion of the insulating layer. The exposed portion of the insulating layer is then anisotropically etched and at least one contact (30 and/or 32) is formed in the contact region. Depending on where the contact region is positioned, either a self-aligned contact or a non-self-aligned contact may be formed, or both types of contacts may be formed simultaneously.

Abstract: Adjacent buried contacts (11, 12, 13) formed at the principal surface of a well or substrate region (14) of a semiconductor device, each having a doped contact region (29, 30 31) of one conductivity type and a punch-through prevention region (36, 37, 38) of the opposite conductivity type surrounding the lower portion of the doped contact region are provided. The punch-through prevention region may advantageously be of the same conductivity type as the substrate. By performing an extra implant or other impurity introduction step while the mask to etch the contacts through the dielectric layer remains in place, the procedure to provide punch-through protected buried contacts may be easily integrated into current processes without the need for an extra mask. Such a structure and procedure enables buried contacts to be spaced closely together without over-doping the well region (14) in which source-drain regions (40, 42, 44, 46) are also formed thus avoiding a degradation in device performance.

Abstract: A process for implementing logic units using base cells and implementing an electrical connection between the logic units in a gate array. The process includes determining a connection path between the base cells and connecting the base cells at the second metalization layer using a portion of the first metalization layer. This is possible due to the gate array having vertical first metalization layer segments of the first metalization layer positioned vertically in the channel between the rows of base cells, wherein each of the vertical segments has vias in the insulation layer between the first metalization layer and the second metalization layer at its endpoints for connecting the metalization layers. Similarly, the individual transistors which comprise the base cell are coupled using the second metalization layer to implement a specific logic unit.

Abstract: An improved process is described for depositing TiW/TiWN/TiW/Au metallization which provides superior adhesion properties, excellent barrier properties and which is suitable for use with metal line widths of the order of one micron or smaller. It is important in order to obtain these properties to ensure that the layer immediately underlying the gold layer by substantially pure TiW deposited in a nitrogen free sputtering atmosphere. To this end, the gas supply manifolds and deposition chamber are purged and the chamber evacuated following deposition of the TiW layer and prior to deposition of the TiWN layer underlying the gold layer. A final TiW layer is also conveniently placed on top of the gold layer to act as an etching mask.

Abstract: A process for fabricating a integrated circuit (IC), including a plurality of devices coupled together by a system of metal interconnects disposed above a semiconductor substrate comprises the steps of forming a plurality of conductive pedestals on the surface of the substrate. A portion of the pedestals form electrical contacts to the devices, wherein the height of the pedestals is higher than any feature of the substrate. After a polyimide layer is deposited on the substrate to a thickness which covers the pedestals, an etching step is performed until the top surface of the pedestals is coplanar with the polyimide layer. A set of metal interconnect lines is then formed over the polyimide and pedestals to form electrical connections to selected ones of the pedestal contacts.

Abstract: For integrated circuit devices with strict design rules, junctions defining the source and drain are typically more shallow than 0.25 .mu.m and are made through vias having an aspect ratio greater than 1.1. Suitable electrical contact to such a shallow junction is quite difficult. To ensure an appropriate contact, an adhesion barrier layer such as titanium nitride or an alloy of titanium and tungsten is first deposited. Tungsten is then deposited under conditions which produce a self-limiting effect in a prototypical deposition on silicon. Additionally, these tungsten deposition conditions are adjusted to higher rather than lower deposition temperatures. Subsequent deposition of aluminum if desired, completes the contact.

Abstract: A method of applying an alloy layer of predetermined thickness on a semiconductor wafer to fill contact openings having a defined diameter, the method comprising the following steps:chemical vapor depositing (CVD) a layer of elemental metal atop the wafer to a thickness of from 5% to 35% of the defined contact diameter;sputtering a layer of an alloy atop the chemical vapor deposited layer of elemental metal to a thickness which results in the combination of the chemical vapor deposited and sputtered layers having substantially the predetermined overall layer thickness; andcombining and intermixing the sputtered alloy layer with the chemical vapor deposited elemental metal layer to form an overall homogenous alloy layer by applying energy to the sputtered alloy layer, the application of energy also filling contact openings and planarizing the homogenous layer.Preferably, the CVD layer has a thickness of from 10% to 20%, and the energy is applied by a scanning pulsed laser.

Abstract: The sub-micron NMOS, PMOS and CMOS devices with methods for forming sub-micron contacts provide sub-micron devices and processes for manufacturing them with contacts down to 0.1 microns or less. All processes and devices utilize doped polysilicon as the electrodes for the device elements, and the preferred embodiment surrounds the polysilicon contacts with low temperature oxide covered by SOG which avoids all oxidation steps that could be detrimental in this contact size range. An optional alternative includes large contact area enlarging layers of silicide directly beneath each contact.

Abstract: A method of manufacturing a semiconductor device having a semiconductor substrate of a first conductivity type, an N-type diffusion layer formed in the substrate, and a P-type diffusion layer formed in the substrate. Two contact holes are formed in separate steps, thus exposing the N-type diffusion layer and the P-type diffusion layer, respectively. Hence, when one of the diffusion layers is again doped with an impurity, or again heat-treated, the other diffusion layer is already protected by inter-layer insulation film. Therefore, the impurity cannot diffuse into the contact formed in the contact hole made in the other diffusion layer. As a result of this, SAC technique can be successfully achieved, without deteriorating the characteristic of the contact.