Abstract: A method of fabricating a semiconductor device. The procedure of fabricating process is performed inversely as the conventional method. Less numbers of photolithography process is performed with the application of selective liquid phase deposition.

Abstract: In a field intensity relaxation of the drain end of a MOSFET, a projective area is not increased with a reduced electrostatic coupling of the source or drain with the gate. The MOSFET satisfying such condition is fabricated on the SOIS film formed by processes of the lateral vapor phase epitaxial growth and the like. A U-shape low concentration impurity region is provided on a gate electrode through a gate dioxide film and high concentration impurity regions are formed at the tops of protrusions. The gate electrode is embedded in insulation films, and the transistor region is fabricated by the lateral vapor phase epitaxial growth and the like.

Abstract: In a field intensity relaxation of the drain end of a MOSFET, a projective area is not increased with a reduced electrostatic coupling of the source or drain with the gate. The MOSFET satisfying such condition is fabricated on the SOIS film formed by processes of the lateral vapor phase epitaxial growth and the like. A U-shape low concentration impurity region is provided on a gate electrode through a gate dioxide film and high concentration impurity regions are formed at the tops of protrusions. The gate electrode is embedded in insulation films, and the transistor region is fabricated by the lateral vapor phase epitaxial growth and the like.

Abstract: A method for producing a semiconductor laser device includes the steps of: forming window layers on either one of a top surface of an internal structure or a reverse surface of a substrate and on light-emitting end facets of the internal structure; forming a reflection film on the light-emitting end facets; removing the window layer formed on either one of the top surface or the reverse surface by using an etchant which hardly etches the reflection film; and forming electrodes on the surface from which the window layer is removed by etching and on the other surface. Another method for producing a semiconductor laser device includes the steps of: forming window layers on light-emitting end facets of the bars; inserting the bars into an apparatus having openings for forming electrodes and a supporting portion for preventing a positional shift between the bars and the openings, and forming the electrodes on the top surfaces and the reverse surfaces of the bars; and cutting the bars into the chips.

Abstract: In a method of manufacturing an optical semiconductor element including at least the steps of forming a mask having a stripe-like gap or interval on a semiconductor substrate, epitaxially growing a semiconductor ridge including an active layer on only an exposed gap portion of the semiconductor substrate, and epitaxially growing a semiconductor cladding layer to cover the ridge, the thickness of the active layer is substantially the same as the width of the active layer.

Abstract: A process is provided for forming a bipolar transistor and a structure thereof. In particular a single polysilicon self-aligned process for a bipolar transistor having a polysilicon emitter is provided. A sacrificial layer defining an opening is provided in a device well region of a substrate, and, after forming a self-aligned base region within the opening, emitter material is selectively provided in the opening to form an emitter-base junction. The sacrificial layer functions as a mask for ion implantations to form the base region, and if required, an underlying local collector region. The sacrificial layer is removed, to expose the well region adjacent sidewalls of the emitter structure. A self-aligned link region implant may be performed before forming isolation on exposed sidewalls of the emitter structure. Extrinsic base contacts are formed in the surface of the surrounding well region.

Abstract: The invention pertains to the field of fabrication, by vapor phase deposition, of the thin layers of monocrystalline, polycrystalline or amorphous material on a substrate having an identical or different nature. The aim is to provide a method, enabling this structure to be made, that includes a modulation of both the composition and the doping, in a direction that is not perpendicular to the surface of the substrate, notably in a lateral way to obtain a planar technology. According to the invention, this thin layer is made by conformal epitaxy, using a crystalline seed in gas phase, between two confinement layers made of a distinct material in such a way that there can be neither nucleation nor deposition of semiconductive material on the surfaces of said confinement layers and wherein the variation of the gaseous mixture of said gas phase is controlled to obtain said modulation of the composition and/or of the doping of said thin film.

Abstract: A III-V group compound crystal article comprises a substrate having a non-nucleation surface with smaller nucleation density (S.sub.NDS) and a nucleation surface (S.sub.NDL) which is arranged adjacent to said non-nucleation surface (S.sub.NDS), has a sufficiently small area for a crystal to grow only from a single nucleus and a larger nucleation density (ND.sub.L) than the nucleation density (ND.sub.S) of said non-nucleation surface (S.sub.NDS) and is comprised of an amorphous material, and a III-V group compound monocrystal grown from said single nucleus on said substrate and spread on said non-nucleation surface (S.sub.NDS) beyond said nucleation surface (S.sub.NDL).

Abstract: A semiconductor device which includes an electrode portion formed on a wafer; a passivation film deposited on said wafer except for said electrode portion; an insulating film deposited only on said passivation film so as to have a predetermined thickness and so as to include a concave portion over said electrode portion; and conductive material embedded in said concave portion at least up to the height of said insulating film, wherein the conductive material is intended to be used for bonding to a substrate.

Abstract: Disclosed is a method for the growing of heteroepitaxial layers of monocrystalline semiconductor materials. To this end, on a substrate made of a material of a first type, there is made a seed of a second type of material. This seed is between a face of the substrate and a confinement layer which defines a confinement space with the face of the substrate. A vapor phase epitaxy of a material of the second type is then effected in the confinement space. This material of the second type grows from the seed in the confinement space. The method can be applied to the manufacture of heterogeneous semiconductor structures and to the three-dimensional integration of semiconductor components.

Abstract: A method for fabricating an optical semiconductor device includes the steps of forming at least two stripes of dielectric parallel to each other with a predetermined interval on a semiconductor substrate, growing a crystal selectively between the two stripes, and forming a multi-layer structure which is required to have a width determined by the crystal grown between the two stripes. In such a method, the width of the multi-layer structure including an active layer or a waveguide is controlled precisely, because there is no step of etching a semiconductor layer, so that the characteristics of the device may improve and the yield may increase.

Abstract: A bi-polar transistor structure in a superhigh speed logic integrated circuit, and a process for producing the same are disclosed. The transistor has a substantially coaxial symmetric structure. Single crystal active layers as base and collector regions have peripheries surrounded wholly or partially by respective polycrystalline electrode layers. The polysilicon electrodes have lateral portions and downward depending portions that connect to single crystal layers. The polycrystalline electrode layers are separated from each other by insulation. One process for producing the structure uses only thin film forming techniques and etching techniques to dispose the active layers, an emitter electrode layer, parts of the other electrode layers and parts of the insulating layers inside a recess formed in an insulating layer formed on a substrate. Another process uses a photoetching technique by which polycrystalline layers for base and collector electrodes are patterned.

Abstract: The invention relates to such semiconductor devices comprising: a wiring layer with a predetermined pattern formed over a major surface of a semiconductor substrate through an insulating film, a diffusion layer formed under a contact hole formed in said insulating film in an adjacent region of the wiring layer, and a conductive layer deposited into said contact hole in a state of being connected to said wiring layer.

Abstract: Several methods are disclosed for minimizing the number of defects or misfit locations in a SiGe layer selectively or non-selectively deposited on a partially oxide masked Si substrate.

Abstract: A method of filling a recess so that it is flat with a material by a bias ECR-CVD process is capable of depositing the recess with the material without resulting in the increase in the aspect ratio of the recess with the progress of the deposition process and without forming any voids in the material filling up the recess. A method in accordance with the present invention is characterized in that the bias ECR-CVD process is controlled so as to meet a condition expressed by: R=2y/x, where R is the deposition rate ratio, namely, the ratio of a vertical deposition rate at which the material is deposited on the vertical side surface of the recess to a deposition rate at which the material deposited on the horizontal bottom surface of the recess, x is the width of the recess and y is the depth of the recess.

Abstract: A process for growing selective epitaxial layers on a silicon substrate. In a epitaxial growth reactor, hydrogen and the reactive gasses, the silicon source gas and hydrochloric acid, are introduced. The amount of silicon to free hydrochloric acid is controlled to be about 1:6 during the growth process and then turned off, the hydrogen remaining on. The resulting epitaxial layer may be grown over one micron in thickness with less than 0.1 micron of faceting. Further, a etchant of H.sub.2 O and HF diluted in NHO.sub.3 is first used to remove surface damage on the silicon substrate prior to epitaxial layer growth.

Abstract: A polysilicon self-aligned transistor has a polysilicon layer (24) with a cavity (30) formed therein. To form the polysilicon layer (24) with a cavity (30), a thin seed layer (14) is disposed over an epitaxial layer (11a). Dielectric layers (16, 18) are formed over the seed layer (14), and are subsequently etched to define the polysilicon layer (24) and the cavity (30). The cavity (30) is defined by a dielectric plug (22). The exposed seed layer (14) is used to selectively grow the polysilicon layer (24). Thereafter, the dielectric plug (22) is removed to form the cavity (30) through which the base (32) is implanted into the substrate (12) and the emitter (36) is formed.

Abstract: A method of producing patterned epitaxial silicon films and devices fabricated thereby is described. The method forms a first layer of a refractory material on a substrate and pattern delineates the first layer. Silicon is then deposited at a temperature within the range between 400 degrees C. and 700 degrees C. and the polycrystalline material that forms is removed.

Abstract: A semiconductor device includes a semiconductor layer, an insulating layer on the semiconductor layer, including a discontinuity therein, a monocrystalline silicon layer on a portion of semiconductor layer defined by the discontinuity, a non-monocrystalline silicon layer on the monocrystalline silicon layer, and a wiring layer on the non-monocrystalline silicon layer.

Abstract: A method of growing a GaAs crystalline layer on a Si substrate by means of which mechanical stresses causing microcracks in the materials when cooled due to the difference in their thermal coefficients are reduced and the location of the microcrack is controlled to predetermined sites. Microcracks are deliberately induced in the GaAs layer at locations where the operation of the ultimate electronic device created on the material is not affected by applying to the substrate a SiO.sub.2 mask providing a deposition opening or window for the GaAs layer, which masks defines along the opening boundary at least one vertex in the cleavage direction of the GaAs crystals. The vertices in the mask create notches in the periphery of the deposited layer which determines the location of any microcracks.

Abstract: Fine featured devices are produced by a series of fabrication steps including exposing selective surface regions to irradiation, e.g. to an ion beam, generally to result in removal of masking material within irradiated regions. In most instances, subsequent etching is under conditions such that bared material is preferentially removed. Etch-removal and irradiation are such that overgrown material is of device quality at least in etched regions. The inventive process is of particular value in the fabrication of integrated circuits, e.g. circuits performing electronic and/or optical functions. The inventive process is expediently used in the fabrication of structures having minimum feature size of 1 micrometer and smaller. Patterning is dependent upon masking material of a maximum thickness of 100 .ANG..

Abstract: A vertical transistor device is characterized by active regions vertically separated by a narrower control region. The control region is defined by conducting layer extensions which extend into a groove within which semiconductor material is regrown during device fabrication. The device is further characterized by regions of isolating material, located horizontally adjacent to the active regions, said isolating material serving to reduce parasitic capacitance and improve thermal distribution within the device, thereby improving frequency and power performance.

Abstract: A method of manufacturing a semiconductor device having a semiconductor substrate of a first conductivity type, an N-type diffusion layer formed in the substrate, and a P-type diffusion layer formed in the substrate. Two contact holes are formed in separate steps, thus exposing the N-type diffusion layer and the P-type diffusion layer, respectively. Hence, when one of the diffusion layers is again doped with an impurity, or again heat-treated, the other diffusion layer is already protected by inter-layer insulation film. Therefore, the impurity cannot diffuse into the contact formed in the contact hole made in the other diffusion layer. As a result of this, SAC technique can be successfully achieved, without deteriorating the characteristic of the contact.

Abstract: In the monolithic integration of HFET and DOES device, a wide band gap carrier confining semiconductor layer is provided only at predetermined locations where DOES devices are desired. This layer is not provided at other predetermined locations where HFET devices are desired as it would constitute a shunt path which would degrade the high frequency operation of the HFET devices. The invention is particularly useful where monolithic integration of optical sources, optical detectors, and electronic amplifying or switching elements is desired.

Abstract: A method of etching and regrowing III-V compounds in a sharply defined vertical feature. Molecular beam epitaxy is used to grow a laterally undefined vertical-cavity, surface-emitting diode laser structure from semiconducting III-V materials. The structure includes interference mirrors defining the end of a Fabry-Perot cavity and a quantum-well layer in the middle of the cavity. A tungsten mask is then defined over the areas of the intended two-dimensional array of lasers. A chemically assisted ion beam etches through to the bottom of the laser structure to from an array of high aspect-ratio pillars. A thermal chlorine gas etch removes a portion of the sidewalls of the pillars without attacking the tungsten, thereby removing ion-beam damage at the sides of the vertical-cavities and creating a lip of the tungsten mask overhanging the pillar sidewall. Organo-metallic chemical vapor deposition is used to regrow III-V material around the pillars. This growth process can quickly planarize the pillars.

Abstract: According to this invention, a first cladding layer of a first conductivity type, an active layer, a second cladding layer of a second conductivity type, and a cap layer much more susceptible to side etching than the second cladding layer susceptible to side etching than the second cladding layer are sequentially grown on a (100) crystal plane of a semiconductor substrate of the first conductivity type, and a stripe-like mask extending in a <011> direction is formed on the grown substrate with respect to each layer of the stacked substrate. This etching is performed in a crystal orientation for forming a reverse triangular mesa. However, since the cap layer is made of a material susceptible to side etching, a rounded mesa is formed. Thereafter, when a burying layer is formed on the etched portion by a vapor phase epitaxy method, the burying layer can be made to have a flat surface depending on crystal orientations.

Abstract: A method of manufacturing a bipolar transistor having a base lead-out electrode provided so as to surround an emitter region to be formed on a main surface of a semiconductor substrate and also having an emitter lead-out electrode provided along a stepped shape of the base lead-out electrode and connected to said emitter region is characterized by forming a first silicon film selectively only in an area surrounded by the base lead-out electrode. Impurity is introduced into the first silicon film and then diffused into the main surface of the semiconductor substrate to form the emitter region. Finally, a second silicon film is formed on the first silicon film to serve as the emitter lead-out electrode.

Abstract: This is a method of fabricating a high-performance semiconductor device. The method comprises: forming a first insulating structure, preferably a layer of silicon nitride (e.g. region 24 in FIG. 2) on a layer of thermally grown oxide (e.g. region 22), on a substrate (e.g. region 20), preferably silicon; patterning and anisotropically etching the first insulating structure to expose a portion of the substrate and sidewalls of the first insulating structure; forming a second insulating structure, preferably a layer of oxide (e.g. region 28 in FIG. 3) on a layer of nitride (the bottom second insulating layer is preferably an etch-stop layer with respect to the removal of the top second insulating layer) (e.g. region 26 in FIG. 3), on the patterned first insulating structure, along the sidewalls of the first insulating structure, and on the exposed semiconductor substrate; anisotropically removing portions of the second insulating structure leaving a sidewall region of the second insulating structure (e.g.

Abstract: The thin buffer layer, very often present in HIMOS devices, is achieved by ion implantation or predeposition of the dopant followed by subsequent diffusion.

Abstract: On a semiconductor substrate, a thin insulating film to be used as a gate insulating film, a thin polysilicon film and a thick mask layer are formed in the order and an opening for gate electrode formation is formed in the mask layer. After an ion implantation of impurities having the same conductivity type as that of the substrate is performed thereto through the opening to form, in the substrate, an impurity region having the same conductivity type as and impurity density larger than that of the substrate, the opening is filled with electrically conductive material. Thereafter, the mask layer is removed and an exposed first polysilicon film is removed to form a gate electrode comprising the conductive material and an underlying portion of the polysilicon film. Then, source region and drain region are formed in self-aligned manner with respect to the gate electrode.

Abstract: A method of forming low-resistive contact to at least two preohmic regions formed in a silicon substrate having a thick insulating layer thereon, including the steps of depositing a polysilicon on the insulating layer, performing an anisotropic etch for opening the preohmic regions, sputter-depositing a titanium deposit, the deposited titanium having electrical disconnections on the vertical side-walls of the opening regions, siliciding the titanium deposit, and depositing a metal silicide deposit for preventing electrical disconnections. Another embodiment uses a sputter-deposited titanium silicide deposit instead of titanium silicide. Still another embodiment includes the step of forming holes by an anisotropic etch, depositing polysilicon in the holes and on the insulating layer, sputter-depositing an titanium deposit, forming an titanium silicide deposit, and depositing a metal silicide deposit.

Abstract: Electrical connection to a device region (3,4) of a semiconductor device is formed by providing a semiconductor body (1) having adjacent one major surface (12) a device region (3,4) bounded by an insulating region (19a,19b,9), providing an activating layer (11) on the one major surface (12), applying a flowable material as a layer (13) of photosensitive resist, exposing and developing the resist to define an opening (14) over a contact area (12a) of the device region (3,4), and selectively plating electrically conductive material into the opening (14) to form a conductive pillar (15) in electrical contact with the contatct area (12a). The layer (13) of photosensitive resist is removed after formation of the conductive pillar (15) and a layer of insulating material is then provided to cover the conductive pillar (15) and the surface (12). The insulating layer is then etched to expose a top surface (15a) of the conductive pillar (15).

Abstract: A method for manufacturing a semiconductor device includes forming contact holes in insulating layers to expose an impurity doped region of a semiconductor substrate. An epitaxial layer is then grown in the contact hole. A polycrystalline silicon layer is formed over the top to provide the lower electrode of a capacitor. Accordingly, the polycrystalline layer is separated from the impurity doped region thereby preventing current leakage.

Abstract: This invention is directed to a method of epitaxial growth by metal organic vapor phase epitaxy (MOVPE) of Group III-V compound semiconductors in a hot wall reactor. Epitaxy is accomplished by use of precursors having a metal, an organic ligand, and an inorganic ligand. The system is operated at very low pressures to provide a high throughput of wafers and a highly uniform deposition growth. The invention is further directed to the use of the class of precursors to selectively grow III-V compounds on a masked substrate, wherein growth occurs epitaxially on the exposed areas of the substrate but not on the surrounding mask.

Abstract: A method is disclosed for forming a shorting contact for shorting P-type and N-type conductivity regions in a semiconductor together. In one embodiment of this method, the P-type region is substantially a square and is surrounded by the N-type region. A substantially square contact opening is made to expose the P-type region and a portion of the N-type region. Sides of the contact opening are formed to be at substantially 45 degree angles with respect to sides of the substantially square P-type region. In this manner, the alignment tolerance for forming the contact opening is less critical than if the sides of the contact opening were parallel to the sides of the P-type region. The contact opening is then filled with a conductive material to electrically short the P-type region to the N-type region. The conductivity types in this example may be reversed.

Abstract: A permeable base transistor (30) including a metal base layer (34) embedded in a semiconductor crystal (32) to separate collector (38) and emitter (40) regions and form a Schottky barrier with each is disclosed. The metal base layer has at least one opening (37) through which the crystal semiconductor (32) joins the collector (38) and emitter (40) regions. Ohmic contacts (42,44) are made to the emitter (38) and collector (40) regions. The width of all openings (37) in the base layer (34) is of the order of the zero bias depletion width corresponding to the carrier concentration in the opening. The thickness of the metal layer (34) is in the order of 10% of this zero bias depletion width. As a result, a potential barrier in each opening limits current flow over the lower portion of the bias range.

Abstract: A semiconductor laser includes, serially disposed, a semiconductor substrate of a first conductivity type, a semiconductor current blocking layer of a second conductivity type opposite the first conductivity tyupe, a first semiconductor cladding layer of the first conductivity type, an active semiconductor layer, a second semiconductor cladding layer of the second conductivity type, and a semiconductor contacting layer of the second conductivity type, and a structure for laterally confining the transverse flow of electrical current through the layers, the structure including a portion of the first cladding layer being disposed in a longitudinal groove extending through the current blocking layer into the substrate and high resistance longitudinal stripes disposed adjacent the groove between the second cladding layer and the current blocking layer, the high resistance stripes forming discontinuities in the active semiconductor layer.

Abstract: A method for fabricating a semiconductor device comprises the steps of forming the first semiconductor layer on a semiconductor substrate, forming a surface protection layer of antimony (Sb) or the material having Sb as its main component, executing the other steps necessary for the fabrication of the semiconductor device, removing the surface protection layer, and forming, on the first semiconductor layer thus exposed, the second semiconductor layer.

Abstract: Selective growth of GaAs and related semiconductors (34) by use of tungsten silicide and related materials for growth masks (36) plus devices incorporating the selective growth plus use of the growth masks as electrical contacts are disclosed. The deposition of semiconductor (38) on such masks (36) is inhibited and single crystal vertical structures (34) grow on unmasked regions of the lattice-matched substrate (32). Variation of the mask (36) composition can vary the inhibited deposition on the mask (36) from small isolated islands of polycrystalline semiconductor (38) to a uniform layer of polycrystalline semiconductor abutting the single crystal structures. Preferred embodiments include bipolar transistors with the selectivity grown structure forming the base and emitter or collector and the mask being the base contact and also include lasers with the vertical structures including the resonant cavities with the mirros being the sidewalls of the vertical structures.

Abstract: A CMOS and bipolar fabrication process wherein a silicon dioxide layer initially formed over a silicon substrate is etched for forming separate collector and base/emitter regions for a bipolar device, and PMOS and NMOS regions for corresponding PMOS and NMOS devices. Buried layer implants are performed using a minimum number of masks, and then an epitaxial layer is grown over the exposed portions of the silicon substrate. The silicon dioxide walls between the devices provide full dielectric isolation between the devices, as well as between the collector and base/emitter regions of the bipolar device. Nonetheless, the oxide wall between the collector and base/emitter of the bipolar device is sufficiently small to allow the buried layer implants to joint under the wall for forming a conventional buried layer for the bipolar device. Because of the oxide walls, the minimum distance between devices may be 0.5 microns or less.

Abstract: A photoelectric conversion apparatus comprising a transistor having a main electrode area of one conductive type semiconductor and a control electrode area of an opposite conductive type semiconductor, and a capacitor for controlling the potential of the control electrode area in floating state in which carriers produced optically are stored in the control electrode area by controlling the potential of the control electrode area via the capacitor. The apparatus comprises a multilayered structure in which switching device for setting the control electrode area to a desired potential is formed on a layer different from that on which the transistor and capacitor are formed.

Abstract: In a method for the fabrication of a layer of a monocrystalline semiconducting layer on a layer of insulating material, an epitaxial growth is achieved in a cavity closed by layers of dielectric material, using a seed of monocrystalline semiconducting material of a substrate. The growth takes place first of all, vertically, perpendicularly to the seed, and then horizontally in the plane of the cavity. This method thus enables a three-dimensional integration of semiconductor components.

Abstract: A process is disclosed for the fabrication of semiconductor devices which yields a device having a very short effective channel length and having polycrystalline source and drain electrodes. In accordance with the disclosed process, a semiconductor substrate is provided having a masking element positioned on the substrate surface. A layer of polycrystalline silicon is deposited on the exposed areas of the substrate surface by the process of selective deposition. The selectively deposited polycrystalline silicon is doped with conductivity determining impurities and that impurity material is thereafter redistributed to dope the underlying substrate to form source and drain regions. The masking element is removed to expose the portion of the semiconductor surface between the source and drain regions and to allow for a subsequent optional channel implantation.

Abstract: A process for making a thyristor device protected against breakover firing is to generate in the semiconductor body (1) of the thyristor an area (A) which has a lower breakdown voltage than the rest of the semiconductor body. This area is protected by suitable measures when the thyristor is overloaded. The invention features a process in which the area (A) of the semiconductor body (1) is irradiated locally with protons, with the proton energy being measured in such a manner that the maximum of the defect density and doping generated by the proton irradiation lies between the PN junction (15) of the first base region (9) and the second base region (10) and the half thickness of the second base region (10), and the semiconductor body (1) is subsequently heat-treated.

Abstract: Proposed is a method of fabricating semiconductor devices involving vapor etching of channels and/or growth of layers in a substrate. The etch or growth rate is controlled by opening up additional regions in the mask which are separated from the opening used to define the active region. The etching or growth in the additional exposed regions of the substrate consumes a certain amount of reactant and controllably reduces the amount available for etching or growth in the active region.

Abstract: A semiconductor body (1) is provided by growing epitaxial layers of semiconductor material on a substrate placed within a processing chamber and forming a mesa structure (3) on an upper epitaxial layer (2). The mesa structure (3) is formed by epitaxially growing, with the semiconductor body (1) still within the processing chamber, a first layer (4) of a semiconductor material different from that of the upper layer (2) on the upper layer (2) and the opening a window (5) in the first layer (4) to expose an area (2a) of the upper layer (2). A further layer (6) of a semiconductor material different from that of the first layer (4) is then epitaxially grown on the first layer (4) and on the said area (2a) of the upper layer. The first layer (4) is then selectively etched so as to remove the first layer (4) and the part of the further layer (6) carried by the first layer ( 14) leaving the remainder (60a, 60b) of the further layer (6) in the window (5) to form the mesa structure (3).

Abstract: A method of manufacturing a semiconductor device in which a silicon layer (8) is epitaxially grown on the surface of a doped monocrystalline semiconductor body (7), whereafter a connection is established between said semiconductor body (7) and a second semiconductor body (1) which is used as a supporting body, while at least one of the surfaces of the two bodies is firstly provided with an insulating layer (2,3) and a rigid connection is established between the bodies, whereafter the monocrystalline semiconductor body (7) is electrochemically etched away down to the epitaxially grown silicon layer (8), parts of the insulating layer (2,3) being removed prior to establishing the connection between the bodies (1,7), whereafter a layer of electrically conducting material (6) is deposited on the surface with a thickness which is larger than that of the insulating layer, whereafter a polishing treatment is performed at least down to the insulating layer.

Abstract: A method for simultaneously forming an epitaxial silicon layer on a surface of a silicon substrate, and a polysilicon layer on a silicon dioxide (SiO.sub.2) layer which is formed on the silicon substrate using a low pressure silicon vapor deposition method, employing silicon hydride gas, particularly disilane (Si.sub.2 O.sub.6), as a silicon source gas. A crystal growing temperature ranging from 780.degree. C. to 950.degree. C. and a reaction gas pressure ranging from 20 Torr to 300 Torr are desirable. An extended silicon epitaxial region is achieved under a higher temperature and a higher gas pressure, and with a substrate of a (100) orientation. A polysilicon layer having an even surface and joining smoothly to an epitaxial silicon layer which is simultaneously formed, is obtained under a lower temperature and a lower gas pressure, and with a substrate of a (111) orientation.

Abstract: A method for selectively depositing amorphous or polycrystalline silicon wherein a wafer having exposed silicon regions thereon is placed into a CVD reactor and subjected to a silicon containing gas and a halogen containing gas, at least one of which flows into the reactor with a hydrogen carrier gas. Amorphous silicon may be selectively deposited in the range of approximately 200 to 550 degrees centigrade while polycrystalline silicon may be selectively deposited in the range of approximately 550 to 750 degrees centigrade. It is also possible to deposit polycrystalline silicon at temperatures in the range of approximately 750 to 1000 degrees centigrade by employing another embodiment of the present invention.

Abstract: A method for manufacturing a surface emitting type AlGaAs/GaAs semiconductor LASER diode by a selective epitaxy method which is capable of forming naturally a 45.degree. mirror reflective face during the epitaxy method itself. The method comprises the steps of forming a silicon oxide or silicon nitride layer on one side of a n-type single crystal GaAs substrate as a mask, removing the mask of the regions each for forming a 45.degree. mirror reflective face and a LASER diode by use of a photolithography and a chemicaletching, forming the two layers by removing the photoresistor on the remaining mask after a selective epitaxy process and converting a slant face of the LASER diode into a vertical face, depositing a n-type metal layer on the other side of the substrate, and carrying out a heat treatment.