Abstract: A process for forming individual dies having faces that allow the dies to be assembled against other like dies to form one and/or two dimensional scanning arrays wherein the active side of a wafer is etched to form small V-shaped grooves defining the die faces, relatively wide grooves are cut in the inactive side of the wafer opposite each V-shaped groove, and the wafer cut by sawing along the V-shaped grooves, the saw being located so that the side of the saw blade facing the die is aligned with the bottom of the V-shaped groove so that there is retained intact one side of the V-shaped groove to intercept and prevent cracks and chipping caused by sawing from damaging the die active surface and any circuits thereon.

Abstract: A method for limiting chippage when sawing a semiconductor wafer into individual pieces which involves providing a dielectric layer at least in some portions of the wafer surface. A border of the dielectric layer is applied to the margins of the individual parts which are to be formed on the surface of the semiconductor wafer, being applied under such conditions that the margins exert a tensile stress on the semiconductor surface. This produces a symmetrical tensile stress distribution for limiting the chippage of the semiconductor material in the sawing region on the surface of the semiconductor wafer.

Abstract: A flat LED panel display with LED elements arranged in a high density and a method of producing such a display are disclosed. A conductive layer is deposited on a ceramic substrate and bonded to one surface of an LED wafer by a conductive paste. A plurality of electrodes are arranged on the other surface of the LED wafer in rows and columns to define a two-dimensional pattern. Slits are formed along the rows or the columns each to a depth which extends from the other surface of the LED wafer to the ceramic substrate. Other slits are formed perpendicular to the first-mentioned slits each with a depth which extends from the other surface of the LED wafer to a position deeper than it but short of the ceramic substrate.

Abstract: A method of making an optically coupled semiconductor laser having cleaved facing end walls and precise alignment and spacing. An indium coated face of a semiconductor laser diode bar is placed on an indium coated support. A knife edge cleaves the bar into two closely spaced and aligned semiconductor diode laser bodies and concurrently cold bonds them to the support. The knife edge is used without deleteriously affecting their bonding to the support.

Abstract: A method of dicing a semiconductor wafer in which a physical discontinuity is formed on the surface of the wafer on both sides of a dicing line to limit the spreading of cracks and chips generated during dicing. Thereafter, the semiconductor wafer is diced to separate the pellets.

Abstract: A wafer divided into rows of abutted end-to-end dice (i.e., semiconductor chips) is placed on a thin, non-elastic membrane and drawn tightly over a knife-edge to successively separate each row of dice from the membrane. The dice are then attached to individual leadframes directly or are picked up by a vacuum fixture and carried to a position where they are secured to the leadframes and are wire bonded. After bonding, the components are assembled into finished subassemblies. In one embodiment, LED lamps are fabricated. A reflector is secured to each leadframe over the die positioned thereon, and the leadframe, die and reflector are molded into a lamp subassembly, which is used to form a larger lamp or display fixture.

Abstract: Small scale integrated chips are fabricated from a semiconductor wafer and subsequently pretested and formed into large area arrays with self aligning and self locking characteristics due to the axial orientation of the semiconductor wafer and geometries employed for the chips based upon the wafer orientation, whereby the spacing of abutting chip edges in an array may be less than 7 .mu.m. The chips are fabricated from <110> axial wafer, e.g., silicon <110> axial wafer, wherein the chip boundaries are aligned with vertical {111} planes of the crystalline material so that each of the chips formed from the wafer may be defined within parallelogrammatic like geometries defined by these planes and their intersections. The term "parallelogrammatic like geometries" means all geometric shapes capable of being formed with various vertical {111} planes within the crystalline structure of the wafer.