Abstract: Reduction in the net charge at the interface of a dielectric and a semiconductor material is achieved by placing atomic species in the dielectric near the interface. Preferably, these species are selected from the group of alkaline earth metals. The presence of these atoms results in a redistribution of the electronic density near the interface. The placement of the atoms is effected by ion implantation followed by multiple annealing steps at alternating low and high temperatures.

Abstract: A manufacturing method for high quality GaN-based light emitting devices. The method enable effective growth of an Al.sub.y Ga.sub.1-y N (0.ltoreq.y.ltoreq.1) layer on an In.sub.x Ga.sub.1- N (0.ltoreq.x.ltoreq.1) layer by CVD. While holding or increasing the temperature after growing the InGaN layer at the temperature of T0 before growing the AlGaN at the temperature of T1 (T0.ltoreq.T1) in an atmosphere including a source of group V of elements, the present invention applies an inert gas as the carrier gas which includes a source of the group V elements. Therefore, the concentration of group V elements near the surface of the InGaN layer increases and the sublimation of the InGaN layer is prevented by increasing the steam pressure of the group V elements near the surface of the InGaN layer.

Abstract: A magnetostrictive element for use in a magnetomechanical marker has a resonant frequency characteristic that is at a minimum at a bias field level corresponding to the operating point of the magnetomechanical marker. The magnetostrictive element has a magnetomechanical coupling factor k in the range 0.28 to 0.4 at the operating point. The magnetostrictive element is formed by applying current-annealing to an iron-nickel-cobalt based amorphous metal ribbon, or by cross-field annealing an iron-nickel-cobalt alloy that includes a few percent chromium and/or niobium.

Abstract: Transistor drive current is controlled by controllably varying light exposure across a semiconductor substrate wafer based on an integrated circuit parameter. Integrated circuit parameters upon which the light exposure is varied include gate oxide thickness, rapid temperature annealing (RTA) temperature, polyetch bias and the like.

Abstract: A method of direct-bonding semiconductor wafers limits the time interval between a bonding step and a bonding anneal step or performs a baking step between the bonding and bonding anneal steps at a predetermined temperature for a predetermined time interval to prevent the formulation of voids on the edge regions of the wafers. The method for fabricating laminated semiconductor wafers includes a bonding step to fit together two polished semiconductor wafers by bonding jigs, and a succeeding bonding anneal step to laminate the wafers. In the method the bonding anneal step is preferably carried out within an hour following the bonding step; or a baking step at a predetermined temperature for a predetermined time interval is carried out between the bonding step and the bonding anneal step. Further, the method can prevent heavy metal impurities attached to the surface of the wafer from diffusing into the wafer by baking the wafer for over 5 minutes at above 100.degree. C.

Abstract: A method for accurately and objectively evaluating stress migration effects on long term reliability of integrated circuits. A sample containing a conductive runner is fabricated according to a given fabrication process. The fabricated sample undergoes a heating step at a first temperature for a first time period to induce material interactions at an accelerated rate, followed by cooling the sample to a second temperature and maintaining the second temperature for a time of sufficient duration such that relaxation occurs. Then the sample undergoes a heating process at a third temperature for a time sufficient to nucleate a predetermined number of voids, followed by heating the sample runner at a fourth temperature, less than than the third temperature, to propagate the voids such that a maximum void size is determined. Void distribution is preferably monitored by optical and scanning electron microscopy.

Abstract: A control element for a magnetomechanical EAS marker is formed of an amorphous metalloid that has been annealed so as to be at least partially crystallized while remaining substantially flat. The annealing is preferably a two-stage process applied to induce semi-hard magnetic characteristics in an amorphous metallic material that is magnetically soft as cast. The two stages include a first stage in which the material is annealed for at least one hour at a temperature that is below a crystallization temperature of the material. The first stage results in a reduction in the volume of the material. The second stage is carried out at a temperature that is above the crystallization temperature and for a time sufficient to crystallize the bulk of the material and give it semi-hard magnetic properties. The two-stage annealing process prevents deformation of the material which has resulted from conventional crystallization processes.

Abstract: A resonator for use in a marker, with a bias element which produces a bias field, in a magnetomechanical electronic article surveillance system is composed of an amorphous magnetostrictive alloy containing iron, cobalt, nickel, silicon and boron in quantities for giving the resonator a quality Q which is between about 100 and 600. The amorphous magnetostrictive alloy is annealed in a transverse magnetic field for giving it a B-H loop which is linear up to about 8 Oe and an anisotropy field strength of at least 10 Oe. When the resonator is excited to resonate by a signal emitted by the transmitter in the surveillance system, it produces a signal at a mechanical resonant frequency which can be detected by the receiver of the detection system. Due to the resonator having a quality Q in the above range, the signal produced by the resonator in a first detector window, beginning approximately 0.

Abstract: A p-i-n structure for use in photoconductors and diodes is disclosed, being formed of an Al.sub.x Ga.sub.1-x N alloy (X=0.fwdarw.1) with In.sub.y Ga.sub.1-Y N (Y=0.fwdarw.1) which as grown by MOCVD procedure with the p-type layer adjacent the substrate. In the method of the subject invention, buffer layers of p-type material are grown on a substrate and then doped. The active, confinement and cap layers of n-type material are next grown and doped. The structure is masked and etched as required to expose a surface which is ion implanted and annealed. A p-type surface contact is formed on this ion-implanted surface which is of sufficiently low resistance as to provide good quality performance for use in a device.

Abstract: A magnetostrictive element for use in a magnetomechanical article surveillance marker formed by first annealing an amorphous metal alloy, such alloy comprising iron and cobalt with the proportion of cobalt being in the range of about 5 to about 45 atomic percent, in the presence of a saturating magnetic field and then second annealing the alloy in the absence of the saturating magnetic field.

Abstract: Disclosed is a method of manufacturing a semiconductor device wherein a corpuscular beam is radiated to a semiconductor substrate to create crystal defects therein. The semiconductor substrate is subjected to a heat treatment, e.g. for 1 second to 60 minutes, wherein rapid heating-up, e.g. raising temperature to 550.degree. to 850.degree. C. within 10 minutes, is done in a process prior to that of carrying out of the radiation with a corpuscular beam. By doing so, there is provided a semiconductor device which is free from degradation in electrical characteristics such as current amplification factor and has an increased switching speed, even where crystal defects are created through the radiation of corpuscular beam such as an electron beam to shorten the carrier lifetime. Thus, the inventive semiconductor device is satisfied by both requirements of switching speed and electrical characteristic.

Abstract: Heteroepitaxy of lattice-mismatched semiconductor materials such as GaAs on silicon is accomplished by first growing GaAs (104) on silicon (102), then growing a lattice matched cap of Al.sub.z Ga.sub.1-z,As (106), next annealing out defects with the Al.sub.z Ga.sub.1-z As cap (106) limiting desorption of gallium, lastly growing further GaAs (110) directly on the cap. The lattice matched cap is also used as an implant anneal cap.

Abstract: A conductor fill technique uses an intermetallic compound wetting layer to allow a subsequent conductive material to be reflowed with minimized interaction between the conductive layer and the wetting layer. As one example, a wetting layer including TiAl or TiAl.sub.3 may be formed over a semiconductor wafer and in an opening of the wafer. A conductive layer including aluminum (Al) may then be deposited and reflowed over the wafer to fill the opening in forming a contact, via, or interconnect line, for example, with minimized interaction between the aluminum (Al) of the conductive layer and the wetting layer. Any reduction in conductance of the material filled in the opening may be minimized as the formation of any new intermetallic TiAl.sub.3 compounds that would otherwise increase the resistance of the material filled in the opening is minimized.

Abstract: To efficiently mass-produce back reflectors which are inexpensive and have high reflectivity, the invention provides a manufacturing method for a solar cell comprising at least a metal layer having a texture structure and high reflectivity, a transparent layer, a semiconductor layer, and a transparent electrode which are formed on a substrate, wherein the metal layer consists of at least two layers formed as a first metal layer and a second metal layer. The method includes a step of, after forming the first metal layer, annealing the first metal layer before forming the second metal layer. The invention also provides a solar cell manufacturing apparatus having, upstream of a second metal layer forming chamber, a heating chamber in which the first metal layer can be annealed.

Abstract: A process for growing semi-insulating layers of indium phosphide and other group III-V materials through the use of halide dopant or etchant introduction during growth. Gas phase epitaxial growth techniques are utilized at low temperatures to produce indium phosphide layers having a resistivity greater than approximately 10.sup.7 ohm-cm. According to the preferred embodiment carbon tetrachloride is used as a dopant at flow rates above 5 sccm to grow the layers with substrate growth temperatures ranging from approximately 460.degree. C. to 525.degree. C. This temperature range provides an advantage over the transition metal techniques for doping indium phosphide since the high temperatures generally required for those techniques limit the ability to control growth. Good surface morphology is also obtained through the growth according to the present invention. The process may be used to form many types of group III-V semiconductor devices.

Abstract: A process for forming a MOS transistor having a salicide structure with a second gate spacers 36 and a source/drain/gate contact pads 32 33. A gate electrode 18 having first sidewall spacers 24 is formed on a substrate. Source and drain regions 28 are formed in the substrate. An amorphous silicon layer is formed over the substrate and patterned leaving the amorphous silicon layer over first sidewall spacers 24 and forming source/drain contact pads 33 over the source/drain regions and gate contact pads 32 over the gate electrode. Nitrogen ions are implanted vertically into the amorphous silicon layer 32 forming a nitrogen rich layer 34. The nitrogen rich layer 34 acts as an oxidation barrier source/drain an gate contact pads. The amorphous silicon layer 28 over the first sidewall spacer is oxidized using the nitrogen rich layer 34 as an oxidation barrier forming second gate spacers 36. A Ti layer is formed over the resultant surface.

Abstract: A method is provided for improving the performance characteristics of the MOS devices contained within an integrated circuit that has been subjected to a rapid thermal anneal. After the rapid thermal anneal the integrated circuit is heated for more than about 30 minutes at a temperature of more than about 430.degree. C. in a gaseous atmosphere that contains hydrogen, typically forming gas.

Abstract: A monitor wafer used to determine the cleanliness of a wafer fabrication environment requires a surface having a minimum of light scattering anomalies so that contamination deposited by the environment is not confused with light scattering anomalies initially on the monitor wafers. In the present invention, ingots of a single-crystal semiconductor are grown at a reduced pull rate and wafers produced from the ingot are annealed within a preferred temperature range that varies with the pull rate to produce wafers having reduced light-scattering anomalies on their surfaces. The number of light-scattering anomalies increases at a slower rate upon repetitive cleaning cycles than does the number of light-scattering anomalies of prior art wafers.

Abstract: A two-step continuous annealing process is applied to an amorphous metal alloy ribbon. During the first annealing step, a saturating transverse magnetic field is applied, and the field is omitted during the second annealing step. After the two annealing steps, the material is cut into discrete strips suitable for use as active elements in pulsed-field magnetomechanical EAS markers. The resulting markers exhibit satisfactory total frequency shift and ring-down signal amplitude characteristics, without excessive sensitivity to bias field variations.

Abstract: In a heating method for semiconductor devices, gas is filled in a heat chamber in which a heat target (semiconductor device) is mounted, and then the gas is compressed to produce heat. The heat target is heated to a desired temperature by the produced heat. Before the gas compression is performed, the heat target is preferably pre-heated by a heater.

Abstract: A method of fabricating a self-aligned FET having a semi-insulating substrate of GaAs or InP with a conductive channel formed either by doping the surface or an epitaxially grown channel by molecular beam epitaxy or metalorganic vapor phase epitaxy in the substrate adjacent the surface. Forming a high temperature stable LaB.sub.6 /TiWN "T-shaped" Schottky gate contact on the substrate surface, which is used for source and drain ohmic region implants into the substrate adjacent to the surface and self-aligned to the "T-shaped" gate, with source and drain ohmic contacts also self-aligned with respect to the gate.

Abstract: Polycrystalline silicon thin-films having a large grain size are formed by preparing a substrate of amorphous surface comprising first regions containing tin atoms at a higher content and second regions containing tin atoms at a lower content or not substantially containing them, and then heat-treating the substrate to grow crystal grains from crystal nuclei formed only in the first regions.

Abstract: A method for enhancing aluminum nitride includes, in one version, annealing sputtered aluminum nitride in a reducing atmosphere (11), and subsequently annealing the sputtered aluminum nitride in an inert atmosphere (12). A superior aluminum nitride thin film (13) results. The films can withstand exposure to boiling water for times up to twenty minutes and maintain a refractive index, N.sub.f, greater than 2.0, and a preferred crystalline orientation ratio, I(002)/I(102), in excess of 1000.

Abstract: The present invention provides a method of manufacturing a semiconductor wafer whereby (1) deterioration of a micro-roughness in a low temperature range in hydrogen atmospheric treatment and increase of resistivity due to outward diffusion of an electrically active impurity in a high temperature range are prevented; (2) in the heat treatment in a hydrogen gas atmosphere, the concentration of gas molecules in the atmosphere, such as water, oxygen and the like, are brought to 5 ppm or less in water molecule conversion; and a reaction is suppressed in which a substrate surface is oxidized unequally and the micro-roughness deteriorates; and (3) the same kind of impurity as the electrically active impurity contained in a Si substrate is mixed into the atmosphere and the outward diffusion of the impurity in the vicinity of the Si substrate surface is prevented to prevent variation of the resistivity.

Abstract: In the manufacture of high temperature deposited aluminum contacts onto silicon substrates wherein a barrier layer of titanium nitride is used, the improvement wherein the titanium nitride contains oxygen. The improved contacts are made by depositing a titanium-containing layer onto a silicon substrate, performing a first, high temperature nitrogen anneal in vacuum to form a low resistance TiSi.sub.x contact to the silicon, and performing a second, lower temperature anneal in vacuum using a mixture of nitrogen and oxygen to stuff the titanium nitride layer. This stuffed titanium nitride layer provides an improved barrier to a subsequently deposited high temperature deposited aluminum layer.

Abstract: In a method of manufacturing a MOS device, of the type wherein an electrode film is deposited on a gate oxide film, after which a plurality of heat-treating steps are carried out in ambient gases and at a temperature range between 800.degree. and 110.degree. C., at least one of the heat-treating steps is carried out in a hydrogen atmosphere. The resultant MOS device has improved a time-dependent dielectric breakdown characteristics and maintained an improved time-zero dielectric breakdown characteristics which is comparable to that provided by the conventional hydrogen annealing.

Abstract: A ribbon-shaped strip of an amorphous magnetic alloy is heat treated, while applying a transverse saturating magnetic field. The treated strip is used in a marker for a pulsed-interrogation electronic article surveillance system. A preferred material for the strip is formed of iron, cobalt, silicon and boron with the proportion of cobalt exceeding 30% by atomic percent.

Abstract: A method for manufacturing a TFT of a SRAM in a highly-integrated semiconductor device, to enlarge the grain size of a polysilicon film, includes steps of depositing amorphous silicon film under a pressure capable of maintaining a uniform thickness thereof, and forming a polysilicon film which has a maximized grain size in the same tube that the amorphous silicon film has been deposited, while performing an annealing process by raising the temperature to 600.degree.-650.degree. C. for 4-10 hours under the pressure which is lowered to approximately 10.sup.-3 Torr. The polysilicon film having a maximized grain size is utilized as the channels of the TFT.

Abstract: A multi-layer structure, typically semiconductor device, is etched according to a process of the present invention, and meets the above-described existing needs by focusing on the post-etch treatment of the damaged, etched semiconductor device formed thereby. This post-etch treatment is accomplished by exposing the damaged silicon to a forming-gas downstream plasma which results in substantially increased oxide regrowth and significantly higher level of gate oxide quality. In conducting the process of the subject invention from about 1% up to about 15% by volume of H.sub.2, and from about 85 up to about 99% by volume of N.sub.2 are preferably employed as the post etching forming-gas plasma.

Abstract: The disclosed invention is a process for fabricating a semiconductor device comprising the steps of:forming a gate electrode;covering the gate electrode and surface of the substrate with a layer of silicon dioxide;etching the silicon dioxide layer using an RIE method and an HF etching method to form a sidewall of silicon dioxide against each side of the gate electrode;injecting ions into the substrate at an acceleration energy within the range of about 10-20 KeV to minimize crystalline defects in the substrate caused by ion injection;heating the entire substrate in two successive stages: (a) initially at a first temperature within the range of 700.degree.-850.degree. C. for approximately one hour to recover the crystallinity of the substrate damaged in the injecting step and to inhibit diffusion of impurities; and (b) then at a second temperature within the range of 900.degree.-1100.degree. C. for 5-15 seconds to form a shallow depth diffusion region in the substrate.

Abstract: Heteroepitaxy of lattice-mismatched semiconductor materials such as GaAs on silicon is accomplished by first growing GaAs (104) on silicon (102), then growing a lattice matched cap of Al.sub.x Ga.sub.1-x As (106), next annealing out defects with the Al.sub.x Ga.sub.1-x As cap (106) limiting desorption of gallium, lastly growing further GaAs (110) directly on the cap. The lattice matched cap is also used as an implant anneal cap.

Abstract: The present invention relates to a method for manufacturing a semiconductor device including a method for reforming an insulating film formed by a low temperature CVD method. It is an object of the present Invention to provide a method for manufacturing a semiconductor device capable of improving a film quality of an insulating film formed by a CVD method which is able to form a film at a low temperature and also capable of maintaining mass productivity, in which processing by irradiation with ultraviolet rays of the insulating film while heating the film after forming an insulating film (4) on a body to be formed by a chemical vapor deposition method is included.

Abstract: In the manufacture of high temperature deposited aluminum contacts onto silicon substrates wherein a barrier layer of titanium nitride is used, the improvement wherein the titanium nitride contains oxygen. The improved contacts are made by depositing a titanium-containing layer onto a silicon substrate, performing a first, high temperature nitrogen anneal in vacuum to form a low resistance TiSi.sub.x contact to the silicon, and performing a second, lower temperature anneal in vacuum using a mixture of nitrogen and oxygen to add oxygen to the titanium nitride layer. This oxygen-containing titanium nitride layer provides an improved barrier to a subsequently deposited high temperature deposited aluminum layer.

Abstract: A method of heat-treating a semiconductor wafer comprises: heat-treating a semiconductor wafer in an atmosphere of an inert gas which does not absorb infrared rays in a specific infrared region to determine heat-treating conditions that heat the semiconductor wafer in a desired temperature profile; and heat-treating a semiconductor wafer in an atmosphere of a process gas according to the previously determined heat-treating conditions. Since the inert gas used in predetermining the heat-treating conditions does not absorb infrared radiation in the specific infrared region corresponding to the infrared absorption range of the process gas, the temperature of the semiconductor wafer can be accurately measured by a pyrometer to determine the heat-treating conditions. In the practical heat treatment of a semiconductor wafer, the temperature of a semiconductor wafer can be accurately controlled according to the predetermined heat-treating conditions.

Abstract: A method for forming a ferroelectric capacitor for use an integrated circuit establishing one layer over another and then annealing the structure, using an oxygen or ozone anneal, after each layer is established. In particular, an ozone anneal is used after the establishment of a layer of ferroelectric material.

Abstract: A method of annealing a partially fabricated semiconductor device which comprises the steps of annealing a partially fabricated semiconductor device in an atmosphere of an inert gas and an oxidizing gas. The inert gas is preferably one of nitrogen and argon and the oxidizing gas is preferably one or more of oxygen, hydrogen chloride and nitrogen trifluoride. The oxidizing gas is from about 1 to about 10% by volume of the atmosphere. The annealing step comprises maintaining the partially fabricated semiconductor device at a first temperature, preferably about 700.degree. C., for a first time period, preferably about 20 minutes, ramping up the temperature at a rate to a second temperature, preferably about 800.degree. C., maintaining the second temperature for a second time period, preferably about 20 minutes, ramping up the temperature at a rate, preferably about 10.degree. C./minute, to a third temperature, preferably about 900.degree. C.

Abstract: A method of decoupling a step for modulating a defect density from a step for modulating a junction depth. A semiconductor substrate (30) having a portion doped with a dopant (34) is heated to a pre-oxidation anneal temperature in a pre-oxidation anneal step (23). After the pre-oxidation anneal step (23), the semiconductor substrate (30) undergoes an oxidation step (25) which serves as a step for modulating the defect density. Subsequent to the oxidation step (25), the semiconductor substrate (30) undergoes a drive-in step (27) which serves as a step for modulating the junction depth. Then, the temperature of the semiconductor substrate (30) is lowered to allow further processing of the semiconductor substrate (30).

Abstract: A method for manufacturing a III-V Group compound or a II-VI Group compound semiconductor element by VPE, comprising the step of annealing a grown compound at 400.degree. C. or higher, or irradiating electron beam the grown compound at 600.degree. C. or higher.

Abstract: An improved semiconductor processing is disclosed. In the manufacturing process, a semiconductor layer is formed and then undergoes photo annealing. A neutralizer is then introduced to the photoannealed semiconductor. The semiconductor thus formed demonstrates the SEL effect instead of the Staebler-Wronski effect.

Abstract: A high quality, narrow band gap, hydrogenated amorphous germanium or amorphous silicon alloy material characterized by a host matrix in which all hydrogen is incorporated therein in germanium monohydride or silicon monohydride form, respectively; their mobility-lifetime product for non-equilibrium charge carriers is about 10.sup.-8 and about 10.sup.-7, respectively; their density of defect states in the band gap thereof is less than about 1.times.10.sup.17 and about 2.times.10.sup.16 /cm.sup.3, respectively; and their band gap is about 1.5 and about 0.9 eV, respectively. There is also disclosed a structure formed from a plurality of very thin layer pairs of hydrogenated amorphous germanium and amorphous silicon alloy material, each layer pair of which cooperates to provide narrow band gap material.

Abstract: A heat-treating method for an indium-doped dislocation-free gallium arsenide monocrystal having a low carbon concentration and grown in the Liquid Encapsulated Czochralski method, comprising a two-step heat treatment:(i) heating the monocrystal at a temperature between 1050.degree. C. and 1200.degree. C. for a predetermined time length, and cooling the monocrystal quickly; and(ii) heating the monocrystal at a temperature between 750.degree. C. and 950.degree. C. for a predetermined time length, and cooling the monocrystal quickly.

Abstract: In a method of heating a semiconductor substrate according to the present invention, a predetermined atmospheric gas such as N.sub.2, O.sub.2 and H.sub.2, is sprayed onto the surface of an impurity layer formed by implanting ions into the main surface of the semiconductor substrate and, at the same time, the substrate is heated from a surface (interface of the impurity layer) opposite to the main surface, thereby annealing the substrate while keeping the temperature of the surface of the impurity layer lower than that of the interface. In this method, the temperature of the surface of the semiconductor substrate is made lower than that of the undersurface thereof so as to have a predetermined difference by the use of the cooling effect controlled by the flow rate of the atmospheric gas, and the semiconductor substrate is heated to have a gentle inclination of temperature in the substrate.

Abstract: A method for depositing a passivation layer on a semiconductor structure having a high resistance value polysilicon layer formed thereon while maintaining the high resistance value thereof and comprises sequentially depositing a silicon oxide layer and a silicon nitride layer, on a high resistance value polysilicon layer of a partially completed semiconductor structure to form a passivation layer thereover. The passivation layer including the silicon oxide layer and the silicon nitride layer is annealed with oxygen plasma in a chamber. The annealed passivation layer is then heated in the presence of a conditioning gas in the chamber to thereby maintaining the resistance of the high resistance value polysilicon layer.

Abstract: An improved semiconductor processing is disclosed. In the manufacturing process, a semiconductor layer is formed and then undergoes photo annealing. A neutralizer is then introduced to the photoannealed semiconductor. The semiconductor thus formed demonstrates the SEL effect instead of the Staebler-Wronski effect.

Abstract: A method of fabricating a metal-gate field effect transistor having source and drain regions which are self-aligned with the gate. The source and drain dopants are introduced into the substrate and driven. Then, a metal gate is formed, the metal gate having a length which is approximately the same as the length of the channel. After the gate is fabricated, dopant ions are implanted into any portions of the channel not covered by the gate. These dopant ions are activated by rapid thermal annealing at a temperature selected to avoid damage to the metal gate, to form bridge regions which extend one or both of the source/drain regions into the channel and which are self-aligned with the gate.

Abstract: A method of producing a GaAs single crystal substrate comprises the steps of conducting a first-stage annealing by vacuum-sealing a GaAs single crystal wafer and arsenic in a heat-resistant vessel and heating the wafer to a temperature of 1050.degree. to 1150.degree. C. while exposing it to arsenic vapor pressure, cooling the wafer to room temperature at a cooling rate of 1.degree.-25.degree. C./min., removing the wafer from the vessel, etching the wafer and placing it in another vessel, conducting a second-stage annealing by heating the wafer to a temperature of 910.degree. to 1050.degree. C. in a non-oxidizing atmosphere, cooling the wafer to room temperature at a cooling rate of 1.degree.-25.degree. C./min., removing it from the vessel, etching the wafer, conducting a third-stage annealing by vacuum-sealing the wafer and arsenic in the heat-resistant vessel and heating the wafer to a temperature of 520.degree.-730.degree. C. while exposing it to arsenic vapor, and cooling the wafer at least down to 400.

Abstract: Disclosed is a method of making a Si-based semiconductor device comprising a contact region that comprises a thin (exemplarily less than 50 nm), substantially uniform silicide layer. The silicide preferably is CoSi.sub.2 or TiSi.sub.2. The method comprises implantation of the appropriate metal ions into a Si body, the dose and the body temperature selected such that substantially complete amorphization of the implant volume results. Subsequently, the Si body is subjected to an annealing treatment that results in recrystallization of the implant volume and formation of the silicide layer. The layer extends to the surface of the body and contains essentially all of the implanted metal ions. The invention can advantageously be used in conjunction with extremely shallow junctions, such as will be of interest in short (e.g., <0.5 .mu.m) channel CMOS devices.

Abstract: Improvements to graphoepitaxy include use of irradiation by electrons, ions or electromagnetic or acoustic radiation to induce or enhance the influence of artificial defects on crystallographic orientation; use of single defects; and use of a relief structure that includes facets at 70.5 and/or 109.5 degrees.

Abstract: A method for fabricating a semiconductive device is described, wherein a semiconductive substrate having a thermally shrinkable, refractory metal silicide thin film is provided, on which an insulating film on the metal silicide thin film is formed. The metal silicide thin film is thermally treated in an atmosphere containing hydrogen. By this, no morphological degradation is observed in the silicide thin film without an increase of the resistance.

Abstract: Dislocation densities are reduced in growing semiconductors from the vapor phase by employing a technique of interrupting growth, cooling the layer so far deposited, and then repeating the process until a high quality active top layer is achieved. The method of interrupted growth, coupled with thermal cycling, permits dislocations to be trapped in the initial stages of epitaxial growth.